DS2188S Dallas Semiconductor, DS2188S Datasheet
DS2188S
Specifications of DS2188S
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DS2188S Summary of contents
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... Jitter attenuation is easily disabled § Single +5V supply; low-power CMOS technology § Available in 16-pin DIP and 16-pin SOIC (DS2188S) § Companion to the DS2186 Transmit Line and DS2187 Receive Line Interface DESCRIPTION The DS2188 T1/CEPT Jitter Attenuator Chip contains a 128 X 2-bit buffer which, in conjunction with an external 4X crystal, is used to attenuate the incoming jitter present in clock and data ...
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... DS2188 to RRCLK, RRPOS, and RRNEG. In this situation, the BL pin has no significance and XTAL OUT will not be coherent with RRCLK. How to use the DS2188 with Dallas Semiconductor’s other T1 and CEPT line interface parts is illustrated in Figures 3 through 5. Figure 3 illustrates how to use the DS2188 in the receive path along with a DS2187 Receive Line Interface. Figure 4 illustrates how to use the DS2188 in the transmit path with the DS2186 Transmit Line Interface. Also, see DS2188 Application Note, “ ...
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DS2188 TI JITTER ATTENUATION PERFORMANCE Figure 1 DS2188 CEPT JITTER ATTENUATION PERFORMANCE Figure DS2188 ...
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DS2188 IN THE RECEIVE PATH Figure 3 DS2188 IN THE TRANSMIT PATH Figure DS2188 ...
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PIN DESCRIPTION Table 1 PIN SYMBOL TYPE 1 DJA 2 RPOS 3 RNEG 4 RCLK 5 BDS 6 TEST 7 XTAL OUT XTAL1 10 XTAL2 RST 13 RRCLK 14 RRNEG 15 RRPOS 16 ...
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CRYSTAL REQUIREMENTS The DS2188 must have a crystal connected to the XTAL1 and XTAL2 pins. For T1 environments, the frequency of this crystal should be 6.176 MHz. For CEPT environments, the frequency of this crystal should be 8.192 MHz. Table ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the ...
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AC ELECTRICAL CHARACTERISTICS PARAMETER RCLK Period RCLK Pulse Width RCLK Rise and Fall Times RPOS, RNEG Setup to RCLK RPOS, RNEG Hold for RCLK Propagation delay from RRCLK to RPOS, RRNEG Valid Propagation delay from XTAL OUT to RRCLK Pulse ...
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AC TIMING DIAGRAM Figure 5 NOTE: 1. The phase relationship between XTAL OUT and RRCLK can be of either form DS2188 ...
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DS1288 T1/CEPT JITTER ATTENTUATOR 16-PIN DIP PKG 16-PIN DIM MIN MAX AIN 0.740 0.780 MM 18.80 19. 0.240 0.260 MM 6.10 6. 0.120 0.140 MM 3.05 3. 0.300 0.325 MM 7.62 8. ...
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DS1288S T1/CEPT JITTER ATTENTUATOR 16-PIN SOIC PKG 16-PIN DIM MIN MAX AIN 0.402 0.412 MM 10.21 10. 0.290 0.300 MM 7.37 7. 0.089 0.095 MM 2.26 2. 0.004 0.012 MM 0.102 0. ...