MT9075BL Mitel, MT9075BL Datasheet
MT9075BL
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MT9075BL Summary of contents
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... DSTo ST-BUS CSTo Interface RxDLCLK RxDL DS5025 MT9075BP MT9075BL Description The MT9075B is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with ...
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MT9075B CS RESET IRQ VSS IC INT/MOT VDD R/W/WR AC0 RESET IRQ VSS IC INT/MOT 92 VDD ...
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Preliminary Information Pin Description Pin # Name PLCC MQFP 1 66 OSC1 Oscillator Input. This pin is either connected via a 20.000 MHz crystal to OSC2 where a crystal is used directly driven when a 20.000 MHz oscillator ...
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MT9075B Pin Description (continued) Pin # Name PLCC MQFP 17 90 VSS Negative Power Supply (Input). Digital ground Internal Connection. Tie INT/MOT Intel/Motorola Mode Selection (Input). A high on this pin configures the ...
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Preliminary Information Pin Description (continued) Pin # Name PLCC MQFP 45 33 C4b 4.096 MHz System Clock (Input/Output). C4b is the clock for the ST-BUS sections and transmit serial PCM data of the MT9075B. In the free-run (BL/FR=0) or line ...
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MT9075B Pin Description (continued) Pin # Name PLCC MQFP 64 61 TxDLCLK Transmit Data Link Clock (Output). A gapped clock signal derived from a gated 2.048 Mbit/s clock for transmit data link 12 kHz. ...
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Preliminary Information Device Overview The MT9075B is an advanced PCM 30 framer with an on-chip Line Interface Unit (LIU) that meets or supports the latest ITU-T Recommendations for PCM 30 and ISDN primary rate including G.703, G.704, G.706, G.775, G.796, ...
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MT9075B Functional Description MT9075B Line Interface Unit (LIU) Receiver The receiver portion of the MT9075B LIU consists of an input signal peak detector, an optional two-stage equalizer, a smoothing filter, adaptive threshold comparators, data and clock slicers, and a clock ...
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Preliminary Information R 0.68uF 1:2 T TTIP TRING R T MT9075B 1:1 RTIP 120 RRING Figure 4 - Analog Line Interface The template for the transmitted pulse, as specified in G703, is shown in Figure 5. The nominal peak voltage ...
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MT9075B MT9075B 20MHz OSC1 56pF 1M 100 OSC2 Note: the 1 H inductor is optional Figure 7 - Crystal Oscillator Circuit Jitter Attenuator (JA) The MT9075B Jitter Attenuator (JA), which consists of a Phase Locked Loop (PLL) and data FIFO, ...
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... This results in a single time slot data rate of 8 bits x 8000/sec kbits/sec. It should be noted that the Mitel ST-BUS also has 32 channels numbered 0 to 31, but the most significant bit of an eight bit channel is numbered bit 7 (see Mitel Application Note MSAN-126). Therefore, ST- BUS bit 7 is synonymous with PCM 30 bit 1 ...
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MT9075B data. Channel alignment and bit numbering is consistent with time slot alignment numbering. However, channels are numbered and relate to time slots as per Table 3. PCM 3...15 Timeslot Voice/Data x 1 ...
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Preliminary Information AUTC ARAI TALM Table 4 - Operation of AUTC, ARAI and TALM Control Bits There are two CRC multiframe alignment ...
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MT9075B one. Bits 5, 7 and 8 (usually designated X) are spare bits and are normally set to one if not used. Time slot 16 of the remaining 15 basic frames of the CAS multiframe (i.e., basic frames 1 to ...
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Preliminary Information used to control the transmit channel associated signalling. The DSTi and DSTo streams contain the transmit and receive voice and digital data. Identification Code The MT9075B shall be identified by the code 10101010, read from the identification code ...
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MT9075B Frames 11, 13 & CRC-4 Addre Multiframe ssable Bytes NBB0 NBB1 ...
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Preliminary Information respectively. The following features are common to both HDLC controllers: • Independent transmit and receive FIFO's; • Receive FIFO maskable interrupts for nearly full (programmable interrupt levels) and overflow conditions; • Transmit FIFO maskable interrupts for nearly empty ...
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MT9075B and inserted after all sequences of 5 contiguous 1s (including the last five bits of the FCS). Upon receiving five contiguous 1s within a frame the receiver deletes the following 0. Invalid Frames A frame is ...
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Preliminary Information ones) are transmitted to indicate that the channel is idle. HDLC Transmitter Following initialization and enabling, the transmitter is in the Idle Channel state (Mark Idle), continuously sending ones. Interframe Time Fill state (Flag Idle) is selected by ...
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MT9075B Two Status Register bits (RQ8 and RQ9) are appended to each data byte written to the Rx FIFO. They indicate that a good packet has been received (good FCS and no frame abort bad ...
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Preliminary Information The minimum delay through the receive slip buffer is approximately two channels and the maximum delay is approximately 60 channels (see Figure 9). When the C4b and the E2o clocks are not phase- locked, the rate at which ...
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MT9075B >914 CRC errors in one second No CRC multiframe alignment. 8 msec. timer expired* CRC-4 multi-frame alignment Start 400 msec timer. Note 7. Start 8 msec timer. Note 7. Find two CRC frame alignment signals. Note 7. CRC multiframe ...
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Preliminary Information The MT9075B framing algorithm supports automatic interworking of interfaces with and without CRC-4 processing capabilities. That is interface with CRC-4 capability, achieves valid alignment, but does not achieve CRC-4 multiframe alignment by the end of a ...
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MT9075B Loopbacks In order to meet PRI Layer 1 requirements and to assist in circuit fault sectionalization, the MT9075B has six loopback functions. The control bits for digital, remote, ST-BUS, payload and metallic loopbacks are located on page 01H, address ...
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Preliminary Information individual counters overflow. These bits stay high until the register is read. PRBS Error Counter (PS7-0) There are two 8 bit counters associated with PRBS comparison; one for errors and one for time. Any errors that are detected ...
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MT9075B single error events, which is a maximum rate of twice per CRC-4 multiframe. There is a maskable interrupts associated with the CRC error measurement. CRCI (page 01H, address 1CH) is initiated when the least significant bit of the counter ...
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Preliminary Information Receive data may also be microprocessor port. The Rx message mode dual port RAMs (on page 11H and 12H) have a unique address associated with each incoming line channel. When the processor reads any of the 32 memory ...
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MT9075B HDLC Interrupt Masks (page 0BH&0CH, address 16H) Bit 7 Ga EOPD TEOP EopR TxFl After a device reset (RESET pin or RST control bit), interrupts from the following interrupt mask words are masked: • National use bit interrupt mask ...
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Preliminary Information Control and Status Registers Master Control 1 (Page 01H) Address ( 10H (Table 13) Multiframe, National Bit Buffer and Data Link Selection Word 11H (Table 14) Mode Selection ...
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MT9075B Bit Name Functional Description 7 ASEL AIS Select. This bit selects the criteria on which the detection of a (0) valid Alarm Indication Signal (AIS) is based. If zero, the criteria is less than three zeros in a two ...
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Preliminary Information 2 TxTRSP Transmit Transparent Mode. If one, the MT9075B is in transmit (0) transparent mode. No framing or signaling is imposed on the data transmit from DSTi onto the line. If zero termination mode. 1 ...
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MT9075B Bit Name Functional Description 7 -4 TMA1-4 Transmit Multiframe Alignment Bits One to Four. These bits are (0) transmitted on the PCM 30 2048 kbit/sec. link in bit positions one to four of time slot 16 of frame zero ...
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Preliminary Information Bit Name Functional Description 7 --- Unused. 6 MLBK Metallic Loopback. If one, then the external RRTIP and RRING signals (0) are isolated from the receiver, and TTIP and TRING are internally connected to the receiver analog input ...
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MT9075B Bit Name Functional Description 7 --- Unused. 6 PRBSO PRBS Counter Interrupt. When (0) (PRBSO = 1), an interrupt is initiated on overflow of PRBS counter (page 04H, address 10H) from FFH to 0H. Interrupt vector = 00000010. 5 ...
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Preliminary Information Bit Name Functional Description 2 CNTCLR Counter Clear. If one, all status counters are cleared and held low. (0) Zero for normal operation. 1 MSN Most Significant Nibble. If one, the CSTo and CSTi (0) channel associated nibbles ...
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MT9075B Bit Name Functional Description 7 EBI Receive E-bit Interrupt. When unmasked an interrupt is initiated (0) when a receive E-bit indicates a remote CRC-4 unmasked masked. Interrupt vector = 00100000. 6 CRCI CRC-4 Error unmasked an interrupt ...
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Preliminary Information Bit Name Functional Description 2 BEROI Bit Error Counter Interrupt. When unmasked (BERO (0) = 1), an interrupt is initiated when the bit error counter overflows. Interrupt vector = 00010000. 1 AUXPI Auxiliary Pattern Interrupt. When unmasked (AUXPI ...
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MT9075B Address ( 10H (Table 28) Error and Debounce Selection Word 11H --- 12H --- 13H (Table 29) Access Control Word 14H --- 15H --- 16H --- 17H --- 18H ...
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Preliminary Information Bit Name Functional Description 7 BPVE Bipolar Violation Error Insertion. A zero-to-one transition of this bit (0) inserts a single bipolar violation error into the transmit PCM 30 data. A one, zero or one-to-zero transition has no function. ...
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MT9075B Bit Name Functional Description 7 JAS Jitter Attenuator Select. If one, the attenuator may be connected to (0) either the transmit or receive sides of the PCM 30 interface depend on bit 6 - JAT/JAR. If zero, the jitter ...
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Preliminary Information Bit Name Functional Description CPLB6 Sign bit. Normalized to a positive going one, when CPLB6 is one then (0) the CPLB0-CPLB5 corresponds to a positive level. When CPLB6 is zero the coefficient is taken to ...
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MT9075B Master Status 1 (Page 03H) Address Register ( 10H (Table 37) Synchronization Status Word 11H (Table 38) Receive Frame Alignment Signal 12H (Table 39) Timer Status 13H (Table 40) ...
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Preliminary Information Bit Name Functional Description 7 SYNC Receive Basic Frame Alignment. SYNC indicates the basic frame alignment status (1 - loss acquired). 6 MFSYNC Receive Multiframe Alignment. MFSYNC indicates the multiframe alignment status (1 - loss; 0 ...
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MT9075B Bit Name Functional Description 7 1SEC One Second Timer Status. This bit changes state once every 0.5 second and is synchronous with the 2SEC timer. 6 2SEC Two Second Timer Status. This bit changes state once every second and ...
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Preliminary Information Bit Name Functional Description RMA1-4 Receive Multiframe Bits One to Four. These bits are received on the PCM 30 2048 kbit/ sec. link in bit positions one to four of time slot 16 of frame ...
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MT9075B Bit Name Functional Description RxEBC7 -0 Receive Eighth Bit Count. The 8 least significant bit of a counter that indicates the number of one eighth bit times there are between the ST-BUS frame pulse and receive ...
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Preliminary Information Bit Name Functional Description 7 CRCS1 Receive CRC Error Status One. If one, the evaluation of the last received submultiframe 1 resulted in an error. If submultiframe 1 was error free. Updated on a submultiframe 1 basis. 6 ...
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MT9075B Master Status 2 (Page 04H) Address ( 10H (Table 50) PRBS Error Counter 11H (Table 51) CRC Multiframe counter for PRBS 12H (Table 52) Interrupt Vector 13H (Table 53) ...
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Preliminary Information Bit Name Functional Description PS7-0 PRBS Error Counter. This counter is incremented for each PRBS error detected on any of the receive channels connected to the PRBS error detector. Table 50 - PRBS Error Counter ...
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MT9075B Bit Name Functional Description 7 PRBSO PRBS Error Counter Overflow. This bit is set to one when the PRBS Error Counter (page 04H address 10H) cleared when this register is read. 6 FEBEO E Bit Counter Overflow. This bit ...
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Preliminary Information Bit Name Functional Description EFAS7 Errored FAS Counter bit counter that is incremented once for - every receive EFAS0 signal that contains one or more errors. Table 60 - Errored Frame Alignment Signal ...
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MT9075B Per Channel Transmit Signalling (Page 05H) Table 62 describes Page 05H, addresses 11H to 1FH, which contains the Transmit Signalling Control Words for PCM 30 channels and 16 to 30. Control of these bits is through ...
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Preliminary Information Per Channel Receive Signalling (Page 06H) Page 06H, addresses 11H to 1FH contain the Receive Signalling Control Words for PCM 30 channels and 16 to 30. Bit Name A(n), B(n), C(n), D(n) ...
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MT9075B Per Time Slot Control Words (Pages 07H and 08H) The control functions described by Table 69 are repeated for each PCM-30 channel. Page 07H addresses 10H to 1FH correspond to time slots 0 to 15, while page 08H addresses ...
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Preliminary Information One Second Status (Page 09H) Address ( 10H MSB Latched (Table 75) E-bit Error Count 11H LSB Latched E-bit Error Count (Table 76) 12H Latched Errored Frame Alignment ...
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MT9075B Bit Name Functional Description --- Unused LEC9 Latched E bit error counter (the most significant two bits). These - bits are sampled every second by LEC8 the internal one second timer. Table 75 ...
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Preliminary Information HDLC Control and Status (Page 0BH & 0CH) Address Control (Write/Verify) 10H (Table 83) Address Recognition 1 11H (Table 84) Address Recognition 2 12H (Table85) TX FIFO & (Table 86) 13H (Table 87) HDLC Control 1 14H (Table ...
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MT9075B Bit Name Functional Description Adr16 A six bit mask used to interrogate the first byte of the received - address. Adr16 is the MSB. Adr11 (000000) 1 Adr10 This bit is used comparison, if control bit ...
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Preliminary Information Bit Name Functional Description 7 Adrec Address Recognition. When one this bit will (0) recognition. This receiver to recognize only those packets having the unique address as programmed in the Receive Address Recognition Registers or if the address ...
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MT9075B Bit Name Functional Description 3, 2 Txstat2, Transmit Status. Txstat1 indicate the status of the TX FIFO as follows: Txsta Txsta FIFO full up to the selected status level or more. See Table 93. ...
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Preliminary Information Bit Name Functional Description 7-0 Ga, This register is used with the EOPD, Interrupt Register to mask out the TEOP, interrupts that are not required by EOPR, the microprocessor. Interrupts that TxFl, are masked out will not produce ...
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MT9075B Bit Name Functional Description Crc7 - 0 The LSB byte of the CRC received from the transmitter. These bits are as the transmitter sent them; that is, most significant inverted. This register is updated at the ...
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Preliminary Information Bit Name Functional Description RSV These bits are reserved. 3 RXclk This bit represents the receiver clock generated after the RXEN control bit is enabled, but before zero deletion is considered. 2 TXclk This bit ...
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MT9075B Bit Name Functional Description 7 --- Unused RFFS2 - 0 These bits select the RXFF (Rx FIFO Full) interrupt threshold level: (000) RFFS RFFS RFFS ...
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Preliminary Information Transmit National Bit Buffer (Page 0DH) Page 0DH, addresses 10H to 14H contain the five bytes of the transmit national bit buffer (TNBB0 - TNBB4 respectively). This feature is functional only when control bit NBTB (page 01H, address ...
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MT9075B Page 0FH, addresses 10H to 1FH contain the 16 bytes of transmit message buffer zero Bit Name TxB0.n.7 - Transmit Bits This byte is transmit on a time slot when selected by the ...
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Preliminary Information Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage at Digital Inputs 3 Current at Digital Inputs 4 Voltage at Digital Outputs 5 Current at Digital Outputs 6 Storage Temperature * Exceeding these values may cause permanent damage. ...
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MT9075B AC Electrical Characteristics Characteristics 1 DS low 2 DS High 3 CS Setup 4 R/W Setup 5 Address Setup 6 CS Hold 7 R/W Hold 8 Address Hold 9 Data Delay Read 10 Data Hold Read 11 Data Active ...
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Preliminary Information AC Electrical Characteristics Characteristics 1 RD low 2 RD High 3 CS Setup 4 CS Hold 5 Address Setup 6 Address Hold 7 Data Delay Read 8 Data Active to High Z Delay 9 Data Setup Write 10 ...
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MT9075B AC Electrical Characteristics - Transmit Data Link Timing Characteristic 1 Data Link Clock Output Delay 2 Data Link Setup 3 Data Link Hold F0b TIME SLOT 0 Bits 4,3,2,1,0 TxDLCLK TxDL TxDLCLK TxDL Figure 13 - Transmit Data Link ...
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Preliminary Information AC Electrical Characteristics - Receive Data Link Timing Characteristic 1 Data Link Clock Output Delay 2 Data Link Output Delay RxFP TIME SLOT 0 Bits 4,3,2,1,0 RxDLCLK RxDL RxDLCLK RxDL Figure 15 - Receive Data Link Functional Timing ...
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MT9075B AC Electrical Characteristics - Transmit 64 k Common Channel Timing Characteristic 1 Transmit Common Channel Setup 2 Transmit Common Channel Hold F0b STBUS Channel Times Internal Clock CSTi Figure 17 - Transmit 64k Common Channel Functional Timing C4b Internal ...
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Preliminary Information AC Electrical Characteristics - Receive 64k Common Channel Timing Characteristic 1 Receive Common Channel Output Delay Rx64KCK CSTo Figure 19 - Receive 64k Common Channel Functional Timing Rx64KCK CSTo Figure 20 - Receive 64k Common Channel Timing Diagram ...
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MT9075B AC Electrical Characteristics - ST-BUS / GCI Timing Characteristic 1 C4b Clock Width High or Low 2 C4b Clock Width High or Low 3 Frame Pulse Setup 4 Frame Pulse Hold 5 Frame Pulse Delay 6 Serial Input Setup ...
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Preliminary Information ST-BUS Bit Bit Cell Stream F0b (Output) t FPD C4b (Output) All Input Streams All Output Streams Figure 23 - ST-BUS Timing Diagram (Output Clocks) ST-BUS Channel 31 Bit Cells Bit 0 F0b C4b Figure 24 - GCI ...
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MT9075B ST-BUS Bit Bit Cell Stream F0b (Input) C4b (Input) All Input Streams All Output Streams Figure 25 - GCI Timing Diagram (Input Clocks) ST-BUS Bit Bit Cell Stream F0b (Output) t FPD C4b (Output) All Input Streams All Output ...
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Preliminary Information AC Electrical Characteristics - Multiframe Timing Characteristic 1 Receive Multiframe Output Delay 2 Transmit Multiframe Setup 3 Transmit Multiframe Hold Frame 15 DSTo BIt Cells Bit 7 Bit 6 Bit 5 F0b C4b (4.096 MHz) RxMF Figure 27 ...
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MT9075B F0b t MOD C4b (1) RxMF t MS (1) TxMF (1) Note : These two signals do not have a defined phase relationship Figure 29 - Multiframe Timing Diagram FRAME FRAME 15 0 TIME SLOT Most BIT Significant Bit ...
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Index Pin 1 44-Pin Dim Min Max A - 0.096 (2.45) A1 0.01 - (0.25) A2 0.077 0.083 (1.95) (2.10) b 0.01 0.018 (0.30) (0.45) D 0.547 BSC (13.90 BSC) D 0.394 BSC 1 ...
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Package Outlines 160-Pin Dim Min 0.125 (3.17) b 0.009 (0.22) D 1.23 BSC (31.2 BSC) D 1.102 BSC 1 (28.00 BSC) E 1.23 BSC (31.2 BSC) E 1.102 BSC 1 (28.00 BSC) e 0.025 BSC (0.65 ...
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Package Outlines Dim D General- (lead coplanarity) A Notes Not ...
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... Mitel. This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specifi ...