CXK77V3211Q-14 Sony, CXK77V3211Q-14 Datasheet
CXK77V3211Q-14
Related parts for CXK77V3211Q-14
CXK77V3211Q-14 Summary of contents
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... READ cycle following a WRITE as controlled by OE. The CXK77V3211Q operates from a +3.3V power supply and all inputs and outputs are LVTTL compatible. The device is ideally suited for i486 and Pentium™ systems and those systems which benefit from a very wide data bus ...
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... CXK77V3211Q ...
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... DQ30 25 Vssq DQ31 DQ32 – 3 – CXK77V3211Q DQ16 78 DQ15 Vssq 75 DQ14 74 DQ13 73 DQ12 72 DQ11 71 Vssq ...
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... Linear Burst: This active high input selects interleaved burst sequence. LBO I ZZ: This active high input enables the device in powerdown mode Supply Power Supply: +3.3V DD Ground: GND V Supply SS Isolated Output Buffer Supply: +3. Supply DD Isolated Output Buffer Ground: GND V q Supply SS Description +10% – 5% +10% – 5% – 4 – CXK77V3211Q ...
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... All L Register A (n – new cycle All – new cycle All HIGH-Z No new cycle One – 1) for one byte – 5 – CXK77V3211Q Address used latched A1 latched A0 latched A1 latched A0 latched A1 latched A0 Next cycle ...
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... Tsolder 235 · 10 Symbol Min. Typ. V 3.135 3 2.0 — –0.3 — IL (GND 2.0V for t ≤ t /2. KC /2. KC – 6 – CXK77V3211Q BW2 BW3 BW4 Unit °C °C °C · sec ( +70°C, GND = 0V) Max ...
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... All inputs ≤ 0.2V or ≥ V – 0.2V DD Device deselect I = –5.0mA 5.0mA < 1µA > 10KΩ < 1µA > 10KΩ – 7 – CXK77V3211Q +10% , GND = 0V +70°C) – 5% Min. Max. –1 1 – ≥ — 210 250 — 20 — ...
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... OLZ 2 0 — OHZ 2 — 5 — t 2.5 — 2 0.5 — 0 ZZS 3 5 — ZZH 3 1 — — 20 ZZR – 8 – CXK77V3211Q -14 Unit 14 ns — ns — ns — — ns — ns — ns — ns — — — ns — ns — ...
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... Output load (2) for and OHZ (Ta = 25° 1MHz) Test condition Typ I/O +10 +70°C) – and HZ OLZ – 9 – Max. Unit 30pF 1.4V T Output load (1) Fig. 1. +3.3V 295 I/O 5pF 217 Output load (2) Fig. 2. CXK77V3211Q ...
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... Next Next Next Next Current Current Current Current Current Current – 10 – CXK77V3211Q ADSC ADV BWx OE CLK ...
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... S H ADV suspends burst t OHZ OLZ t KQX Q Q (A1) Q (A2) ( – 11 – CXK77V3211Q A3 Burst continued with new base address Deselect cycle ( ( (A2 Burst wrap around to its initial state. Burst READ DON'T CARE UNDEFINED A4 ) ...
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... ADV must be HIGH to permit a WRITE to the loaded address (A2 Burst WRITE – 12 – ADSC extends burst ADV suspends burst (A3 Extended Burst WRITE DON'T CARE UNDEFINED CXK77V3211Q D ( ...
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... CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW OLZ D (A2 OHZ KQ Q (A1) Q (A2) Pass Through READ Single WRITE – 13 – CXK77V3211Q ( ) (A3 Burst READ DON'T CARE UNDEFINED ...
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... HIGH. When CE is HIGH, CE2 is HIGH and CE is LOW OHZ OLZ t KOX Q Q (A1) Q (A2) ( – 14 – A3 ADV suspends burst ( (A2 Burst wrap around to its initial state. Burst READ DON'T CARE UNDEFINED CXK77V3211Q (A3) ...
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... ADV must be HIGH to permit a WRITE to the loaded address (A2 Burst WRITE – 15 – CXK77V3211Q ADSC extends burst ADV suspends burst (A3) ( ...
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... CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW OLZ D (A2) t OHZ (A3) Single WRITE – 16 – CXK77V3211Q ( ) ( ( ( Burst READ DON'T CARE UNDEFINED ...
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... ZZ Timing t KC CLK ADSP ADSC ZZH ZZS t Snooze – 17 – CXK77V3211Q ZZR ...
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... EIAJ CODE JEDEC CODE 100PIN QFP (PLASTIC) 1420 23.2 ± 0.2 20.0 ± 0 0.65 0.12 M 0.25 + 0.15 0.1 0.1 0.1 – 0.05 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT QFP-100P-L02 QFP100-P-1420-B LEAD MATERIAL PACKAGE WEIGHT – 18 – CXK77V3211Q 0.35 2.75 – 0.15 + 0.08 0.32 – 0.07 (0.3) DETAIL B EPOXY RESIN SOLDER PLATING COPPER 1.7g ...