MT90810AK Mitel, MT90810AK Datasheet
MT90810AK
Specifications of MT90810AK
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MT90810AK Summary of contents
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... Microprocessor Interface AD[0:7] A[0:1] ALE WR/ RD/ CS RDY/ DS R/W DTACK Figure 1 - Functional Block Diagram MT90810 CMOS Preliminary Information ISSUE 2 October 1994 Ordering Information MT90810AK 100 Pin PQFP 0 °C to +70 °C The MVIP (Multi-Vendor Integration FRAME CLK2 CLK4 CLK8 RESET CSTo FGA[0:11] FGB[0:11] ERR DREQ[0:1] DACK[0:1] 2-145 ...
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MT90810 80 78 FGA10 LDO1 82 LDO2 FGB10 84 LDO3 86 VDD LDI0 88 LDI1 LDI2 LDI3 90 EX8_KA 92 EX8_KB VSS FRAME 94 CLK8 FGA11 96 CLK4 CLK2 98 FGB11 FGA0 100 2 4 2-146 ...
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Preliminary Information Pin Description Pin # Name 58, 60, 63, 67, 70, DSo[0:7] 72, 74, 77 59, 61, 64, 68, 71, DSi[0:7] 73, 75, 78 80, 82, 83, 85 LDO[0:3] 87, 88, 89, 90 LDI[0:3] 4 CSTo 55 F0b 56 ...
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MT90810 Pin Description Pin # Name 32, 34 A[0:1] 29 ALE RD/ [DS] 25 WR/ [R/W] 30 RDY [DTACK] 31 ERR 49, 50 DREQ[0:1] 47, 48 DACK[0:1] 10 TCK 11 TDI 2-148 Description Microprocessor Address (TTL Input). ...
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... VDD[0:3] 16, 41, 52, 66, VSS[0:5] 79, 93 Device Overview Mitel’s MT90810 is a MVIP compliant device. It provides a complete, cost effective, MVIP compliant interface between the MVIP Bus and a wide variety of processors, telephony interfaces and other circuits. The FMIC supports 384 full duplex, time ...
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MT90810 DSi0 O Connection Memory Connection memory is comprised of a static RAM block 384 locations by 12 bits. Each location in connection memory corresponds to one of the 384 output ...
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Preliminary Information EX_8KA EX_8KB 16MHz C4b PLL_MODE External 16MHz Crystal XCLK_SEL 0 div div 2 F0b Figure 4 - Clock Control Functional Block Diagram 8kHz clock. The digital PLL ...
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MT90810 Jitter - 6 Attenuation 8 (dB Figure 5 - Jitter Transfer ...
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Preliminary Information Local Output Clock Control The FMIC provides four output clocks which are always driven off of the device. The FRAME output clock has a duty cycle and period equal to the MVIP F0 signal. The CLK2 and CLK4 ...
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MT90810 framing signal in the group is asserted. The distance between consecutive frame pulses within a frame group can be one 8Mb/s channel time and can be specified by two bits in the frame mode register. Mode ...
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Preliminary Information memory and auto increment/decrement mode is written to the AMR. Finally, the write operation is performed when data is written to the Indirect Data Register(IDR). Similarly, to perform a read operation from an indirect location, the LAR and ...
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MT90810 into the device due to a DMA write request of a given channel, is not actually written to that channel but to the next channel enabled for DMA on the same stream DMA read or write request ...
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Preliminary Information Bits 7:0 All bits are written into the indirect address location specified by the LAR and AMR registers. If auto increment on write/read is enabled, and connection memory is selected, then consecutive writes/reads to/from the IDR will toggle ...
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MT90810 Mode [bits] APLL source Frame Sync. 0 [000] X1 divided by no frame 1, sync. 1 [001] SEC8K >DPLL no frame sync. 2 [010] EX8KA >DPLL 3 [011] EX8KB >DPLL frame sync. 4 [100] MVIP C4 to ...
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Preliminary Information Bit Name 7 DACK1 6 DACK0 5 EX8KB 4 EX8KA 3 INV_CLK8 2 INV_CLK4 1 INV_CLK2 0 INV_FRM Table 11 - Local Clock Control (LOC_CLK) Register Mode Description [bits] 0 [00] 2MHz streams All local streams are configured ...
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MT90810 Mode Description [bits] 3 [11] Split 2MHz/4MHz streams Local streams 0&1 are each configured to run at 2MHz on pins LDI/O[0] and LDI/O[1], respectively. Local streams 2&3 are multiplexed onto pin LDI/O[2]. Table 12 - SER_CNFG bits (control configuration ...
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Preliminary Information Mode [bits] 0 [00] Programmed output 1 FGx[0:11] are programmable output pins. All 8 bits of FRMx_START register are driven out pins FGx[0:7] (with bit 0 corresponding to pin FGx[0] etc.) and bits 0-3 of FRMx_MODE register are ...
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MT90810 Bit Name Frame Start (FRMx_STRT) Register x 7:0 STRT(7:0) Frame Mode (FRMx_STRT) Register x 7:6 MODE 5 FRM_TYPE 4:3 BIT_RATE 2:0 STRT(11:8) Table 16 - Frame Register bits for modes 2&3 Bit Name 7:3 RESERVED Should NEVER be set ...
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Preliminary Information Streams MVIP Stream 0 MVIP Stream 1 MVIP Stream 2 MVIP Stream 3 MVIP Stream 4 MVIP Stream 5 MVIP Stream 6 MVIP Stream 7 Local Stream 0 Local Stream 1 Local Stream 2 Local Stream 3 Indirect ...
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MT90810 Figure 11 - Connection Memory High Byte Bit Name 7:4 RESERVED 3 DC Direction Control. controls the direction of the MVIP DSi/DSo channel pair. When DC is set, DSi is the input channel and DSo is the output channel. ...
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Preliminary Information Bit Name 7-4 RESERVED 3 CSTo CSTo. The inverted value of this bit is output on the CSTo pin and is available for general purpose system timing functions. The CSTo bit for each of the local output channels ...
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MT90810 JTAG Support The FMIC JTAG interface is designed to the Boundary-Scan standard IEEE1149.1. The standard specifies a design-for-testability technique called Boundary-Scan Test (BST). A boundary-scan IC has a shift-register stage or ‘Boundary-Scan Cell’ (BSC) in between the core logic ...
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Preliminary Information • The Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers ...
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MT90810 Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any I/O pin 3 Current at outputs 4 Storage Temperature 5 Thermal Resistance * Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed. ...
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Preliminary Information AC Electrical Characteristics- Clock and Stream Timing Characteristics 1 Data Propagation Delay 2 Data Setup Time 3 Data Hold Time 4 Data bit 7 Tristate 5 F0b/FRAME Setup Time 6 F0b/FRAME Hold Time 7 F0b/FRAME Pulse Width 8 ...
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MT90810 FRAME C8P t CLK 8 C8L CLK 4 t CLK 2 (2 MHz t Bit Rate) PD LDO LDI (4 MHz Bit Rate LDO LDI (8 MHz Bit Rate ...
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Preliminary Information 8 MHz Clock F0b C4b C2o In DSi DSo Out Frame Group programmed for 2Mb/s Data Streams start of frame group can be programmed to occur on any 8 MHz clock boundary 1 bit cell ...
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MT90810 AC Electrical Characteristics - GCI Timing Characteristics 1 Clock Period 2 Clock High/Low Width 3 Frame Setup 4 Frame Hold 5 Clock Edge to Data Valid 6 Data Setup 7 Data Hold CLK4/ DCL FRAME/ FSC Ch. 31 DU/DD ...
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Preliminary Information AC Electrical Characteristics - Microprocessor Timing Characteristics 1 Address Setup 2 Address Hold 3 Data Access from RDY High 4 Microprocessor Access to Data Ready Register (Fast) Access Memory (Slow) Access 5 Microprocessor to RDY low 7 Data ...
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MT90810 AD[0:7] Add t AS ALE RDY RDY Notes: RDY is only driven low during memory (slow) cyles measured from either going high, whichever is later. DOFF Figure 22 - Intel Multiplexed ...
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Preliminary Information A[0:1] R/W [WR [RD] CS DTACK AD[0:7] Figure 24 - Motorola Non-multiplexed Bus Timing for Read Cycle (ALE=VDD) A[0:1] R/W [WR [RD] CS DTACK t DS AD[0:7] Figure 25 - Motorola Non-multiplexed ...
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MT90810 AC Electrical Characteristics - DMA Timing Characteristics 1 C2o low to DACK1 asserted 2 C2o low to DACK0 asserted 3 DACK1 asserted to RD low 4 DACK0 asserted to WR low 5 C2 low to DREQ1 asserted 6 C2 ...
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Preliminary Information C2o t CDRQ DREQ/1 DACK0/1 WR/ 100 0.106 0.004 (2.7 0.1) 0.006 0.002 (0.15 0.05) Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) async WDRQ t RDRQ t ...
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MT90810 Notes: 2-178 Preliminary Information ...