MT90826AG Mitel, MT90826AG Datasheet

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MT90826AG

Manufacturer Part Number
MT90826AG
Description
0.3-5.0V; 20mA; quad digital switch. For medium and large switching platforms; CTI applications
Manufacturer
Mitel
Datasheet

Specifications of MT90826AG

Case
BGA
Dc
02+

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Features
Applications
STi0/FEi0
STi1/FEi1
STi31/FEi31
4,096
at 8.192 or 16.384 Mb/s
Per-channel variable or constant throughput
delay
Accept ST-BUS streams of 2.048Mb/s,
4.096Mb/s, 8.192Mb/s, or 16.384 Mb/s
Split Rate mode allows mix of two bit rates and
rate conversions
Automatic frame offset delay measurement for
ST-BUS input and output streams
Per-stream frame delay offset programming
Per-channel high impedance output control
Bit Error Monitoring on selected ST-BUS input
and output channels.
Per-channel message mode
Connection memory block programming
IEEE-1149.1 (JTAG) Test Port
3.3V local I/O with 5V tolerant inputs and TTL
compatible outputs
Medium and large switching platforms
CTI application
Voice/data multiplexer
Digital cross connects
WAN access system
Wireless base stations
4,096 channel non-blocking switching
V
DD
PLLV
Converter
V
DD
Parallel
SS
Serial
to
PLLV
SS
CLK
Timing
Unit
Figure 1 - Functional Block Diagram
F0i
IC2
TMS
IC3
Multiple Buffer
Data Memory
TDI TDO
DT1 AT1
Registers
Internal
Test Port
TCK
DS
DS5197
Description
The MT90826 Quad Digital Switch has a non-
blocking switch capacity of 4,096 x 4,096 channels at
a serial bit rate of 8.192Mb/s or 16.384 Mb/s, 2,048 x
2,048 channels at 4.096Mb/s and 1024 x 1024
channels at 2.048Mb/s. The device has many
features that are programmable on a per stream or
per channel basis, including message mode, input
offset delay and high impedance output control.
The per stream input and output delay control is
particularly useful for managing large multi-chip
switches with a distributed backplane.
Operating in Split Rate mode allows for switching
between two groups of bit rate streams.
TRST
Microprocessor Interface
CS
MT90826AL
MT90826AG
IC1
R/W
Connection
Output
MUX
RESET
Memory
A13-A0 DTA
Ordering Information
-40 to +85 C
160 Pin MQFP
160 Pin PBGA
Advanced Information
Quad Digital Switch
ISSUE 2
D15-D0
Converter
Parallel
ODE
Serial
to
MT90826
June 1999
STo0
STo1
STo31
1

Related parts for MT90826AG

MT90826AG Summary of contents

Page 1

... PLLV PLLV CLK DD SS DS5197 MT90826AL MT90826AG Description The MT90826 Quad Digital Switch has a non- blocking switch capacity of 4,096 x 4,096 channels at a serial bit rate of 8.192Mb/s or 16.384 Mb/s, 2,048 x 2,048 channels at 4.096Mb/s and 1024 x 1024 channels at 2.048Mb/s. The device has many features that are programmable on a per stream or per channel basis, including message mode, input offset delay and high impedance output control ...

Page 2

MT90826 CMOS 115 113 119 117 NC STo22 121 STo23 VSS 123 VDD 125 STi24/FEi24 STi25/FEi25 127 STI26/FEi26 STi27/FEi27 129 VSS STo24 131 STo25 STo26 133 STo27 VSS 135 VDD STi28/FEi28 137 STi29/FEi29 STi30/FEi30 139 STi31/FEi31 VSS 141 STo28 STo29 ...

Page 3

Advanced Information STi26 STi24 STo20 B STi27 STi25 C STo26 STo25 D STo27 STo24 E STi30 STi28 F STi31 STi29 G STo28 STo29 H STo30 STo31 ...

Page 4

MT90826 CMOS Pin Description (continued) Pin # MQFP Pin # PBGA 34 N11 35 M11 36 N12 37 N13 38 M12 40 K11 41 J11 42 L11 43 M13 44 L12 46 L13 47 K12 48 J12 49 H11 50 ...

Page 5

Advanced Information Pin Description (continued) Pin # MQFP Pin # PBGA 52 K13 55 J13 56 H13 57 H12 58 G13 59 G12 67-70 F13,F12,E13,E12 78,79 B13,A13 82,83 A12,B12 91-94 C11,C10,C9,C8 102-105 A7,B7,A6,B6 113-116 A5,B5,A4,B4 126-129 A2,B2,A1,B1 137-140 E2,F2,E1,F1 61-64 ...

Page 6

... All inputs and outputs may be programmed to 2.048, 4.096 or 8.192 Mb/s. STi0-15 and STo0-15 may be set to 16.384 Mb/s. Combinations of two bit rates, N and 2N are provided. See Table 1. By using Mitel’s message mode capability, the microprocessor can access input timeslots on a per channel basis ...

Page 7

Advanced Information Locations in the connection memory are associated with particular ST-BUS output channels. When a channel is due to be transmitted on an ST-BUS output, the data for this channel can be switched either from an ST-BUS input in ...

Page 8

MT90826 CMOS 16Mb/s mode (DR2=0, DR1=0, DR0 =1) When the 16Mb/s mode is selected, the device is configured with 16-input/16-output data streams each having 256 64Kbit/s channels. This mode allows a maximum non-blocking capacity of 4,096 x 4,096 channels. 4Mb/s ...

Page 9

Advanced Information See Table 10 and Table 11 for the frame output offset programming. Memory Block Programming The MT90826 provides users with the capability of initializing the entire connection memory block in two frames. Bits every ...

Page 10

MT90826 CMOS A13 A12 A11 A10 ...

Page 11

Advanced Information Memory Mapping The address bus on the microprocessor interface selects the internal registers and memories of the MT90826. If the A13 address input is low, then the registers are addressed by A12 to A0 according to Table 3. ...

Page 12

MT90826 CMOS Read/Write Address: Reset Value BPD2 BPD1 BPD0 CPLL 0 Bit Name 15-13 BPD2-0 Block Programming Data. These bits carry the value to be loaded into the connection memory block whenever the memory block ...

Page 13

Advanced Information DR2 DR1 DR0 Table 6 - Serial Data Rate Selections and External Clock Rates Read/Write Address: Reset ...

Page 14

MT90826 CMOS F0i CLK (16.384MHz) Internal master clock at 32MHz Offset Value 0 FEi Input For 8Mb/s, 16Mb/s, 4&8Mb/s and 16&8Mb/s modes F0i CLK (16.384MHz) Internal master clock at 16 MHz Offset Value 0 FEi Input F0i CLK (16.384MHz) Internal ...

Page 15

Advanced Information Read/Write Address Reset value: 0000 IF33 IF32 IF31 IF30 IF23 IF63 IF73 IF72 IF71 IF70 IF113 IF112 IF111 IF110 IF103 IF153 IF152 IF151 IF150 IF143 IF193 IF192 IF191 IF190 ...

Page 16

MT90826 CMOS Input Stream Offset No internal master clock shift (Default) + 1/4 internal master clock shift + 1/2 internal master clock shift + 3/4 internal master clock shift + 1.00 internal master clock shift + 1.25 internal master clock ...

Page 17

Advanced Information Read/Write Address: 000A 000B 000C 000D Reset value: 0000 OF71 OF70 OF61 OF60 OF51 OF151 OF150 OF141 OF140 OF131 OF231 OF230 OF221 OF220 OF211 OF311 OF310 OF301 OF300 OF291 Name (Note 1) OFn1, ...

Page 18

MT90826 CMOS Read/Write Address: 0011 Reset value: 0000 BSA4 BSA3 Bit Name BSA4 - BSA0 BER Input Stream Address Bits. The number expressed in binary notation on these bits ...

Page 19

Advanced Information SAB SAB TM1 TM0 Bit Name 15-14 TM1-0 Mode Select Bits Output Enable. This bit enables the drivers of STo pins on a per-channel basis. When 1, the ...

Page 20

MT90826 CMOS JTAG Support The MT90826 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). The operation of the boundary-scan circuitry is controlled by an external test access port (TAP) Controller. ...

Page 21

Advanced Information Boundary Scan Bit 0 to Bit 165 Device Pin Tri-state Output Control Scan Cell F0i CLK ODE STi0 STi1 STi2 STi3 STo0 7 8 STo1 9 10 STo2 11 12 STo3 13 14 STi4 STi5 STi6 STi7 STo4 ...

Page 22

MT90826 CMOS Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any 3.3V tolerant pin I/O (other than sup- ply pins) 3 Voltage on any 5V tolerant pin I/O (other than sup- ply pins) 4 Continuous Current at digital ...

Page 23

Advanced Information AC Electrical Characteristics - Frame Pulse and CLK Characteristic 1 Frame pulse width 2 Frame Pulse Setup time before CLK falling 3 Frame Pulse Hold Time from CLK falling 4 CLK Period 5 CLK Pulse Width High 6 ...

Page 24

MT90826 CMOS t FPW F0i t FPS CLK (16.384MHz) STo Bit 0, Last Channel STi Bit 0, Last Channel Figure 7 - ST-BUS Timing for Stream rate of 8.192 Mb/s t FPW F0i t FPS CLK (16.384MHz) STo Ch63 Bit ...

Page 25

Advanced Information F0i t t FPS8 FPH8 CLK (8.192MHz) t SOD STo Ch31 Bit 0 (2Mb/s) STi Ch31 Bit 0 (2Mb/s) Figure 11 - ST-BUS Timing for Stream rate of 2.048 Mb/s when CLK = 8.192MHzMHz CLK t DZ Valid ...

Page 26

MT90826 CMOS AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS ...

Page 27

Pin #1 Corner 3.00*45 (4x) 20.00 REF 30 Typ. C Seating Plane Package Outlines ...

Page 28

Index Pin 1 44-Pin Dim Min Max A - 0.096 (2.45) A1 0.01 - (0.25) A2 0.077 0.083 (1.95) (2.10) b 0.01 0.018 (0.30) (0.45) D 0.547 BSC (13.90 BSC) D 0.394 BSC 1 ...

Page 29

Package Outlines 160-Pin Dim Min 0.125 (3.17) b 0.009 (0.22) D 1.23 BSC (31.2 BSC) D 1.102 BSC 1 (28.00 BSC) E 1.23 BSC (31.2 BSC) E 1.102 BSC 1 (28.00 BSC) e 0.025 BSC (0.65 ...

Page 30

... Mitel. This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specifi ...

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