MCM69P737TQ4R Motorola, MCM69P737TQ4R Datasheet

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MCM69P737TQ4R

Manufacturer Part Number
MCM69P737TQ4R
Description
128K x 36 bit pipelined burstRAM synchronous fast static RAM
Manufacturer
Motorola
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
128K x 36 Bit Pipelined
BurstRAM Synchronous
Fast Static RAM
a burstable, high performance, secondary cache for the PowerPC
high performance microprocessors. It is organized as 128K words of 36 bits
each. This device integrates input registers, an output register, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in cache data RAM applications. Synchronous design allows precise cycle
control with the use of an external clock (K).
enable (G) and linear burst order (LBO) are clock (K) controlled through positive–
edge–triggered noninverting registers.
addresses can be generated internally by the MCM69P737 (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
controlled by the burst address advance (ADV) input pin.
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx and SW are asserted.
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC stan-
dard JESD8–5 compatible.
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
REV 6
1/20/98
MOTOROLA FAST SRAM
The MCM69P737 is a 4M bit synchronous fast static RAM designed to provide
Addresses (SA), data inputs (DQx), and all control signals except output
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
Write cycles are internally self–timed and are initiated by the rising edge of the
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
For read cycles, pipelined SRAMs output data is temporarily stored by an
The MCM69P737 operates from a 3.3 V core power supply and all outputs
Motorola, Inc. 1998
MCM69P737–3.5: 3.5 ns Access/6 ns Cycle (166 MHz)
MCM69P737–3.8: 3.8 ns Access/6.7 ns Cycle (150 MHz)
MCM69P737–4: 4 ns Access/7.5 ns Cycle (133 MHz)
3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
ADSP, ADSC, and ADV Burst Control Pins
Selectable Burst Sequencing Order (Linear/Interleaved)
Single–Cycle Deselect Timing
Internally Self–Timed Write Cycle
Byte Write and Global Write Control
PB1 Version 2.0 Compatible
JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages
and other
MCM69P737
CASE 983A–01
Order this document
TQ PACKAGE
ZP PACKAGE
CASE 999–02
by MCM69P737/D
PBGA
TQFP
MCM69P737
1

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MCM69P737TQ4R Summary of contents

Page 1

... PB1 Version 2.0 Compatible JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages The PowerPC name is a trademark of IBM Corp., used under license therefrom. REV 6 1/20/98 MOTOROLA FAST SRAM Motorola, Inc. 1998 Order this document MCM69P737 and other ZP PACKAGE CASE 999–02 TQ PACKAGE CASE 983A– ...

Page 2

... MCM69P737 2 FUNCTIONAL BLOCK DIAGRAM BURST COUNTER K2 CLR 2 17 ADDRESS REGISTER WRITE REGISTER a WRITE REGISTER b WRITE REGISTER c WRITE REGISTER ENABLE ENABLE REGISTER REGISTER 2 17 128K x 36 ARRAY DATA–IN DATA–OUT REGISTER REGISTER K DQa – DQd MOTOROLA FAST SRAM ...

Page 3

... SA0 V SS DQa LBO DDQ TOP VIEW 119 BUMP PBGA MOTOROLA FAST SRAM PIN ASSIGNMENTS 7 100 9695 94 93 DQc 1 V DDQ DQc 2 DQc DDQ DQc 6 DQb DQc 7 DQc ...

Page 4

... SBx pins. If only byte write signals SBx are being used, tie this pin low Supply Core Power Supply. V DDQ Supply I/O Power Supply Supply Ground. NC — No Connection: There is no connection to the chip. Description MOTOROLA FAST SRAM ...

Page 5

... MOTOROLA FAST SRAM Symbol Type ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect ...

Page 6

... WRITE 1 X High–Z WRITE 1 X High–Z WRITE 4th Address (Internal X11 X00 X01 X10 4th Address (Internal X11 X10 X01 X00 SBb SBc SBd MOTOROLA FAST SRAM ...

Page 7

... Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1). MOTOROLA FAST SRAM Value Unit ...

Page 8

... IH2 20% t KHKH (MIN) Figure 1. Undershoot Voltage Min Typ Max Unit 3.135 3.3 3.6 V 2.375 2.5 2.9 V – 0.3 — 0.7 V 1.7 — 0.3 V 1.7 — V DDQ + 0.3 V Min Typ Max Unit 3.135 3.3 3.6 V 3.135 3 – 0.5 — 0 — 0 — V DDQ + 0.5 V MOTOROLA FAST SRAM ...

Page 9

... TTL levels for I/O’s are IH2 . TTL levels for other inputs are V in CAPACITANCE (f = 1.0 MHz 3 Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance Input/Output Capacitance MOTOROLA FAST SRAM Symbol Min I lkg(I) — I lkg(O) — MCM69P737–3.5 I DDA — ...

Page 10

... MCM69P737–4 133 MHz Max Min Max Unit Notes — 7.5 — ns — 3 — — 3 — 3.8 — 3.5 — 3.8 ns — 0 — — 1.5 — — 0 — 3.5 — 3 6.7 1.5 7 — 1.5 — ns — 0.5 — ns MOTOROLA FAST SRAM ...

Page 11

... Figure 3. Lumped Capacitive Load and Typical Derating Curve INPUT WAVEFORM OUTPUT WAVEFORM NOTES: 1. Input waveform has a slew rate of 1 V/ns. 2. Rise time is measured from 0.5 to 2.0 V unloaded. 3. Fall time is measured from 2.0 to 0.5 V unloaded. Figure 4. Unloaded Rise and Fall Time Characterization MOTOROLA FAST SRAM ...

Page 12

... Pull–Up for 3.3 V I/O Supply (c) Pull–Down – 38 – 105 CURRENT (mA) – 50 – 100 – 150 CURRENT (mA CURRENT (mA) MOTOROLA FAST SRAM ...

Page 13

... MOTOROLA FAST SRAM MCM69P737 13 ...

Page 14

... Force the control signals to an inactive state (this guarantees any potential source of noise on the clock input will not start an unplanned on activity). Force the address inputs to a low state. STOP CLOCK WITH READ TIMING Q(A1) CLOCK STOP (CONTINUE BURST READ Q(A2) WAKE UP ADSP (INITIATES BURST READ) MOTOROLA FAST SRAM ...

Page 15

... NOTE: While the clock is stopped, DATA IN must be fixed in a high ( low ( state to reduce the DC current of the input buffers. For lowest power operation, all data and address lines should be held in a low ( state and control lines held in an inactive state. MOTOROLA FAST SRAM STOP CLOCK WITH WRITE TIMING D( FIXED (SEE NOTE) HIGH– ...

Page 16

... For lowest power operation, all data and address lines should be held in a low ( state and control lines held in an inactive state. MCM69P737 FIXED (SEE NOTE) HIGH–Z DATA CLOCK STOP (DESELECTED) WAKE UP MOTOROLA FAST SRAM ...

Page 17

... MCM 69P737 Blank = Trays Tape and Reel Speed (3.5 = 3.5 ns, 3.8 = 3.8 ns ns) Package (ZP = PBGA TQFP) MCM69P737ZP3.8 MCM69P737ZP3.5R MCM69P737ZP3.8R MCM69P737TQ3.5 MCM69P737TQ3.8 MCM69P737TQ3.5R MCM69P737TQ3. ADSP ADSC ADV SE1 SE2 LBO D(E) D(F) D(G) D(H) WRITES MCM69P737ZP4 MCM69P737ZP4R MCM69P737TQ4 MCM69P737TQ4R MCM69P737 17 ...

Page 18

... DIMENSION b IS THE MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. MILLIMETERS DIM MIN MAX A ––– 2.40 A1 0.50 0.70 A2 1.30 1.70 A3 0.80 1.00 D 22.00 BSC D1 20.32 BSC D2 19.40 19.60 E 14.00 BSC E1 7.62 BSC E2 11.90 12.10 b 0.60 0.90 e 1.27 BSC MOTOROLA FAST SRAM ...

Page 19

... D1 TIPS 0.20 (0.008) C A–B A –H– –C– SEATING PLANE 0.05 (0.002 VIEW AB MOTOROLA FAST SRAM TQ PACKAGE TQFP CASE 983A– TIPS 0.20 (0.008) C A–B D –D– E/2 –B– E1 D ...

Page 20

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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