W83977TF-AW Winbond, W83977TF-AW Datasheet
W83977TF-AW
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W83977TF-AW Summary of contents
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... W83977TF WINBOND I/O ...
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... W83977TF Data Sheet Revision History Pages Dates 1 n.a. 05/20/97 IV,V,6,7,14,49,5 2 07/01/97 5,69-80,87-96, 103,113, 117, 118,122, 128, 149 3 III,3,68,134, 07/20/97 146,148; 64-67 4 P101,101.1,102 11/18/97 P1,3,49,62,64, 5 03/19/98 67,71,73,74, 100,117,119, 120,129 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners ...
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... MULTI-MODE PARALLEL PORT ...........................................................................................................9 1.6 FDC INTERFACE ......................................................................................................................................14 1.7 KBC INTERFACE......................................................................................................................................15 1.8 POWER PINS .............................................................................................................................................16 1.9 ACPI INTERFACE.....................................................................................................................................16 2. FDC FUNCTIONAL DESCRIPTION ................................................................................ 17 2.1 W83977TF FDC .........................................................................................................................................17 2.1.1 AT INTERFACE.............................................................................................................................17 2.1.2 FIFO (DATA) ..................................................................................................................................17 2.1.3 DATA SEPARATOR .....................................................................................................................18 2.1.4 WRITE PRECOMPENSATION ...................................................................................................18 2.1.5 PERPENDICULAR RECORDING MODE .................................................................................18 2.1.6 FDC CORE ......................................................................................................................................19 2.1.7 FDC COMMANDS ........................................................................................................................19 2.2 REGISTER DESCRIPTIONS ...................................................................................................................29 2.2.1 STATUS REGISTER A (SA REGISTER) (READ BASE ADDRESS + 0).............................29 2 ...
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... BIT MAP OF PARALLEL PORT AND EPP REGISTERS .......................................................53 5.2.7 EPP PIN DESCRIPTIONS ............................................................................................................54 5.2.8 EPP OPERATION ..........................................................................................................................54 5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT .....................................................................55 5.3.1 ECP REGISTER AND MODE DEFINITIONS...........................................................................55 5.3.2 DATA AND ECPAFIFO PORT....................................................................................................56 5.3.3 DEVICE STATUS REGISTER (DSR).........................................................................................56 5.3.4 DEVICE CONTROL REGISTER (DCR) ....................................................................................57 Publication Release Date: March 1998 - II - W83977TF Revision 0.62 ...
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... GENERAL PURPOSE I/O....................................................................................................69 7.1 BASIC I/O FUNCTIONS...........................................................................................................................71 7.2 ALTERNATE I/O FUNCTIONS ..............................................................................................................73 7.2.1 INTERRUPT STEERING..............................................................................................................73 7.2.2 WATCH DOG TIMER OUTPUT .................................................................................................74 7.2.3 POWER LED...................................................................................................................................74 7.2.4 GENERAL PURPOSE ADDRESS DECODER..........................................................................74 7.2.5 GENERAL PURPOSE WRITE STROBE....................................................................................74 8. PLUG AND PLAY CONFIGURATION ............................................................................ 75 8.1 COMPATIBLE PNP...................................................................................................................................75 8.1.1 EXTENDED FUNCTION REGISTERS......................................................................................75 .................................................67 .........................................................67 ............................................67 Publication Release Date: March 1998 - III - W83977TF Revision 0.62 ...
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... GENERAL PURPOSE EVENT 1 STATUS REGISTER 2 (GP1STS2)...................................90 9.3.19 GENERAL PURPOSE EVENT 1 ENABLE REGISTER 1 (GP1EN1)....................................91 9.3.20 GENERAL PURPOSE EVENT 1 ENABLE REGISTER 2 (GP1EN2)....................................91 9.3.21 BIT MAP CONFIGURATION REGISTERS...............................................................................92 10. SERIAL IRQ ......................................................................................................................... 10.1 START FRAME .........................................................................................................................................94 10.2 IRQ/DATA FRAME...................................................................................................................................94 10.3 STOP FRAME ............................................................................................................................................94 10.4 RESET AND INITIALIZATION ..............................................................................................................95 11. CONFIGURATION REGISTER.......................................................................................96 Publication Release Date: March 1998 - IV - W83977TF 93 Revision 0.62 ...
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... EPP DATA OR ADDRESS READ CYCLE (EPP VERSION 1.9)......................................139 13.3.3 EPP DATA OR ADDRESS WRITE CYCLE (EPP VERSION 1.9) ....................................140 13.3.4 EPP DATA OR ADDRESS READ CYCLE (EPP VERSION 1.7)......................................141 13.3.5 EPP DATA OR ADDRESS WRITE CYCLE (EPP VERSION 1.7) ....................................142 13.3.6 PARALLEL PORT FIFO TIMING...........................................................................................142 Publication Release Date: March 1998 - V - W83977TF Revision 0.62 ...
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... GPIO WRITE TIMING DIAGRAM .......................................................................................................146 13.6 MASTER RESET (MR) TIMING...........................................................................................................146 14. APPLICATION CIRCUITS .............................................................................................147 14.1 PARALLEL PORT EXTENSION FDD.................................................................................................147 14.2 PARALLEL PORT EXTENSION 2FDD...............................................................................................147 14.3 FOUR FDD MODE ..................................................................................................................................148 15. ORDERING INFORMATION.........................................................................................148 16. HOW TO READ THE TOP MARKING .......................................................................148 17. PACKAGE DIMENSIONS...............................................................................................149 Publication Release Date: March 1998 - VI - W83977TF Revision 0.62 ...
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... RAM bank. Keyboard BIOS firmware is available with optional AMIKEY TM MultiKey/ customer code. The W83977TF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. ...
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... Programmable baud generator allows division of 1.8461 Mhz and 24 Mhz Maximum baud rate up to 921k bps for 14.769 Mhz and 1.5M bps for 24 Mhz SCI signal issued from any of the 13 IQRs pins or GPIO xx -2- W83977TF PRELIMINARY 16 -1) Publication Release Date: April 1998 ...
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... Keyboard wake-up by programmable keys Mouse wake-up by programmable buttons Package 128-pin PQFP TM TM and Windows98 (Memphis Compatible with IEEE 1284 specification Compatible with IEEE 1284 specification TM TM -2, Phoenix MultiKey/42 3 dedicate, 20 optional Publication Release Date: April 1998 -3 - W83977TF PRELIMINARY customer code Revision 0.62 ...
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... -4- W83977TF PRELIMINARY / / ...
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... System data bus bits 6-7 CPU I/O read signal CPU I/O write signal System address bus enable In EPP Mode, this pin is the IO Channel Ready output to extend the host read/write cycle. Master Reset; Active high low during normal operations. Publication Release Date: April 1998 -5 - W83977TF PRELIMINARY Revision 0.62 ...
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... Terminal Count. When active, this pin indicates termination of a DMA transfer. Interrupt request 1 Interrupt request 3 Interrupt request 4 Interrupt request 5 Interrupt request 6 Interrupt request 7 Interrupt request 8 Interrupt request 9 Interrupt request 10 Interrupt request 11 Interrupt request 12 Publication Release Date: April 1998 -6- W83977TF PRELIMINARY Revision 0.62 ...
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... General purpose I/O port 2 bit 4 (CR2A bit 5_4 = 01) Alternate Function from GP24: KBC P16 I/O port KBC P13 I/O port. (CR2A bit 5_4 = 10) General purpose I/O port 2 bit 5. Alternate Function from GP25: GATE A20 (KBC P21) Publication Release Date: April 1998 -7 - W83977TF PRELIMINARY is active low by the power Revision 0.62 ...
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... PEN48, which provides the power-on value for CR24 bit 6 (EN48). A 4.7 k resistor is recommended if intends to pull up. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Publication Release Date: April 1998 -8- W83977TF PRELIMINARY Revision 0.62 ...
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... EXTENSION FDD MODE: WD2 This pin is for Extension FDD B; its function is the same as the WD pin of FDC. EXTENSION 2FDD MODE: WD2 This pin is for Extension FDD A and B; its function is the same as the WD pin of FDC. Publication Release Date: April 1998 -9 - W83977TF PRELIMINARY Revision 0.62 ...
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... EXTENSION FDD MODE: HEAD2 This pin is for Extension FDD B; its function is the same as the HEADpin of FDC. EXTENSION 2FDD MODE: HEAD2 This pin is for Extension FDD A and B; its function is the same as the HEAD pin of FDC. Publication Release Date: April 1998 -10- W83977TF PRELIMINARY Revision 0.62 ...
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... EXTENSION FDD MODE: DRVDEN0 This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC. EXTENSION 2FDD MODE: DRVDEN0 This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC. -11 - W83977TF PRELIMINARY Publication Release Date: April 1998 Revision 0.62 ...
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... This pin is for Extension FDD B; the function of this pin is the same as the WP pin of FDC pulled high internally. EXTENSION. 2FDD MODE: WP2 This pin is for Extension FDD A and B; the function of this pin is the same as the WP pin of FDC pulled high internally. Publication Release Date: April 1998 -12- W83977TF PRELIMINARY Revision 0.62 ...
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... ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION. 2FDD MODE: MOA2 This pin is for Extension FDD A; its function is the same as the MOA pin of FDC. Publication Release Date: April 1998 -13 - W83977TF PRELIMINARY Revision 0.62 ...
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... Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. Drive Select B. When set to 0, this pin enables disk drive B. This is an open drain output. Publication Release Date: April 1998 -14- W83977TF PRELIMINARY Revision 0.62 ...
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... General purpose I/O port 1 bit 1. (CR2A bit Alternate Function from GP11: Interrupt channel input. W83C45 Keyboard Reset (P20) Output. (CR2A bit default) General purpose I/O port 1 bit 2. (CR2A bit Alternate Function 1 from GP12 : Watchdog timer output. Publication Release Date: April 1998 -15 - W83977TF PRELIMINARY This Revision 0.62 ...
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... VBAT 64 NA XTAL1 XTAL2 FUNCTION W83C45 KINH (P17) Input. (CR2B bit default) General purpose I/O port 1 bit 3. (CR2B bit FUNCTION FUNCTION battery voltage input 32.768Khz Clock Input 32.768Khz Clock Output Publication Release Date: April 1998 -16- W83977TF PRELIMINARY Revision 0.62 ...
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... FDC FUNCTIONAL DESCRIPTION 2.1 W83977TF FDC The floppy disk controller of the W83977TF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports bits/sec data rate ...
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... A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk. W83977TF Publication Release Date: April 1998 -18- PRELIMINARY Revision 0 ...
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... FDC Core The W83977TF FDC is capable of performing twenty commands. Each command is initiated by a multi- byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. Command The microprocessor issues all required information to the controller to perform a specific operation. ...
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... HDS DS1 DS0 -20- W83977TF PRELIMINARY REMARKS Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: April 1998 Revision 0.62 ...
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... HDS DS1 DS0 Publication Release Date: April 1998 -21 - W83977TF PRELIMINARY REMARKS Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Revision 0.62 ...
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... HDS DS1 DS0 Publication Release Date: April 1998 -22- W83977TF PRELIMINARY REMARKS Command codes Sector ID information prior to command execution Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT Status information after ...
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... HDS DS1 DS0 Publication Release Date: April 1998 -23 - W83977TF PRELIMINARY REMARKS Command codes The first correct ID information on the cylinder is stored in Data Register Status information after command execution Disk status after the command has been completed REMARKS ...
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... HDS DS1 DS0 Publication Release Date: April 1998 -24- W83977TF PRELIMINARY REMARKS Command code Enhanced controller REMARKS Command codes Sector ID information prior to Command execution Data transfer between the FDD and system Status information after Command execution Sector ID information after Command execution Revision 0 ...
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... HDS DS1 DS0 Publication Release Date: April 1998 -25 - W83977TF PRELIMINARY REMARKS Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Revision 0.62 ...
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... DS1 DS0 -26- W83977TF PRELIMINARY REMARKS Command codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters Status information after command execution REMARKS Command codes Head retracted to Track 0 Interrupt REMARKS Command code Status information at the end ...
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... HDS DS1 DS0 -27 - W83977TF PRELIMINARY REMARKS Command codes REMARKS Command codes Head positioned over proper cylinder on diskette REMARKS Configure information Internal registers written REMARKS Command codes Publication Release Date: April 1998 Revision 0.62 ...
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... HDS DS1 DS0 -28- W83977TF PRELIMINARY REMARKS Registers placed in FIFO REMARKS Command Code REMARKS Command Code REMARKS Command Code Status information about disk drive REMARKS Invalid codes (no operation- FDC goes to standby state) ST0 = 80H Publication Release Date: April 1998 ...
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... Register Descriptions There are several status, data, and control registers in W83977TF. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 2.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, ...
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... This bit indicates the complement of latched STEP output. TRAK0 (Bit 4): This bit indicates the complement of TRAK0 input. HEAD (Bit 3): This bit indicates the value of HEAD output. 0 side 1 1 side DIR WP INDEX HEAD TRAK0 STEP F/F DRQ INIT PENDING -30- W83977TF PRELIMINARY Publication Release Date: April 1998 Revision 0.62 ...
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... MOT EN A (Bit 0) This bit indicates the complement of the MOA output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows MOT EN A MOT RDATA Toggle WDATA Toggle Drive SEL0 -31 - W83977TF PRELIMINARY Publication Release Date: April 1998 Revision 0.62 ...
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... DSD (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected DSC (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected DSC DSD WE F/F RDATA F/F WD F/F DSA DSB DRV2 -32- W83977TF PRELIMINARY Publication Release Date: April 1998 Revision 0.62 ...
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... Tape sel 0 Tape sel 1 Logical Device 0 CRF0 Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1 -33 - W83977TF PRELIMINARY bit:0), the bit definitions Publication Release Date: April 1998 Revision 0.62 ...
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... Transition to LOW state indicates execution phase has ended. DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor. -34- W83977TF PRELIMINARY 4, ...
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... DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET PRECOMPENSATION DELAY 250K - 1 Mbps Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 0.00 nS (disabled) Publication Release Date: April 1998 -35 - W83977TF PRELIMINARY 2 Mbps Tape drive Default Delays 20.8 nS 41.17 nS 62.5nS 83.3 nS 104.2 nS 125.00 nS 0.00 nS (disabled) Revision 0.62 ...
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... This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83977TF, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. ...
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... During execution of the read data or scan command 0 No error Not used. This bit is always US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready WP Write Protected FT Fault -37 - W83977TF PRELIMINARY Publication Release Date: April 1998 Revision 0.62 ...
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... Reserved for the hard disk controller x During a read of this register, these bits are in tri-state DSKCHG HIGH DENS DRATE0 DRATE1 DSKCHG DRATE0 DRATE1 NOPREC DMAEN DSKCHG -38- W83977TF PRELIMINARY , Publication Release Date: April 1998 Revision 0.62 ...
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... This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC DRATE0 DRATE1 NOPREC -39 - W83977TF PRELIMINARY DRATE0 DRATE1 Publication Release Date: April 1998 Revision 0.62 ...
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... Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB) Publication Release Date: March 1998 - 40 - W83977TF PRELIMINARY Revision 0.62 ...
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... CTS DSR RI Falling Toggling Toggling Edge (TCTS) (TDSR) (FERI) Bit 0 Bit 1 Bit 2 Bit 0 Bit 1 Bit 2 Bit 8 Bit 9 Bit W83977TF PRELIMINARY Data RX Data RX Data Bit 3 Bit 4 Bit 5 TX Data TX Data TX Data Bit 3 Bit 4 Bit 5 HSR 0 0 Interrupt ...
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... RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI) Publication Release Date: March 1998 - 42 - W83977TF PRELIMINARY Revision 0.62 ...
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... This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable Publication Release Date: March 1998 - 43 - W83977TF PRELIMINARY Revision 0.62 ...
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... CTS, Loopback RI input ( bit 2 of HCR) DCD CTS toggling (TCTS) DSR toggling (TDSR) RI falling edge (FERI) DCD toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD) Publication Release Date: March 1998 - 44 - W83977TF PRELIMINARY Revision 0.62 ...
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... Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before other bits of UFR are programmed FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB Publication Release Date: March 1998 - 45 - W83977TF PRELIMINARY Revision 0.62 ...
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... W83977TF PRELIMINARY Publication Release Date: March 1998 - 46 - Revision 0.62 ...
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... RX FIFO. TBR empty 1. TCTS = 1 2. TDSR = 1 3. FERI = 1 4. TDCD = 1 Publication Release Date: March 1998 - 47 - W83977TF PRELIMINARY Clear Interrupt - Read USR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 1. Write data into TBR 2 ...
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... RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI) Publication Release Date: March 1998 - 48 - W83977TF PRELIMINARY 16 -1. The output frequency of Revision 0.62 ...
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... Publication Release Date: March 1998 - 49 - W83977TF PRELIMINARY Error Percentage between desired and actual ** ** 0.18% 0.099 0.53 Revision 0.62 ...
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... INFRARED (IR) PORT The Infrared (IR) function provides point-to-point (or multi-point to multi-point) wireless communication which can operate under various transmission protocols including IrDA 1.0 SIR, SHARP ASK-IR. IR port shares the same port with UART B port in W83977TF. Please refer to section 11.5 for configuration information. 5. PARALLEL PORT 5 ...
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... Data port (R/W) Printer status buffer (Read) Printer control latch (Write) Printer control swapper (Read) EPP address port (R/W) EPP data port 0 (R/W) EPP data port 1 (R/W) EPP data port 2 (R/W) EPP data port 2 (R/W) Publication Release Date: March 1998 - 50 - W83977TF PRELIMINARY EXT2FDD PIN EXTFDD ATTRIBUTE --- --- --- I INDEX 2 ...
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... A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect TMOUT ERROR SLCT PE ACK BUSY Publication Release Date: March 1998 - 51 - W83977TF PRELIMINARY Revision 0.62 ...
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... The address port is available only in EPP mode. Bit definitions are as follows STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR Publication Release Date: March 1998 - 52 - W83977TF PRELIMINARY PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Revision 0.62 ...
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... IRQEN SLIN 1 DIR IRQ SLIN PD6 PD PD4 PD3 5 PD6 PD PD4 PD3 5 PD6 PD PD4 PD3 5 Publication Release Date: March 1998 - 53 - W83977TF PRELIMINARY PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD2 PD1 PD0 1 1 TMOUT INIT AUTOFD STROBE INIT AUTOFD STROBE ...
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... EPP Data Port 2 (R/W) PD7 PD6 EPP Data Port 3 (R/W) PD7 PD6 PD PD4 PD3 PD2 5 PD PD4 PD3 PD2 5 Publication Release Date: March 1998 - 54 - W83977TF PRELIMINARY PD1 PD0 PD1 PD0 Revision 0.62 ...
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... EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high. W83977TF PRELIMINARY EPP DESCRIPTION Publication Release Date: March 1998 - 55 - Revision 0 ...
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... R/W All CR60 and 61, which are determined by configuration register or hardware setting. DESCRIPTION CRF0 to select ECP/EPP mode) Publication Release Date: March 1998 - 56 - W83977TF PRELIMINARY FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO ...
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... These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Address or RLE Address/RLE nFault Select PError nAck nBusy Publication Release Date: March 1998 - 57 - W83977TF PRELIMINARY Revision 0.62 ...
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... Bit 2: This bit is output to the INIT output. Bit 1: This bit is inverted and output to the AFD output. Bit 0: This bit is inverted and output to the STB output strobe autofd nInit SelectIn ackIntEn Direction Publication Release Date: March 1998 - 58 - W83977TF PRELIMINARY Revision 0.62 ...
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... Bit 7: This bit is read-only low level during a read. This means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts IRQx 0 IRQx 1 IRQx 2 intrValue compress Publication Release Date: March 1998 - 59 - W83977TF PRELIMINARY Revision 0.62 ...
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... Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. IRQ resource empty full service Intr dmaEn nErrIntrEn MODE MODE MODE Publication Release Date: March 1998 - 60 - W83977TF PRELIMINARY . Revision 0.62 ...
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... PD5 PD4 PD3 PD2 PError Select nFault Directio ackIntEn SelectIn nInit nErrIntrEn dmaEn serviceIntr Publication Release Date: March 1998 - 61 - W83977TF PRELIMINARY D1 D0 NOTE PD1 PD0 autofd strobe full empty ...
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... ECP Mode. This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. This signal is always deasserted in ECP mode. Publication Release Date: March 1998 - 62 - W83977TF PRELIMINARY Revision 0.62 ...
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... PeriphAck is low. The most significant bit of the command is always zero. 5.3.13.3 Data Compression The W83977TF supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo ...
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... I/O will empty or fill the FIFO using the appropriate direction and mode. 5.4 Extension FDD Mode (EXTFDD) In this mode, the W83977TF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 5-1. ...
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... KEYBOARD CONTROLLER The KBC (8042 with licensed KB BIOS) circuit of W83977TF is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBM compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer ...
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... Auxiliary device output buffer full 0: No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error) FUNCTION BIT DEFINITION Reserved IBM Keyboard Translate Mode Disable Auxiliary Device Disable Keyboard Reserve System Flag Enable Auxiliary Interrupt Enable Keyboard Interrupt Publication Release Date: March 1998 - 66 - W83977TF PRELIMINARY Revision 0.62 ...
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... Auxiliary Device "Data" line is stuck low Auxiliary Device "Data" line is stuck low BIT DEFINITION No Error Detected Keyboard "Clock" line is stuck low Keyboard "Clock" line is stuck high Keyboard "Data" line is stuck low Keyboard "Data" line is stuck high Publication Release Date: March 1998 - 67 - W83977TF PRELIMINARY Revision 0.62 ...
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... A "1" on this bit causes KBRESET to drive low for 6 S(Min.) with 14 S(Min.) delay. Before issuing another keyboard reset command, the bit must be cleared Res. (1) Res. (0) Res. (0) Publication Release Date: March 1998 - 68 - W83977TF PRELIMINARY P92EN HGA20 HKBRST Res. (1) SGA20 PLKBRST Revision 0 ...
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... CR-E0 determines which button (left or right) to perform wake-up function. chipset TX, LX PIIX4) panel switch input. The wake-up conditions pin must be connected to + blocked to PANSWIN PANSWOUT Publication Release Date: March 1998 - 69 - W83977TF PRELIMINARY pin, and connect PANSWOUT To implement this function ATX SB pin to store the data (the BAT , by setting LD-0A CR-E0 properly Revision 0 ...
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... GENERAL PURPOSE I/O W83977TF provides 23 Input/Output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. Those 23 GP I/O ports are divided into three groups, the first group contains 8 ports, the second group contains only 7 ports, and the third group contains 8 ports ...
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... W83977TF Figure 7.2 Figure 7.3 Publication Release Date:March 1998 -70 - PRELIMINARY Revision 0.62 ...
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... Non-inverted output bit value of GP2 drive to Common Interrupt 1 Inverted output bit value of GP2 drive to Common Interrupt 0 Basic non-inverting input 1 Basic inverting input 0 Non-inverted input drive to Common Interrupt 1 Inverted input drive to Common Interrupt Publication Release Date:March 1998 -71 - W83977TF PRELIMINARY three 8-bit Revision 0.62 ...
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... BIT 6 GP16 BIT 7 GP17 BIT 0 GP20 BIT 1 GP21 BIT 2 GP22 BIT 3 GP23 BIT 4 GP24 BIT 5 GP25 BIT 6 GP26 BIT 0 GP30 BIT 1 GP31 BIT 2 GP32 BIT 3 GP33 BIT 4 GP34 BIT 5 GP35 BIT 6 GP36 BIT 7 GP37 Publication Release Date:March 1998 -72 - W83977TF PRELIMINARY Revision 0.62 ...
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... ALTERNATE FUNCTION can be programmed to map their own interrupt channels. The configuration registers CR70 and CR72 of logical device 7 Publication Release Date:March 1998 -73 - W83977TF PRELIMINARY GP I/O ports. Table Revision 0.62 ...
Page 84
... GP14 and at CR62-65 of logical device output is normally active low. Users can alter its polarity GP32, and GP33's configuration register. Publication Release Date:March 1998 -74 - W83977TF PRELIMINARY POWER LED STATE 1 Hertz Toggle pulse Continuous high or low * Continuous high or low * 1 Hertz Toggle pulse ...
Page 85
... The W83977TF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83977TF, there are nine Logical Devices 0 to Logical Device A with the exception of logical device 4 and 6 for compatibility) to nine individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2), UART2 (logical device 3), KBC (logical device 5), GPIO1 (logical device 7), GPIO2 (logical device 8), GPIO3 (logical device 9), and ACPI ((logical device A) ...
Page 86
... The EFIRs are write-only registers with port address 3F0h or 370h (as described in section 8.1.1) on PC/AT systems; the EFDRs are read/write registers with port address 3F1h or 371h (as described in section 8.1.1) on PC/AT systems. enters the default operating mode. Before the Publication Release Date:March 1998 -76 - W83977TF PRELIMINARY W83977TF Revision 0.62 ...
Page 87
... ACPI REGISTERS FEATURES W83977TF supports both ACPI and legacy power managements. The switch logic of the power managment block generates an SMI interrupt in the legacy mode and an SCI interrupt in the ACPI mode. For the legacy mode, the SMI_EN bit is used set, it routes the power management events to the SMI interrupt logic ...
Page 88
... ACPI software. If BIOS_RLS is set by the BIOS software and GBL_EN is set by the ACPI software, an SCI interrupt is raised. Writing BIOS_RLS sets it to logic 1 and also sets GBL_STS to logic 1. Writing BIOS_RLS has no effect. Wrinting GBL_STS clears it to logic 0 and also clears BIOS_RLS to logic 0. Writing GBL_STS has no effect. W83977TF PRELIMINARY clear GBL_STS ...
Page 89
... See the following figure for illustration. TMR_ON 3.579545 MHz TMR_STS 24 bit counter Bits (23-0) 24 TMR_EN TMR_VAL Publication Release Date:March 1998 -79 - W83977TF PRELIMINARY The power There are no timer reset To SCI Logic Revision 0.62 ...
Page 90
... Power Management 1 Status Register 1 (PM1STS1) Register Location: <CR60, 61> System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits TMR_STS Reserved Reserved Reserved BM_STS GBL_STS Reserved Reserved Publication Release Date:March 1998 -80 - W83977TF PRELIMINARY interrupt could be Reverved or The base address of general- Revision 0.62 ...
Page 91
... When the WAK_STS is cleared and all devices are in sleeping state, the whole chip enters the sleeping state. Description This bit is set when the BIOS wants the Reserved Reserved Reserved Reserved Reserved Reserved Reserved WAK_STS Description Publication Release Date:March 1998 -81 - W83977TF PRELIMINARY Revision 0.62 ...
Page 92
... Bit Name 0-7 Reserved Reserved. These bits always return zeros TMR_EN Reserved Reserved Reserved GBL_EN Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Publication Release Date:March 1998 -82 - W83977TF PRELIMINARY Revision 0.62 ...
Page 93
... Reserved. These bits always return zeros SCI_EN BM_RLD GBL_RLD Reserved Reserved Reserved Reserved Reserved Description When this bit is set, then the power management events will Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Publication Release Date:March 1998 -83 - W83977TF PRELIMINARY Revision 0.62 ...
Page 94
... Bit Name 0-7 Reserved Reserved. These bits always return zeros Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Publication Release Date:March 1998 -84 - W83977TF PRELIMINARY Revision 0.62 ...
Page 95
... System I/O Space Default Value: 00h Attribute: Read only Size: 8 bits TMR_VAL0 TMR_VAL1 TMR_VAL2 TMR_VAL3 TMR_VAL4 TMR_VAL5 TMR_VAL6 TMR_VAL7 Description TMR_VAL8 TMR_VAL9 TMR_VAL10 TMR_VAL11 TMR_VAL12 TMR_VAL13 TMR_VAL14 TMR_VAL15 Publication Release Date:March 1998 -85 - W83977TF PRELIMINARY Revision 0.62 ...
Page 96
... TMR_STS bit is set any time the last bit of the timer (bit 23) goes from from the TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. Description TMR_VAL16 TMR_VAL17 TMR_VAL18 TMR_VAL19 TMR_VAL20 TMR_VAL21 TMR_VAL22 TMR_VAL23 Description Publication Release Date:March 1998 -86 - W83977TF PRELIMINARY Revision 0.62 ...
Page 97
... IRQ to the SCI logic input is ignored and no SCI interrupt will be raised. bit is not Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description URBSCISTS URASCISTS FDCSCISTS PRTSCISTS KBCSCISTS MOUSCISTS Reserved Reserved Publication Release Date:March 1998 -87 - W83977TF PRELIMINARY Revision 0.62 ...
Page 98
... Bit Name 0-7 Reserved Reserved. These bits always return zeros. Description status, which is set by the KBC IRQ. status, which is set by the MOUSE IRQ Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Publication Release Date:March 1998 -88 - W83977TF PRELIMINARY Revision 0.62 ...
Page 99
... System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits URBSCIEN URASCIEN FDCSCIEN PRTSCIEN KBCSCIEN MOUSCIEN Reserved Reserved (KBCSCIEN and KBCSCISTS) or Description enable, which controls the KBC IRQ. enable, which controls the MOUSE IRQ. Publication Release Date:March 1998 -89 - W83977TF PRELIMINARY Revision 0.62 ...
Page 100
... Register Location: <CR64, 65> Default Value: 00h Attribute: Read/write Size: 8 bits Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description System I/O Space BIOS_STS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description System I/O Space Publication Release Date:March 1998 -90 - W83977TF PRELIMINARY Revision 0.62 ...
Page 101
... Default Value: 00h Attribute: Read/write Size: 8 bits Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description System I/O Space BIOS_EN TMR_ON Reserved Reserved Reserved Reserved Reserved Reserved Description System I/O Space Publication Release Date:March 1998 -91 - W83977TF PRELIMINARY Revision 0.62 ...
Page 102
... GBL_EN TMR_VAL6 TMR_VAL5 TMR_VAL4 TMR_VAL14 TMR_VAL13 TMR_VAL12 TMR_VAL22 TMR_VAL21 TMR_VAL20 -92 - W83977TF PRELIMINARY Wrinting BM_STS clears BM_STS GBL_RLS TMR_VAL3 TMR_VAL2 ...
Page 103
... SERIAL IRQ W83977TF supports a serial IRQ scheme. This allow a signal line to be used to report the legacy ISA interrupt rerquests. Because more than one device may need to share the signal serial IRQ signal line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is transfered on the IRQSER signal, one cycle consisting of three frames types: a start frame, several IRQ/Data frame, and one Stop frame ...
Page 104
... Stop Frame is low for 2 clocks, the next IRQSER cycle's Sample mode is the Quiet mode. If the Stop Frame is low for 3 clocks, the next IRQSER cycle's Sample mode is the Continuous mode. IOCHCK FRAME STOP FRAME STOP None Host Controller T=Turn-around S=Sample Publication Release Date:March 1998 -94 - W83977TF PRELIMINARY NEXT CYCLE START I=Idle Revision 0.62 ...
Page 105
... Start IRQ0 IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK INTA INTB INTC INTD Unassigned Publication Release Date:March 1998 -95 - W83977TF PRELIMINARY Revision 0.62 ...
Page 106
... Address Qualification = 1 16 bit Address Qualification Bit 6: EN48 = 0 The clock input on Pin 1 should be 24 Mhz The clock input on Pin 1 should be 48 Mhz. The corresponding power-on setting pin is SOUTB (pin 53). 0x73 (read only). Publication Release Date: March 1998 -96 - W83977TF PRELIMINARY Revision 0.62 ...
Page 107
... Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective on selecting IRQ = 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not effective on selecting IRQ PNPCSV The corresponding power-on Publication Release Date: March 1998 -97 - W83977TF PRELIMINARY must be complementary PNPCSV to 0 PNPCSV is 1. Revision 0.62 ...
Page 108
... External two FDC Mode CR2A (Default 0x00) Bit 7: PIN57S = 0 KBRST = 1 GP12 Bit 6: PIN56S = 0 GA20 = 1 GP11 Bit PIN40S1, PIN40S0 = 00 Reserved = 01 GP24 = 10 8042 P13 = 11 Reserved Bit Reserved. Bit PIN3S1, PIN3S0 = 00 DRVDEN1 = 01 GP10 = 10 8042 P12 SCI = 11 Publication Release Date: March 1998 -98 - W83977TF PRELIMINARY Revision 0.62 ...
Page 109
... Reserved Bit PIN103S1, PIN103S0 = 00 IRQ14 = 01 GP14 = 10 PLEDO = 11 Reserved CR2D (Default 0x00) Test Modes: Reserved for Winbond. CR2E (Default 0x00) Test Modes: Reserved for Winbond. CR2F (Default 0x00) Test Modes: Reserved for Winbond. Publication Release Date: March 1998 -99 - W83977TF PRELIMINARY Revision 0.62 ...
Page 110
... Bit 1: FDC DMA Mode = 0 Burst Mode is enabled = 1 Non-Burst Mode (Default during POR, default 0x00 otherwise) if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise during POR, default 0x00 otherwise during POR, default 0x04 otherwise) Publication Release Date: March 1998 -100 - W83977TF PRELIMINARY Revision 0.62 ...
Page 111
... When FDD is in enhanced 3-mode(CRF0.bit0=1),these bits determine SELDEN value in TABLE A of CRF4 and CRF5 as follows. DTYPE1 DPYTE0 Note: X means don't care. DRATE1 DRATE0 SELDEN Publication Release Date: March 1998 -101 - W83977TF PRELIMINARY Revision 0.62 ...
Page 112
... Bit DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A Select Regular drives and 2.88 format = 01 Specifical application = 10 2 Meg Tape = 11 Reserved Bit 2: Reserved. Bit 1:0: DMOD0, DMOD1 : Drive Model select (Refer to TABLE B). CRF5 (Default 0x00) FDD1 Selection: Same as FDD0 of CRF4. Publication Release Date: July 1997 -101.1 - W83977TF PRELIMINARY Revision 0.61 ...
Page 113
... DRVDEN1(pin 3) DRATE0 4/2/1 MB 3.5” “ 2/1 MB 5.25” 2/1.6/1 MB 3.5” (3-MODE) DRATE0 DRATE0 DRATE1 Publication Release Date: March 1998 -102- W83977TF PRELIMINARY SELDEN CRF0 bit 0 DRIVE TYPE Revision 0.62 ...
Page 114
... ECP and EPP - 1.7 mode during POR, default 0x00 otherwise) PNPCSV during POR, default 0x00, 0x00 otherwise) (all modes supported, EPP is only available when the base = 0 during POR, default 0x00 otherwise) Publication Release Date: March 1998 -103- W83977TF PRELIMINARY Revision 0.62 ...
Page 115
... POR, default 0x00 otherwise) if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise during POR, default 0x00 otherwise during POR, default 0x00 otherwise) if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise during POR, default 0x00 otherwise) Publication Release Date: March 1998 -104- W83977TF PRELIMINARY Revision 0.62 ...
Page 116
... Inverting IRTX/SOUTB & 500 KHZ clock Note: The notation is normal mode in the IR function. IRTX high Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX Publication Release Date: March 1998 -105- W83977TF PRELIMINARY IRRX Revision 0.62 ...
Page 117
... Select 12Mhz as KBC clock input Select 16Mhz as KBC clock input. Bit Reserved. Bit Port 92 disable Port 92 enable. if PENKBC= 1 during POR, default 0x00 otherwise) if PENKBC= 1 during POR, default 0x00 otherwise) Publication Release Date: March 1998 -106- W83977TF PRELIMINARY Revision 0.62 ...
Page 118
... Bit 4: IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 3: Select Function Select Alternate Function: Interrupt Steering Select Basic I/O Function. Bit 2: Reserved. Bit 1: Polarity Invert Invert. GP11 Publication Release Date: March 1998 -107- W83977TF PRELIMINARY alternate function Revision 0.62 ...
Page 119
... Bit Reserved. Bit Select Function Select Basic I/O function Select 1st alternate function: Power LED output Reserved = 11 Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: 1: Input, 0: Output Watch Dog Timer Output. Publication Release Date: March 1998 -108- W83977TF PRELIMINARY Revision 0.62 ...
Page 120
... Bit Select Function Select Basic I/O function Select 1st alternate function: Power LED output. Please refer to TABLE Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: 1: Input, 0: Output Watch Dog Timer Output. Publication Release Date: March 1998 -109- W83977TF PRELIMINARY Revision 0.62 ...
Page 121
... Bit These bits select IRQ resource for Watch Dog. WDT_CTRL1 BIT[ GP20~GP26 Publication Release Date: March 1998 -110- W83977TF PRELIMINARY POWER LED STATE 1 Hertz Toggle pulse Continuous high or low* Continuous high or low* 1 Hertz Toggle pulse at Logic Device 8. Revision 0.62 ...
Page 122
... Select Basic I/O function Reserved = 10 Select 2nd alternate function: Keyboard P14 I/ Reserved Bit 2: Int Enable Common IRQ = 0 Disable Common IRQ Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: 1: Input, 0: Output¡ @¡ @ Publication Release Date: March 1998 -111- W83977TF PRELIMINARY Revision 0.62 ...
Page 123
... Bit Reserved. Bit 3: Select Function Select alternate function: GATE A20(Connect to KBC P21 Select basic I/O function Bit 2: Int Enable Common IRQ = 0 Disable Common IRQ Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: 1: Input, 0: Output Publication Release Date: March 1998 -112- W83977TF PRELIMINARY Revision 0.62 ...
Page 124
... Timer is not affected by Mouse interrupt Bit 1: Keyboard interrupt reset Enable or Disable = 1 Watch Dog Timer is reset upon a Keyboard interrupt = 0 Watch Dog Timer is not affected by Keyboard interrupt Bit 0: Reserved. Watch Dog Timer Time-out value, but Counter. Publication Release Date: March 1998 -113- W83977TF PRELIMINARY Watch Dog Revision 0.62 ...
Page 125
... Bit These bits select IRQ resource for GP30 as you setting GP30 alternate function (Interrupt Steering). CR72 (Default 0x00) Bit Reserved. Bit These bits select IRQ resource for GP31 as you setting GP31 alternate function (Interrupt Steering). Timer Status). The ORed signal is self-clearing. Publication Release Date: March 1998 -114- W83977TF PRELIMINARY Revision 0.62 ...
Page 126
... Select Basic I/O Function. Bit 2: Reserved. Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: 1: Input, 0: Output CRE3 (GP33, Default 0x01) Bit Reserved. Bit 3: Select Function Select Alternate Function: General Purpose Address Decode Select Basic I/O Function. Publication Release Date: March 1998 -115- W83977TF PRELIMINARY Revision 0.62 ...
Page 127
... Disable GP33 General Purpose Address Decode. Bit Enable GP32 General Purpose Address Decode Disable GP32 General Purpose Address Decode. *Note: If the logical device's activate bit is not set then bit 0 and 1 have no effect. Publication Release Date: March 1998 -116- W83977TF PRELIMINARY Revision 0.62 ...
Page 128
... Bit 1: MSXKEY. Enable any character received from Mouse to wake-up the system Just clicking Mouse left/right-botton twice can wake the system up Any character received from Mouse can wake the system up (the setting of Bit 4 is ignored). SCI . PANSWOUT . PANSWOUT . PANSWOUT PANSWOUT Publication Release Date: March 1998 -117- W83977TF PRELIMINARY . . PANSWOUT . Revision 0.62 ...
Page 129
... CRF0.bit7 (CHIPPME) is also set to 1. Bit 0: URBPME. UART B power management enable disable the auto power management functions enable the auto power management functions provided CRF0.bit7 (CHIPPME) is also set to 1. PANSWIN . This bit is cleared by Publication Release Date: March 1998 -118- W83977TF PRELIMINARY Revision 0.62 ...
Page 130
... IRQ, any DMA acknowledge, and any transition on BUSY, pins. ACK , PE, SLCT, and ACK Publication Release Date: March 1998 -119- W83977TF PRELIMINARY ERR pins PE, SLCT, and ERR Revision 0.62 ...
Page 131
... SMI interrupt due to printer port's idleness. SMI interrupt due to printer port's idleness. SMI interrupt due to FDC's idleness. SMI interrupt due to FDC's idleness. Publication Release Date: March 1998 -120- W83977TF PRELIMINARY bit is set SMI logics respectively. Revision 0.62 ...
Page 132
... UART A's trap. SMI interrupt due to UART B's trap. SMI interrupt due to UART B's trap. generation due to the device's IRQ. SMI interrupt due to any IRQ of the devices. These 4 bits SMI logics respectively. The Publication Release Date: March 1998 -121- W83977TF PRELIMINARY SMI logic Revision 0.62 ...
Page 133
... SMI interrupt due to UART A's IRQ. SMI interrupt due to UART B's IRQ. SMI interrupt due to UART B's IRQ. SMI event is raised on the output of the SMI interrupt to be generated on the pin Publication Release Date: March 1998 -122- W83977TF PRELIMINARY SMI SMI . If this bit is SMI . Revision 0.62 ...
Page 134
... MAX. UNIT 2.4 uA 2.0 mA 0.8 V 2.0 V 0.4 V 2.4 V +10 A -10 A 0.8 V 2.0 V 0.4 V 2.4 V +10 A -10 A Publication Release Date: March 1998 - 123 - W83977TF PRELIMINARY UNIT CONDITIONS V = 2.5 V BAT V = 5.0 V, All ACPI pins are SB not connected ...
Page 135
... TYP. MAX. 0.3xV DD 0.7xV DD 0.4 3 0.3xV DD 0.7xV DD 0.4 3 0.3xV DD 0.7xV DD 0.4 3 0.3xV DD 0.7xV DD 0.4 3 Publication Release Date: March 1998 - 124 - W83977TF PRELIMINARY UNIT CONDITIONS ...
Page 136
... Input High Leakage I LIH Input Low Leakage I LIL MIN. TYP. MAX. UNIT 0.8 2.0 0.4 2 0.8 2.0 0.4 2 0.4 2.4 0.4 2.4 0.4 0.4 0.8 2.0 +10 -10 Publication Release Date: March 1998 - 125 - W83977TF PRELIMINARY CONDITIONS ...
Page 137
... V 0.5 1 +10 LIH I -10 LIL V 0.5 0.8 1 1.6 2.0 2 0.5 1 +10 LIH I -10 LIL Publication Release Date: March 1998 - 126 - W83977TF PRELIMINARY UNIT CONDITIONS ...
Page 138
... 100 MCY 260/430 AA /510 Publication Release Date: March 1998 - 127 - W83977TF PRELIMINARY TYP. MAX. UNIT (NOTE 360/570 nS /675 360/570 nS /675 Revision 0 ...
Page 139
... TEST MIN. CONDITIONS 135/220 TC /260 1.8/3/3. RST 5 0.5/0.9 IDX /1.0 1.0/1.6 DST /2.0 24/40/48 STD 6.8/11.5 STP /13.8 Note 2 SC 100/185 /225 100/138 /225 Publication Release Date: March 1998 - 128 - W83977TF PRELIMINARY TYP. MAX. UNIT (NOTE 1) 6/12 S /20/ 7/11.7 7.2/11.9 S /14 /14.2 Note 2 Note 2 S 125/210 150/235 S /250 /275 125/210 150/235 ...
Page 140
... Loading MWO T SIM T RIM T 100 pF Loading IAD T 100 pF Loading IID N 100 pF Loading SYM. MIN. TYP 200 t5 Publication Release Date: March 1998 - 129 - W83977TF PRELIMINARY MAX. UNIT 9/16 Baud Rate 1 S 1/16 8/16 Baud Rate 175 nS 9/16 16/16 Baud Rate 1/2 Baud Rate 250 nS 200 ...
Page 141
... Command Deasserted to PD Hi-Z WAIT Deasserted to PD Drive WRITE Deasserted to Command PBDIR Set to Command PD Hi-Z to Command Asserted Asserted to Command Asserted WAIT Deasserted to Command Deasserted Time out WAIT PD Valid to Deasserted WAIT PD Hi-Z to Deasserted W83977TF PRELIMINARY SYM. MIN. MAX ...
Page 142
... PD Invalid to Command Asserted IOW to Command Asserted WAIT Asserted to Command Asserted WAIT Deasserted to Command Deasserted WAIT Command Asserted to Deasserted Time out WAIT Command Deasserted to Asserted IOW WRITE Deasserted to Deasserted and PD invalid W83977TF PRELIMINARY SYM. MIN. MAX ...
Page 143
... Asserted to BUSY Asserted BUSY Asserted to nSTROBE Deasserted 12.3.8 ECP Parallel Port Reverse Timing Parameters PARAMETER PD Valid to nACK Asserted nAUTOFD Deasserted to PD Changed nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted nACK Deasserted to nAUTOFD Asserted PD Changed to nAUTOFD Deasserted W83977TF PRELIMINARY SYMBOL MIN. MAX. t1 600 t2 600 t3 ...
Page 144
... Time from inactive CLK transition, used to time when the auxiliary device sample DATA T25 Time of inhibit mode T26 Time from rising edge of CLK to DATA transition T27 Duration of CLK inactive T28 Duration of CLK active T29 Time from DATA transition to falling edge of CLK W83977TF PRELIMINARY MIN. MAX ...
Page 145
... KCLK/MCLK falling edge to WKUPD edge delay t PANSWOUT WKUPW active pulse width MIN. MIN. falling edge PANSWOUT PANSWOUT Hi-Z falling PANSWOUT 0.5 Publication Release Date: March 1998 - 134 - W83977TF PRELIMINARY MAX. UNIT 300(Note 1) ns MAX. UNIT 200 ns 1 sec Revision 0.62 ...
Page 146
... TRA TDH TDF INDEX TR TC TWA TWW TWD TDW RESET TWI DIR TAA TDST STEP Publication Release Date: March 1998 - 135 - W83977TF PRELIMINARY Write Date TWDD Index TIDX TIDX Terminal Count TTC Reset TRST Drive Seek operation TSTP TSTD TSC Revision 0.62 ...
Page 147
... SERIAL OUT (SOUT) THRS IRQ3 or IRQ4 THR IOW TSI (WRITE THR) IOR (READ TIR) Receiver Timing STAR DATA BITS (5-8) PARITY Transmitter Timing STAR DATA (5-8) PARITY THR Publication Release Date: March 1998 - 136 - W83977TF PRELIMINARY STOP TSINT TRINT STAR STOP (1-2) TSTI TIR Revision 0.62 ...
Page 148
... Printer Interrupt Timing ¢x ¢x ¢x ¢x ¡ö TLAD ¢x ¢x ¢x ¢x ¢x ¢x ¢x Publication Release Date: March 1998 - 137 - W83977TF PRELIMINARY ¢x ¢x ¢x ¡÷ ¡ö TMWO ¢x ¢x ¢x ¢x ¢x TSIM ¢x ¢x ¢ ...
Page 149
... Parallel Port 13.3.1 Parallel Port Timing IOW INIT, STROBE AUTOFD, SLCTIN PD<0:7> ACK IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR (ECP) IRQ Publication Release Date: March 1998 - 138 - W83977TF PRELIMINARY t3 t4 Revision 0.62 ...
Page 150
... EPP Data or Address Read Cycle (EPP Version 1.9) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 t17 PD<0:7> t21 t22 t23 t24 ADDRSTB DATASTB WAIT t18 t19 t25 t27 t26 Publication Release Date: March 1998 - 139 - W83977TF PRELIMINARY t15 t20 t28 Revision 0.62 ...
Page 151
... EPP Data or Address Write Cycle (EPP Version 1.9) A10-A0 SD<0:7> t1 IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT t22 PBDIR t10 t11 t13 t15 t16 t17 t18 t19 t20 Publication Release Date: March 1998 - 140 - W83977TF PRELIMINARY t12 t14 t21 Revision 0.62 ...
Page 152
... EPP Data or Address Read Cycle (EPP Version 1.7) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 t17 PD<0:7> t21 t22 t23 ADDRSTB t24 DATASTB WAIT t18 t19 t25 t26 t27 Publication Release Date: March 1998 - 141 - W83977TF PRELIMINARY t15 t20 t28 Revision 0.62 ...
Page 153
... IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT 13.3.6 Parallel Port FIFO Timing PD<0:7> nSTROBE BUSY t10 t11 t13 t15 t16 t17 t18 t19 t20 t1 t2 >| > t6 >| Publication Release Date: March 1998 - 142 - W83977TF PRELIMINARY t22 t22 t4 >| t3 >| t5 >| Revision 0.62 ...
Page 154
... ECP Parallel Port Forward Timing nAUTOFD PD<0:7> nSTROBE BUSY 13.3.8 ECP Parallel Port Reverse Timing PD<0:7> nACK nAUTOFD Publication Release Date: March 1998 - 143 - W83977TF PRELIMINARY Revision 0.62 ...
Page 155
... RDB D0-D7 13.4.3 Send Data to K/B CLOCK (KCLK) T12 SERIAL DATA START (KDAT ACTIVE T7 DATA ACTIVE T10 T11 DATA OUT T13 T14 T19 Publication Release Date: March 1998 - 144 - W83977TF PRELIMINARY T17 T18 T16 D7 P STOP Revision 0.62 ...
Page 156
... Bit 13.4.7 Receive Data from Mouse MCLK T29 MDAT START D0 T14 T13 T23 T22 T24 T26 T27 T28 Publication Release Date: March 1998 - 145 - W83977TF PRELIMINARY D7 P STOP P STOP Bit P STOP Bit Revision 0.62 ...
Page 157
... GPIO Write Timing Diagram A0-A15 IOW D0-7 GPIO10-17 GPIO20-25 13.6 Master Reset (MR) Timing Vcc MR 13.7 Keyboard/Mouse Wake-up Timing KCLK MCLK PANSWIN PANSWOUT HI-Z tSWL VALID VALID PREVIOUS STATE tVMR tWKUPD tSWZ Publication Release Date: March 1998 - 146 - W83977TF PRELIMINARY VALID tWGO tWKUPW Revision 0.62 ...
Page 158
... RDD2/PD3 5 STEP2/SLIN 17 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension 2FDD Connection Diagram JP13 Publication Release Date: March 1998 - 147 - W83977TF PRELIMINARY JP 13A DCH2 34 33 HEAD2 32 31 RDD2 30 29 WP2 28 27 TRK02 26 25 WE2 24 23 WD2 22 ...
Page 159
... MOB 15.0 ORDERING INFORMATION PART NO. KBC FIRMWARE W83977TF-P Phoenix MultiKey/42 W83977TF-A AMIKEY W83977TF-PW Phoenix MultiKey/42 W83977TF-AW AMIKEY 16.0 HOW TO READ THE TOP MARKING Example: The top marking of W83977TF-A inbond W83977TF-A AM. MEGA. 87-96 730AC2722968SA 1st line: Winbond logo 2nd line: the type number: W83977TF-A 3rd line: the source of KBC F/W -- American Megatrends Incorporated ...
Page 160
... Detail F Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Publication Release Date: March 1998 - 149 - W83977TF PRELIMINARY Dimension in mm Dimension in inch Min Nom Max Min Nom Max 0.25 0.35 0.45 ...