W83977EF-AW Winbond, W83977EF-AW Datasheet
W83977EF-AW
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W83977EF-AW Summary of contents
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... W83977EF-AW /W83977EG-AW NUVOTON ISA I/O W83977EF-AW W83977EG- Publication Release Date: January, 2010 Revision 1.5 ...
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... ORT ...................................................................................................................11 4.6 FDC I NTERFACE .........................................................................................................................................16 4.7 KBC I NTERFACE .........................................................................................................................................18 4.8 POWER PINS ...........................................................................................................................................18 4.9 ACPI I NTERFACE ........................................................................................................................................18 5. FDC FUNCTIONAL DESCRIPTION ...........................................................................................................19 5.1 W83977EF-AW/EG FDC .........................................................................................................................19 5.1.1 AT interface........................................................................................................................................19 5.1.2 FIFO (Data) ........................................................................................................................................19 5.1.3 Data Separator ..................................................................................................................................20 5.1.4 Write Precompensation....................................................................................................................20 5.1.5 Perpendicular Recording Mode ......................................................................................................20 5.1.6 FDC Core ...........................................................................................................................................21 5.1.7 FDC Commands................................................................................................................................21 5 EGISTER ESCRIPTIONS ...........................................................................................................................33 5.2.1 Status Register A (SA Register) (Read base address + 0) ........................................................33 5 ...
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... FDD M (EXTFDD) ..........................................................................................................68 XTENSION ODE 7.5 E 2FDD M (EXT2FDD)......................................................................................................68 XTENSION ODE 8.KEYBOARD CONTROLLER ........................................................................................................................69 8 UTPUT UFFER .........................................................................................................................................69 8 NPUT UFFER .............................................................................................................................................69 8 TATUS EGISTER ......................................................................................................................................70 8.4 C OMMANDS .................................................................................................................................................71 8.5 H GATEA20/K ARDWARE EYBOARD W83977EF-AW /W83977EG-AW (ECP) P ORT .....................................................................................60 ......................................................................................... ESET ONTROL OGIC ...................................................................72 Publication Release Date: January, 2010 -III - Revision 1.5 ...
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... EVICE 13.SPECIFICATIONS ......................................................................................................................................116 13 BSOLUTE AXIMUM ATINGS ...............................................................................................................116 13.2 DC CHARACTERISTICS ....................................................................................................................116 13 HARACTERISTICS ...........................................................................................................................120 13.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec. ..........................................................120 13.3.2 UART/Parallel Port .......................................................................................................................122 W83977EF-AW /W83977EG-AW .................................................................... OUSE AKE P ...........................................................................74 .......................................................................................................85 )......................................................................................................95 ORT I) ......................................................................................................100 II) .....................................................................................................104 Publication Release Date: January, 2010 -IV - Revision 1 ...
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... ISA W T ...................................................................................................................................141 RITE IMING 15. APPLICATION CIRCUITS........................................................................................................................142 15 FDD.........................................................................................................142 ARALLEL ORT XTENSION 15 2FDD.......................................................................................................143 ARALLEL ORT XTENSION 15.3 F FDD M OUR ODE ...................................................................................................................................144 16. ORDERING INFORMATION ..................................................................................................................144 17. TOP MARKING SPECIFICATIONS........................................................................................................144 W83977EF-AW /W83977EG-AW IMING ....................................................................................................139 Publication Release Date: January, 2010 -V - Revision 1.5 ...
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... PACKAGE DIMENSIONS ........................................................................................................................145 19. REVISION HISTORY.................................................................................................................................146 W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -VI - Revision 1.5 ...
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... DMA logic. The wide range of functions integrated onto the W83977EF-AW greatly reduces the number of components required for interfacing with floppy disk drives. The W83977EF-AW/EG-AW supports four 360K, 720K, 1 ...
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... UART • Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs • MIDI compatible • Fully programmable serial-interface characteristics: --- 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1 stop bits generation W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -2 - Revision 1.5 ...
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... Support both interrupt and polling modes • Fast Gate A20 and Hardware Keyboard Reset • 8 Bit Timer/ Counter • Support binary and BCD arithmetic • 6MHz, 8 MHz, 12 MHz MHz operating frequency W83977EF-AW /W83977EG- -2, Phoenix MultiKey/42 or customer code Publication Release Date: January, 2010 ...
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... General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog timer output, power LED output, infrared I/O pins, general purpose address decoder, KBC control I/O pins OnNow Funtions • Keyboard Wake-Up by programmable keys • Mouse Wake-Up by programmable buttons Package • 128-pin PQFP W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -4 - Revision 1.5 ...
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... DACK2# DACK2# 124 124 DRQ2 DRQ2 125 125 DACK3# DACK3# 126 126 DRQ3 DRQ3 127 127 TC TC 128 128 W83977EF-AW /W83977EG-AW W83977EF-AW W83977EF-AW W83977EG-AW W83977EG-AW Publication Release Date: January, 2010 - VBAT VBAT 63 63 XTAL1 XTAL1 62 62 VSS VSS 61 61 ...
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... IN ts IOCHRDY 108 118 IN ts W83977EF-AW /W83977EG-AW FUNCTION System address bus bits 0-10 System address bus bits 11-14 System address bus bit 15 System data bus bits 0-5 System data bus bits 6-7 CPU I/O read signal CPU I/O write signal System address bus enable In EPP Mode, this pin is the IO Channel Ready output to extend the host read/write cycle. Master Reset ...
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... OUT Interrupt request 6 12t IRQ7 94 OUT Interrupt request 7 12t IRQ9 92 OUT Interrupt request 9 12t IRQ10 100 OUT Interrupt request 10 12t IRQ11 101 OUT Interrupt request 11 12t IRQ12 102 OUT Interrupt request 12 12t W83977EF-AW /W83977EG-AW FUNCTION Publication Release Date: January, 2010 -7 - Revision 1.5 ...
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... KBC P16 I/O port. (CR2B bit 4_3 = 10) 12t PANSWOUT Panel Switch output. (CR2B bit default) 12t GP22 I/O General purpose I/O port 2 bit 2. (CR2B bit 12t (P14) Alternate Function from GP22: KBC P14 I/O port. W83977EF-AW /W83977EG-AW FUNCTION FUNCTION Publication Release Date: January, 2010 -8 - Revision 1.5 ...
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... CR26 bit 6 (HEFRAS). A 4.7 kΩ is recommended if intends to pull up. (select 370H as configuration I/O port′s address) 50 I/O UART B Request To Send. An active low signal informs the 8t RTSB# modem or data set that the controller is ready to send data. W83977EF-AW /W83977EG-AW FUNCTION FUNCTION Publication Release Date: January, 2010 -9 - Revision 1.5 ...
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... Ring Indicator. An active low signal indicates that a ring signal is t being received from the modem or data set. 66 RIB# 4.4 Infrared Interface SYMBOL PIN I/O IRRX 37 IN Infrared Receiver input. cs IRTX 38 OUT Infrared Transmitter Output. 12t W83977EF-AW /W83977EG-AW FUNCTION FUNCTION Publication Release Date: January, 2010 -10 - Revision 1.5 ...
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... EXTENSION FDD MODE: WD2# 12 This pin is for Extension FDD B; its function is the same as the WD# pin of FDC. EXTENSION 2FDD MODE: WD2 This pin is for Extension FDD A and B; its function is the same as the WD# pin of FDC. W83977EF-AW /W83977EG-AW FUNCTION Publication Release Date: January, 2010 -11 - Revision 1.5 ...
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... OD 12 This pin is for Extension FDD B; its function is the same as the HEAD#pin of FDC EXTENSION 2FDD MODE: HEAD2# This pin is for Extension FDD A and B; its function is the same as the HEAD# pin of FDC. W83977EF-AW /W83977EG-AW FUNCTION Publication Release Date: January, 2010 -12 - Revision 1.5 ...
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... This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC. EXTENSION 2FDD MODE: DRVDEN0 OD 12 This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC. W83977EF-AW /W83977EG-AW FUNCTION Publication Release Date: January, 2010 -13 - Revision 1.5 ...
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... WP# pin of FDC pulled high internally. EXTENSION. 2FDD MODE: WP2 This pin is for Extension FDD A and B; the function of this pin is the same as the WP# pin of FDC pulled high internally. W83977EF-AW /W83977EG-AW FUNCTION Publication Release Date: January, 2010 -14 - Revision 1.5 ...
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... I/O PD6 24t - OD 24 W83977EF-AW /W83977EG-AW FUNCTION PRINTER MODE: PD3 Parallel port data bus bit 3. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: RDATA2# This pin is for Extension FDD B; the function of this pin is the same as the RDATA# pin of FDC ...
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... Direction of the head step motor. An open drain output. 24 Logic 1 = outward motion Logic 0 = inward motion MOB Motor B On. When set to 0, this pin enables disk drive 1. This open drain output. W83977EF-AW /W83977EG-AW FUNCTION FUNCTION Publication Release Date: January, 2010 -16 - Revision 1.5 ...
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... This Schmitt-triggered input from the disk drive is active low cs when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). W83977EF-AW /W83977EG-AW FUNCTION Publication Release Date: January, 2010 -17 - Revision 1.5 ...
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... GND 25, 62, 90, Ground 120 4.9 ACPI Interface SYMBOL PIN I/O VBAT 64 NA battery voltage input XTAL1 63 IN 32.768Khz Clock Input C XTAL2 61 O 32.768Khz Clock Output 8t W83977EF-AW /W83977EG-AW FUNCTION FUNCTION FUNCTION Publication Release Date: January, 2010 -18 - Revision 1.5 ...
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... FDC FUNCTIONAL DESCRIPTION 5.1 W83977EF-AW/EG FDC The floppy disk controller of W83977EF-AW/EG integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports bits/sec data rate. ...
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... FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write perpendicular media. Some manufacturers offer drives that can read and write standard and perpendicular media in a perpendicular media drive. W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -20 - ...
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... FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk. 5.1.6 FDC Core The W83977EF-AW/EG FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor ...
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... Relative Cylinder Number R/W: Read/Write SC: Sector/per cylinder SK: Skip deleted data address mark SRT: Step Rate Time ST0: Status Register 0 ST1: Status Register 1 ST2: Status Register 2 ST3: Status Register 3 WG: Write gate alters timing of WE W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -22 - Revision 1.5 ...
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... EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83977EF-AW /W83977EG- Command codes 0 0 HDS DS1 DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after ...
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... W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83977EF-AW /W83977EG- Command codes 0 0 HDS DS1 DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution ...
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... EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83977EF-AW /W83977EG- Command codes 0 0 HDS DS1 DS0 Sector ID information prior to command execution Data transfer between the FDD reads cylinders from index hole to ...
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... ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- -------------------- DTL/SC ------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83977EF-AW /W83977EG- HDS DS1 DS0 HDS DS1 DS0 Publication Release Date: January, 2010 ...
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... ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83977EF-AW /W83977EG- HDS DS1 DS0 Publication Release Date: January, 2010 ...
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... N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83977EF-AW /W83977EG- HDS DS1 DS0 Publication Release Date: January, 2010 -28 - REMARKS Command codes Sector ID information prior to command execution Data transfer between the ...
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... N ------------------------ Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- (10) Recalibrate PHASE R Command Execution W83977EF-AW /W83977EG- HDS DS1 DS0 Command codes DS1 DS0 Head retracted to Track 0 ...
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... NCN ----------------------- Execution R (14) Configure PHASE R Command EIS EFIFO POLL | ------ FIFOTHR ----| W | --------------------PRETRK ----------------------- | Execution W83977EF-AW /W83977EG- Command code Status information at the end of each seek operation Command codes ...
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... EIS EFIFO POLL | ------ FIFOTHR -------- R -----------------------PRETRK ------------------------- (17) Perpendicular Mode PHASE R Command (18) Lock PHASE R Command W LOCK 0 0 Result W83977EF-AW /W83977EG- HDS DS1 DS0 ...
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... Sense Drive Status PHASE R Command Result R ---------------- ST3 ------------------------- (20) Invalid PHASE R Command W ------------- Invalid Codes ----------------- Result R -------------------- ST0 ---------------------- W83977EF-AW /W83977EG- HDS DS1 DS0 Publication Release Date: January, 2010 -32 - REMARKS ...
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... Register Descriptions There are several status, data, and control registers in W83977EF-AW. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 5.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, ...
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... This bit indicates the complement of latched STEP# output. TRAK0 (Bit 4): This bit indicates the complement of TRAK0# input. HEAD# (Bit 3): This bit indicates the value of HEAD# output. 0 side 1 1 side 0 INDEX (Bit 2): This bit indicates the complement of INDEX# output. W83977EF-AW /W83977EG- DIR# WP INDEX HEAD# ...
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... This bit indicates the complement of the WE# output pin. MOT EN B (Bit 1) This bit indicates the complement of the MOB# output pin. MOT EN A (Bit 0) This bit indicates the complement of the MOA# output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows: W83977EF-AW /W83977EG- ...
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... WE F/F (Bit 2): This bit indicates the complement of latched WE# output pin. DSD# (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected DSC# (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected W83977EF-AW /W83977EG- DSC# DSD# WE F/F RDATA F/F WD F/F ...
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... three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows W83977EF-AW /W83977EG-AW 1-0 2 Drive Select: 00 select drive A 01 select drive B 10 select drive C 11 select drive D Floppy Disk Controller Reset Active low resets FDC DMA and INT Enable Active high enable DRQ/IRQ Motor Enable A ...
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... The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by the DR REGISTER. The real data rate is determined by the most recent write to either of the DR REGISTER or CC REGISTER. W83977EF-AW /W83977EG-AW TAPE SEL 0 DRIVE SELECTED 0 ...
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... DATA RATE 250 KB/S 300 KB/S 500 KB/S 1 MB/S 2 MB/S W83977EF-AW /W83977EG- DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET PRECOMPENSATION DELAY 250K - 1 Mbps 2 Mbps Tape drive Default Delays Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208 ...
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... This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83977EF-AW/EG, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. ...
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... Status Register 3 (ST3 W83977EF-AW /W83977EG-AW Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted. NW (Not Writable write Protect signal is detected from the diskette drive during execution of write data. ND (No DATA specified sector cannot be found during execution of a read, write or verifly data. ...
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... These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings corresponding to the individual data rates. HIGHDENS#(Bit 0): 0 500 KB MB/S data rate (high density FDD) 1 250 KB/S or 300 KB/S data rate W83977EF-AW /W83977EG- ...
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... This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as follows Reserved Bit 7-2: Reserved. These bits should be set to 0. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. In the PS/2 Model 30 mode, the bit definitions are as follows: W83977EF-AW /W83977EG- DRATE0 DRATE1 ...
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... Reserved Bit 7-3: Reserved. These bits should be set to 0. NOPREC (Bit 2): This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. W83977EF-AW /W83977EG- DRATE0 ...
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... Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1, (1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check. (2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check. W83977EF-AW /W83977EG- ...
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... Baudrate BHL Bit 8 Divisor Latch BDLAB = 1 High *: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 Mode. W83977EF-AW /W83977EG-AW Bit Number Data RX Data RX Data RX Data ...
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... Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in each serial character. TABLE 6-2 WORD LENGTH DEFINITION DLS1 DLS0 DATA LENGTH W83977EF-AW /W83977EG-AW 5 bits 6 bits 7 bits 8 bits Publication Release Date: January, 2010 -47 - Revision 1.5 ...
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... Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0. 6.2.3 Handshake Control Register (HCR) (Read/Write) W83977EF-AW /W83977EG- ...
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... Bit 0: This bit controls the DTR# output. The value of this bit is inverted and output to DTR#. 6.2.4 Handshake Status Register (HSR) (Read/Write) This register reflects the current state of four input pins for handshake peripherals such as a modem and records changes on these pins W83977EF-AW /W83977EG- Data terminal ready (DTR) Request to send (RTS) ...
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... Bit 4, 5: Reserved Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if UFR bit W83977EF-AW /W83977EG- FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved ...
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... First UART Receive Status Second RBR Data Ready W83977EF-AW /W83977EG- interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled INTERRUPT SET AND FUNCTION Interrupt Source - No Interrupt pending 1 ...
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... MHz and the same divisor as the normal speed divisor. In high-speed mode, the data transmission rate can be as high as 1.5M bps. 6.2.9 User-defined Register (UDR) (Read/Write) This is a temporary register that can be accessed and defined by the user. W83977EF-AW /W83977EG-AW Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. ...
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... The percentage error for all baud rates, except where indicated otherwise, is 0.16%. Note. Pre-Divisor is determined by CRF0 of UART A and B. W83977EF-AW /W83977EG-AW Decimal divisor used to generate 16X 24M Hz clock 650 2304 975 1536 1430 1047 1478 ...
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... PARALLEL PORT 7.1 Printer Interface Logic The parallel port of W83977EF-AW/EG makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. W83977EF-AW/EG supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD) on the parallel port ...
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... Notes: 1. These registers are available in all modes. 2. These registers are available only in EPP mode. W83977EF-AW /W83977EG-AW PIN SPP PIN EXT2FDD ATTRIBUTE O nSTB --- --- I/O PD0 I INDEX2# I/O PD1 I TRAK02# I/O PD2 I WP2# I/O PD3 I RDATA2# ...
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... Bit 0: This bit is valid in EPP mode only. It indicates that a 10 μS time-out has occurred on the EPP bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect. W83977EF-AW /W83977EG- ...
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... Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be present for a minimum of 0.5 microseconds before and after the strobe pulse. 7.2.4 EPP Address Port The address port is available only in EPP mode. Bit definitions are as follows W83977EF-AW /W83977EG- ...
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... PD7 PD6 EPP Data Port 0 (R/W) PD7 PD6 EPP Data Port 1 (R/W) PD7 PD6 EPP Data Port 2 (R/W) PD7 PD6 EPP Data Port 3 (R/W) PD7 PD6 W83977EF-AW /W83977EG-AW c auses an EPP address write cycle to be performed, and the PD0 PD1 PD2 PD3 PD4 ...
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... EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high. W83977EF-AW /W83977EG-AW EPP DESCRIPTION WAIT# is deasserted. The current EPP cycle is ...
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... EPP mode (If this option is enabled in the CRF0 to select ECP/EPP mode) 101 Reserved 110 Test mode 111 Configuration mode Note: The mode selection bits are bit 7-5 of the Extended Control Register. W83977EF-AW /W83977EG-AW I/O ECP MODES R/W 000-001 Data Register R/W 011 ECP FIFO (Address) ...
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... The bit definitions are as follows 7.3.3 Device Status Register (DSR) These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows W83977EF-AW /W83977EG- PD0 PD1 ...
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... Bit 3: This bit is inverted and output to the SLIN# output. 0 The printer is not selected. 1 The printer is selected. INIT# Bit 2: This bit is output to the output. Bit 1: This bit is inverted and output to the Bit 0: This bit is inverted and output to the W83977EF-AW /W83977EG- strobe autofd nInit ...
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... The bit definitions are as follows Bit 7: This bit is read-only low level during a read. This means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts. W83977EF-AW /W83977EG- ...
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... Reserved. 110 Test Mode. The FIFO may be written and read in this mode, but the data will not be transmitted on the parallel port. 111 Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. W83977EF-AW /W83977EG- ...
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... ECP Data FIFO tFifo Test FIFO cnfgA 0 0 cnfgB compress intrValue ecr MODE Notes: 1. These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO. W83977EF-AW /W83977EG- PD5 PD4 PD3 PD2 PError Select nFault 1 Directio ackIntEn ...
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... I nInit (nReverseRequest) O nSelectIn (ECPMode) O W83977EF-AW /W83977EG-AW DESCRIPTION The nStrobe registers data or address into the slave on the asserting edge during write operations. This signal handshakes with Busy. These signals contains address or data or RLE data. This signal indicates valid data driven by the peripheral when asserted ...
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... Data Compression The W83977EF-AW supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo ...
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... I/O will empty or fill the FIFO using the appropriate direction and mode. 7.4 Extension FDD Mode (EXTFDD) In this mode, W83977EF-AW/EG changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 5-1 ...
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... CONTROLLER The KBC (8042 with licensed KB BIOS) circuit of W83977EF-AW/EG is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBM - ® compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer ...
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... Auxiliary Device Output Buffer 6 General Purpose Time- out 7 Parity Error W83977EF-AW /W83977EG-AW DESCRIPTION 0: Output buffer empty 1: Output buffer full 0: Input buffer empty 1: Input buffer full This bit may be set writing to the system flag bit in the command byte of the keyboard controller. It defaults to 0 after a power-on reset ...
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... BIT AAh Self-test Returns 055h if self test succeeds W83977EF-AW /W83977EG-AW FUNCTION BIT DEFINITION IBM Keyboard Translate Mode Enable Keyboard Interrupt BIT DEFINITION No Error Detected Auxiliary Device "Clock" line is stuck low Auxiliary Device "Clock" line is stuck high Auxiliary Device "Data" line is stuck low Auxiliary Device " ...
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... Pulse only RC(the reset line) low for 6 μ Command byte is even FXh 8.5 Hardware GATEA20/Keyboard Reset Control Logic The KBC implements a hardware control logic to speed-up GATEA20 and KBRESET. This control logic is controlled by LD5-CRF0 as follows: W83977EF-AW /W83977EG-AW FUNCTION BIT DEFINITION No Error Detected Keyboard "Clock" line is stuck low Keyboard " ...
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... A "1" on this bit drives GATE A20 signal to high. A "0" on this bit drives GATE A20 signal to low. PLKBRST (Pull-Low KBRESET) A "1" on this bit causes KBRESET to drive low for 6 μ S(Min.) with 14 μ S(Min.) delay. Before issuing another keyboard reset command, the bit must be cleared. W83977EF-AW /W83977EG- ...
Page 80
... Otherwise, the mouse can Wake-Up the system only by clicking its button twice successively with the mouse unmoved. The bit 4 of LD-0A CR-E0 determines which button (left or right) to perform Wake-Up function. W83977EF-AW /W83977EG-AW TM chipset TX, LX PIIX4) panel switch input. The Wake-Up ...
Page 81
... General Purpose I/O W83977EF-AW/EG provides 14 Input/Output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. Those 14 GP I/O ports are divided into three groups, the first group contains 8 ports, and the second group contains only 6 ports. Each port in first group corresponds to a configuration register in logical device 7, and the second group in logical device 8 ...
Page 82
... W83977EF-AW /W83977EG-AW Figure 9.2 Figure 9.3 Publication Release Date: January, 2010 -76 - Revision 1.5 ...
Page 83
... Basic I/O functions The Basic I/O functions of W83977EF-AW/EG provide several I/O operations including driving a logic value to output port, latching a logic value from input port, inverting the input/output logic value, and steering Common Interrupt (only available in the second group of the GP I/O port). Common Interrupt is the ORed function of all interrupt channels in the second group of the GP I/O ports, and it also connects to a 1ms debounce filter which can reject a noise pulse width or less ...
Page 84
... Table 7.1.2 GP I/O PORT ACCESSED REGISTER BIT REGISTER ASSIGNMENT GP1 GP2 W83977EF-AW /W83977EG-AW GP I/O PORT BIT 0 GP10 BIT 1 GP11 BIT 2 GP12 BIT 3 GP13 BIT 4 GP14 BIT 5 GP15 BIT 6 GP16 BIT 7 GP17 BIT 0 GP20 BIT 1 GP21 BIT 2 GP22 BIT 3 GP23 BIT 4 GP24 BIT 5 GP25 Publication Release Date: January, 2010 -78 - Revision 1 ...
Page 85
... Alternate I/O Functions W83977EF-AW/EG provides several alternate functions which are scattered among the GP I/O ports. Table 9.2.1 shows their assignments. Polarity bit can also be set to alter their polarity. Table 9.2.1 GP I/O PORT GP10 Interrupt Steering GP11 Interrupt Steering GP12 Watch Dog Timer Output/IRRX input GP13 Power LED output/IRTX output ...
Page 86
... CR62, CR63, CR64, and CR65 of logical device 7 for GP14 and GP15. The decoding range can be programmed to 1~8 byte boundary. The decoding output is normally active low. Users can alter its polarity through the polarity bit of the GP14 and GP15 configuration register. W83977EF-AW /W83977EG-AW WDT_CTRL1 BIT[0] X ...
Page 87
... Plug and Play Configuration W83977EF-AW/EG uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83977EF-AW/EG, there are nine Logical Devices (from Logical Device 0 to Logical Device A with the exception of logical device 4 and 6 for compatibility) which correspond to nine individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2), UART2 (logical device 3), KBC (logical device 5), GPIO1 (logical device 7), GPIO2 (logical device 8), and ACPI ((logical device A) ...
Page 88
... MR = 1). A warm reset will not affect the configuration registers. 10.1.2 Extended Functions Enable Registers (EFERs) After a power-on reset, W83977EF-AW/EG enters the default operating mode. Before W83977EF- AW/EG enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers ...
Page 89
... DX,3F1H MOV AL,01H OUT DX,AL ; select logical device 1 ; MOV DX,3F0H MOV AL,F0H OUT DX,AL ; select CRF0 MOV DX,3F1H MOV AL,3CH OUT DX,AL ; update CRF0 with value 3CH ;------------------------------------------ ; Exit extended function mode | ;------------------------------------------ MOV DX,3F0H MOV AL,AAH OUT DX,AL W83977EF-AW /W83977EG-AW | Publication Release Date: January, 2010 -83 - Revision 1.5 ...
Page 90
... ACPI Registers Features W83977EF-AW/EG supports both ACPI and legacy power managements. The switch logic of the power management block generates an SMI# interrupt in the legacy mode and an SCI# interrupt in the ACPI mode. The new ACPI feature routes SMI#/SCI# logic output either to SMI# or toSCI#. The SMI#/SCI# logic routes to SMI# only when both SCI_EN = 0 and SMISCI_OE = 1 ...
Page 91
... Bit 2, 1: Reserved. Bit 0: FDCPWD = 0 Power down = 1 No Power down CR23 (Default 0xFE) Bit Reserved. Bit 0: IPD (Immediate Power Down). When set will put the whole chip into power down mode immediately. W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -85 - Revision 1.5 ...
Page 92
... PnP registers if the present value of PNPCSV The corresponding power-on setting pin is NDTRA (pin 44). CR25 (Default 0x00) Bit Reserved Bit 5: URBTRI Bit 4: URATRI Bit 3: PRTTRI Bit Reserved Bit 0: FDCTRI. W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -86 - Revision 1.5 ...
Page 93
... Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ Bit 0: DSUBLGRQ = 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -87 - Revision 1.5 ...
Page 94
... KBRST = 1 GP12 Bit 6: PIN56S = 0 GA20 = 1 GP11 Bit PIN40S1, PIN40S0 = 00 Reserved = 01 GP24 = 10 8042 P13 = 11 Reserved Bit PIN39S1, PIN39S0 = 00 SUSCIN Reserved = 10 GP25 = 11 Reserved Bit PIN3S1, PIN3S0 = 00 DRVDEN1 = 01 GP10 = 10 8042 P12 = 11 SCI# W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -88 - Revision 1.5 ...
Page 95
... GP20 = 10 Reserved = 11 Reserved Bit 0: PIN58S = 0 KBLOCK = 1 GP13 CR2C (Default 0x00) Bit PIN121S1, PIN121S0 = 00 DRQ0 = 01 GP17 = 10 8042 P14 = 11 SCI# Bit PIN119S1, PIN119S0 = 00 NDACK0 = 01 GP16 = 10 8042 P15 = 11 Reserved Bit PIN104S1, PIN104S0 W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -89 - Revision 1.5 ...
Page 96
... Reserved Bit PIN103S1, PIN103S0 = 00 IRQ14 = 01 GP14 = 10 PLEDO = 11 Reserved CR2D (Default 0x00) Test Modes: Reserved for Winbond. CR2E (Default 0x00) Test Modes: Reserved for Winbond. CR2F (Default 0x00) Test Modes: Reserved for Winbond. W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -90 - Revision 1.5 ...
Page 97
... Bit 5: DRV2EN (PS2 mode only) When this bit is a logic 0, this indicates that a second drive is installed and is reflected in status register A. Bit 4: Swap Drive 0, 1 Mode = 0 No Swap (Default Drive and Motor sel 0 and 1 are swapped. W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -91 - Revision 1.5 ...
Page 98
... Forced to logic Forced to logic 0) Bit 1: DISFDDWR = 0 Enable FDD write Disable FDD write(forces pins WE, WD stay high). Bit 0: SWWP = 0 Normal, use WP to determine whether the FDD is write protected or not FDD is always write-protected. W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -92 - Revision 1.5 ...
Page 99
... Enable FDC Precompensation. Bit 5: Reserved. Bit DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A Select Regular drives and 2.88 format = 01 Specifical application = 10 2 Meg Tape = 11 Reserved Bit 2: Reserved. Bit 1:0: DMOD0, DMOD1 : Drive Model select (Refer to TABLE B). W83977EF-AW /W83977EG-AW DRATE0 SELDEN ...
Page 100
... Note:Refer to CRF2 for SELDEN value in the cases when CRF0, bit0=1. TABLE B DMOD0 DMOD1 DRVDEN0(pin SELDEN 0 1 DRATE1 1 0 SELDEN 1 1 DRATE0 W83977EF-AW /W83977EG-AW Selected Data Rate DRATE0 MFM FM 1 1Meg --- 0 500K 250K 1 300K 150K 0 250K 125K 1 1Meg --- 0 500K ...
Page 101
... Standard and Bi-direction (SPP) mode = 001 EPP - 1.9 and SPP mode = 101 EPP - 1.7 and SPP mode = 010 ECP mode = 011 ECP and EPP - 1.9 mode = 111 ECP and EPP - 1.7 mode. 12.4 Logical Device 2 (UART A)¢) W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -95 - Revision 1.5 ...
Page 102
... These two registers select Serial Port 2 I/O base address [0x100:0xFF8 byte boundary. CR70 (Default 0x03 if PNPCSV during POR, default 0x00 otherwise) Bit Reserved. Bit [3:0]: These bits select IRQ resource for Serial Port 2. W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -96 - Revision 1.5 ...
Page 103
... ASK-IR Inverting IRTX/SOUTB 111* ASK-IR Inverting IRTX/SOUTB & 500 KHZ clock Note: The notation is normal mode in the IR function. Bit 2: HDUPLX. IR half/full duplex function select. W83977EF-AW /W83977EG-AW IRTX high Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into SINB/IRRX ...
Page 104
... SOUTB pin of UART B function or IRTX pin of IR function. Bit 0: RX2INV the SINB pin of UART B function or IRRX pin of IR function in normal condition inverse the SINB pin of UART B function or IRRX pin of IR function W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -98 - Revision 1.5 ...
Page 105
... Select 12Mhz as KBC clock input Select 16Mhz as KBC clock input. Bit Reserved. Bit Port 92 disable Port 92 enable. Bit Gate20 software control Gate20 hardware speed up. Bit KBRST software control KBRST hardware speed up. W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -99 - Revision 1.5 ...
Page 106
... CRE0 (GP10, Default 0x01) Bit Reserved. Bit 4: IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 3: Select Function Select Alternate Function: Interrupt Steering Select Basic I/O Function. Bit 2: Reserved. Bit 1: Polarity Invert Invert. W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -100 - Revision 1.5 ...
Page 107
... Bit 4: IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 3: Select Function Select Alternate Function: Interrupt Steering Select Basic I/O Function. Bit 2: Reserved. Bit 1: Polarity Invert Invert. Bit 0: In/Out selection Input Output. W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -101 - Revision 1.5 ...
Page 108
... Select 1st alternate function: General Purpose Address Decoder(Active Low when Bit Decode two byte address Select 2nd alternate function: Keyboard Inhibit(P17 Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: 1: Input, 0: Output CRE5 (GP15, Default 0x01) Bit W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -102 - Revision 1.5 ...
Page 109
... Select 1st alternate function: Power LED output. Please refer to TABLE Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: 1: Input, 0: Output TABLE C WDT_CTRL1* BIT[1]* WDT_CTRL0* BIT[3] W83977EF-AW /W83977EG-AW WDT_CTRL1 BIT[0] POWER LED STATE Publication Release Date: January, 2010 -103 - Revision 1.5 ...
Page 110
... Bit These bits select IRQ resource for Common IRQ of GP20~GP26 at Logic Device 8. CR72 (Default 0x00) Bit Reserved. Bit These bits select IRQ resource for Watch Dog. CRE8 (GP20, Default 0x01) Bit Reserved. Bit Select Function. W83977EF-AW /W83977EG- ...
Page 111
... Disable Common IRQ Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: 1: Input, 0: Output CREB (GP23, Default 0x01) Bit Reserved. Bit Select Function Select Basic I/O function = 01 Reserved = 10 Select 2nd alternate function: Keyboard P15 I Reserved W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -105 - Revision 1.5 ...
Page 112
... Debounce Filter Enable or Disable for General Purpose I/O Combined Interrupt. The Debounce Filter can reject a pulse with 1ms width or less. Bit Reserved Bit 3: GP Common IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit Reserved CRF1 (Reserved) W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -106 - Revision 1.5 ...
Page 113
... Time-out occurs after 255 minutes CRF3 (WDT_CTRL0, Default 0x00) Watch Dog Timer Control Register #0 Bit Reserved Bit 3: When Time-out occurs, Enable or Disable Power LED with 1 Hz and 50% duty cycle output Enable = 0 Disable W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -107 - Revision 1.5 ...
Page 114
... Internal logic provides an 1us Debounce Filter to reject the width of P20 pulse less than 1us. 2). The P20 signal that coming from Debounce Filter is ORed with the signal generated by the Force Time-out bit and then connect to set the Bit 0(Watch Dog Timer Status). The ORed signal is self-clearing. W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -108 - Revision 1.5 ...
Page 115
... Any character received from Keyboard can Wake-Up the system. CRE1 (Default 0x00) Keyboard Wake-Up Index Register This register is used to indicate which Keyboard Wake-Up Shift register or Predetermined key Register read/written via CRE2. The range of Keyboard Wake-Up index register is 0x00 - 0x0E, W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -109 - Revision 1.5 ...
Page 116
... CRE5 (Default 0x00) Bit 7: Reserved. Bit Compared Code Length. When the compared codes are storaged in the data register, these data length should be written to this register. CRE6 (Default 0x00) Bit Reserved. W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -110 - Revision 1.5 ...
Page 117
... Bit 0: URBPME. UART B auto power management enable disable the auto power management functions enable the auto power management functions. W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -111 - Revision 1.5 ...
Page 118
... UART A is now in the working state due to any UART A access, any IRQ, the receiver begins receiving a start bit, the transmitter shift register begins transmitting a W83977EF-AW /W83977EG-AW start bit, and any transition on MODEM control input lines. start bit, and any transition on MODEM control input lines. ...
Page 119
... MOUIRQSTS) or (URCIRQEN and URCIRQSTS) or (WDTIRQEN and WDTIRQSTS) or (COMIRQEN and COMIRQSTS) or (GP11IRQEN and GP11IRQSTS) or (GP10IRQEN and GP10IRQSTS) Bit 6: URCIRQEN disable the generation of an SMI#/SCI# interrupt due to UART C's IRQ. W83977EF-AW /W83977EG-AW start bit, and any transition on MODEM control input lines. Publication Release Date: January, 2010 -113 - Revision 1.5 ...
Page 120
... SMI#/SCI# interrupt due to common IRQ function's IRQ. Bit 1: GP11IRQEN disable the generation of an SMI#/SCI# interrupt due to GP11 interrupt steering's IRQ enable the generation of an SMI#/SCI# interrupt due to GP11 interrupt steering's IRQ. W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -114 - Revision 1.5 ...
Page 121
... Bit 0: SMISCI_OE: This is the SMI# and SCI# enable bit neither SMI# nor SCI# will be generated. Only the IRQ status bit is set SMI# or SCI# event will be generated. CRFE, FF (Default 0x00) Reserved for Nuvotontest. W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -115 - Revision 1.5 ...
Page 122
... TTL level bi-directional pin with source-sink capability Input Low Voltage V IL Input High Voltage V IH Output Low Voltage V OL Output High Voltage V OH Input High Leakage I LIH Input Low Leakage I LIL W83977EF-AW /W83977EG-AW RATING -0.5 to 7.0 -0 +0.5 DD 4.0 to 1.8 4 +70 -55 to +150 = 0V) SS MIN. TYP. MAX. UNIT ≤ 2.0 mA ...
Page 123
... Input Low Voltage V IL Input High Voltage V 0.7xV IH Output Low Voltage V OL Output High Voltage V OH Input High Leakage I LIH Input Low Leakage I LIL W83977EF-AW /W83977EG-AW MIN. TYP. MAX. UNIT 0.3xV 0 μ μ A 0.3xV V DD ...
Page 124
... Open-drain output pin with sink capability Output Low Voltage TTL level input pin t Input Low Voltage V IL Input High Voltage V IH Input High Leakage I LIH Input Low Leakage I LIL W83977EF-AW /W83977EG-AW MIN. TYP. MAX. UNIT 0.8 V 2.0 V 0 μ μ A 0 ...
Page 125
... Input High Leakage Input Low Leakage IN - TTL level Schmitt-triggered input pin with internal pull-up resistor tsu Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage W83977EF-AW /W83977EG-AW MIN. TYP. MAX. V 0.3 × 0.7 × ...
Page 126
... DRQ cycle time T MCY DRQ delay time DACK# ↓ DRQ to DACK# delay T MA DACK# width IOR# delay from DRQ MR T IOW# delay from DRQ MW W83977EF-AW /W83977EG-AW TEST MIN. TYP. (NOTE 1) CONDITIONS 100 100 100 ...
Page 127
... STD STEP# pulse width T STP STEP# cycle width T SC WD# pulse width T WDD Write precompensation T WPC Notes: 1. Typical values for ° C and normal supply voltage. 2. Programmable from 2 mS through increments. W83977EF-AW /W83977EG-AW TEST MIN. TYP. CONDITIONS (NOTE 1) 6/12 /20/24 135/220 /260 1.8/3/3. 5 0.5/0.9 /1.0 1.0/1.6 /2.0 ...
Page 128
... Baud Divisor 13.3.3 Parallel Port Mode Parameters PARAMETER PD0-7, INDEX#, STROBE#, AUTOFD# Delay from IOW# IRQ Delay from ACK#, nFAULT IRQ Delay from IOW# IRQ Active Low in ECP and EPP Modes ERROR# Active to IRQ Active W83977EF-AW /W83977EG-AW SYMBOL TEST MIN. CONDITIONS T 9/16 SINT T ...
Page 129
... Command Asserted to PD Valid Command Deasserted to PD Hi-Z WAIT# Deasserted to PD Drive WRITE# Deasserted to Command PBDIR Set to Command PD Hi-Z to Command Asserted Asserted to Command Asserted WAIT# Deasserted to Command Deasserted Time out PD Valid to WAIT# Deasserted PD Hi-Z to WAIT# Deasserted W83977EF-AW /W83977EG-AW SYM. MIN ...
Page 130
... WAIT# Asserted to PD Invalid PD Invalid to Command Asserted IOW# to Command Asserted WAIT# Asserted to Command Asserted WAIT# Deasserted to Command Deasserted Command Asserted to WAIT# Deasserted Time out Command Deasserted to WAIT# Asserted IOW# Deasserted to WRITE# Deasserted and PD invalid W83977EF-AW /W83977EG-AW SYM. MIN ...
Page 131
... BUSY Asserted to nSTROBE Deasserted 13.3.8 ECP Parallel Port Reverse Timing Parameters PARAMETER PD Valid to nACK Asserted nAUTOFD Deasserted to PD Changed nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted nACK Deasserted to nAUTOFD Asserted PD Changed to nAUTOFD Deasserted W83977EF-AW /W83977EG-AW SYMBOL MIN. MAX. t1 600 t2 600 t3 450 ...
Page 132
... Time from inactive CLK transition, used to time when the auxiliary device sample DATA T25 Time of inhibit mode T26 Time from rising edge of CLK to DATA transition T27 Duration of CLK inactive T28 Duration of CLK active T29 Time from DATA transition to falling edge of CLK W83977EF-AW /W83977EG-AW MIN ...
Page 133
... PANSWIN# falling edge to PANSWOUT# falling edge SWL t PANSWIN# falling edge to PANSWOUT# Hi-Z SWH t KCLK/MCLK falling edge to PANSWOUT# falling WKUPD edge delay t PANSWOUT# active pulse width WKUPW W83977EF-AW /W83977EG-AW MIN. 300(Note 1) MIN. 0.5 Publication Release Date: January, 2010 -127 - MAX. UNIT ns MAX. UNIT 20 ns ...
Page 134
... TIMING WAVEFORMS 14.1 FDC W83977EF-AW /W83977EG-AW Publication Release Date: January, 2010 -128 - Revision 1.5 ...
Page 135
... IRQ3 or IRQ4 IOR (READ RECEIVER BUFFER REGISTER) SERIAL OUT STAR (SOUT) THRS IRQ3 or IRQ4 THR IOW TSI (WRITE THR) IOR (READ TIR) W83977EF-AW /W83977EG-AW Receiver Timing DATA BITS (5-8) PARITY STOP TSINT Transmitter Timing DATA (5-8) PARITY STOP (1-2) THR Publication Release Date: January, 2010 ...
Page 136
... IRQ4 │ IOR# (READ MSR) RI# │ │ │ ACK# │ → ← │ │ │ │ │ IRQ7 │ │ W83977EF-AW /W83977EG-AW │ │ │ → → ← TMWO │ │ │ │ │ ? │ │ → │ ← TSIM │ ...
Page 137
... Parallel Port 14.3.1 Parallel Port Timing IOW# INIT#, STROBE# AUTOFD, SLCTIN# PD<0:7> ACK# IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR# (ECP) IRQ W83977EF-AW /W83977EG- Publication Release Date: January, 2010 -131 - t4 Revision 1.5 ...
Page 138
... EPP Data or Address Read Cycle (EPP Version 1.9) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE# t16 t17 PD<0:7> t21 t22 t23 t24 ADDRSTB DATASTB WAIT# W83977EF-AW /W83977EG- t18 t19 t25 t27 t26 Publication Release Date: January, 2010 -132 - t15 t20 t28 Revision 1.5 ...
Page 139
... EPP Data or Address Write Cycle (EPP Version 1.9) A10-A0 SD<0:7> t1 IOW# IOCHRDY t9 t10 t11 WRITE# t13 PD<0:7> DATAST# ADDRSTB# WAIT# t22 PBDIR W83977EF-AW /W83977EG- t15 t16 t17 t18 t19 t20 Publication Release Date: January, 2010 -133 - t6 t12 t14 t21 Revision 1.5 ...
Page 140
... EPP Data or Address Read Cycle (EPP Version 1.7) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE# t16 t17 PD<0:7> t21 t22 t23 ADDRSTB t24 DATASTB WAIT# W83977EF-AW /W83977EG- t18 t19 t25 t26 t27 Publication Release Date: January, 2010 -134 - t15 t20 t28 Revision 1.5 ...
Page 141
... EPP Data or Address Write Cycle (EPP Version 1.7) A10-A0 SD<0:7> t1 IOW# IOCHRDY t9 t10 t11 WRITE# PD<0:7> DATAST# ADDRSTB# WAIT# 14.3.6 Parallel Port FIFO Timing PD<0:7> nSTROBE BUSY W83977EF-AW /W83977EG- t13 t15 t16 t17 t18 t19 t20 >| > t6 >| Publication Release Date: January, 2010 ...
Page 142
... ECP Parallel Port Forward Timing nAUTOFD PD<0:7> nSTROBE BUSY 14.3.8 ECP Parallel Port Reverse Timing PD<0:7> nACK t5 nAUTOFD W83977EF-AW /W83977EG- Publication Release Date: January, 2010 -136 - Revision 1.5 ...
Page 143
... A2, CSB WRB D0~D7 GA20 OUTPUT PORT FAST RESET PULSE RC FE COMMAND 14.4.2 Read Cycle Timing A2,CSB AEN# RDB D0-D7 14.4.3 Send Data to K/B CLOCK (KCLK) T12 SERIAL DATA START D0 (KDAT) W83977EF-AW /W83977EG- ACTIVE T8 T7 DATA IN T9 T17 ACTIVE T10 T11 DATA OUT T14 T13 D1 ...
Page 144
... START D0 (T1) T20 14.4.5 Input Clock CLOCK CLOCK T21 14.4.6 Send Data to Mouse MCLK T25 T22 MDAT START D0 Bit 14.4.7 Receive Data from Mouse MCLK T29 T26 MDAT START D0 W83977EF-AW /W83977EG-AW T14 T13 T23 T24 T27 T28 D5 D1 ...
Page 145
... GPIO Write Timing Diagram A0-A15 IOW# D0-7 GPIO10-17 PREVIOUS STATE GPIO20-25 14.6 Master Reset (MR) Timing Vcc MR 14.7 Keyboard/Mouse Wake-up Timing KCLK MCLK PANSWIN# PANSWOUT# HI-Z tSWL W83977EF-AW /W83977EG-AW VALID VALID tWGO tVMR tWKUPW tWKUPD tSWZ Publication Release Date: January, 2010 -139 - VALID Revision 1.5 ...
Page 146
... SA9 – SA0, AEN#, DACK#, CS#, setup time to IOR# ↓ SA9 – SA0, AEN#, DACK#, hold time for IOR# ↑ width IOR Data access time from IOR# ↓ Data hold from IOR# ↓ IRQ delay from IOR# ↑ W83977EF-AW /W83977EG-AW TRR TFD SYM. TEST MIN. CONDITIONS T 25 ...
Page 147
... SA9 – SA0, AEN#, DACK#, setup time to IOW# ↓ SA9 – SA0, AEN#, DACK#, hold time for IOW# ↑ width IOW Data setup time to IOW# ↑ Data hold time from IOW# ↑ IRQ delay from IOW# ↑ W83977EF-AW /W83977EG-AW TWW TWD TDW SYM. TEST MIN. CONDITIONS T ...
Page 148
... WP2#/PD2 16 DIR2#/INIT# 3 TRK02#/PD1 15 HEAD2#/ERR# 2 IDX2#/PD0 14 RWC2#/AFD# 1 STB# PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram W83977EF-AW /W83977EG-AW DCH2# HEAD2# RDD2# WP2# TRK02# WE2# WD2# STEP2# DIR2# MOB2# DSB2# IDX2# RWC2# Publication Release Date: January, 2010 ...
Page 149
... DIR2#/IN IT K02#/ EAD 2#/ X2#/ 2#/AFD # 1 STB TER Parallel Port Extension 2FD D Connection D iagram W83977EF-AW /W83977EG- K02# W E2# W D2# ST EP2# DIR2 # A2 X2# ...
Page 150
... W83977EF-AW © AM. MEGA. 87-96 821A2B282012345 1st line: Nuvotonlogo 2nd line: the type number: W83977EF-AW-AW,W83977EG-AW-AW(Pb-free package) 3rd line: the source of KBC F/W -- American Megatrends Incorporated 4th line: the tracking code 821 282012345 821: packages made in '98, week 21 A: assembly house ID; A means ASE, S means SPIL.... etc. ...
Page 151
... PACKAGE DIMENSIONS (128-pin PQFP 102 65 64 103 128 See Detail Seating Plane W83977EF-AW /W83977EG-AW Symbol Min 0.10 c 0.10 D 13.90 E 19. 17.00 H 23. 0. Note: 1.Dimension D & not include interlead flash. ...
Page 152
... W83977EF-AW /W83977EG-AW PAGE DESCRIPTION n.a. Remove W83977CTF Part Update the new version on web P86~P110 Add Chapter 10 Configuration Register n.a Add Pb-free part no:W83977EG- Remove CIRRX from pin 40. 2. Update the description of CR2Ah, bit 5-4 in 12.1 Chip (Global) Control Register. ...
Page 153
... Nuvoton customers using or selling these products for use in such applications their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. W83977EF-AW /W83977EG-AW Important Notice Publication Release Date: January, 2010 -147 - ...