UPD72001L-11 Renesas Electronics Corporation., UPD72001L-11 Datasheet
UPD72001L-11
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UPD72001L-11 Summary of contents
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MULTI-PROTOCOL SERIAL CONTROLLERS DESCRIPTION The PD72001- MPSC (Multi-Protocol Serial Controller) which is a general-purpose communication LSI equipped with two sets of bidirectional parallel/serial converter circuits for data communication. This controller has a transmitter function to convert the parallel ...
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ORDERING INFORMATION Part Number PD72001C-11 PD72001G-11-22 PD72001GC-11-3B6 PD72001L-11 PD72001C-A8 PD72001G-A8-22 PD72001GC-A8-3B6 2 Package 40-pin plastic DIP (600 mil) 44-pin plastic QFP (10 10 mm) (resin thickness: 1.45 mm) 52-pin plastic QFP (14 14 mm) (resin thickness: 2.7 mm) 52-pin plastic ...
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SPECIFICATIONS Item Part number Supply voltage System clock frequency 11 MHz MAX. Maximum transfer rate 2.2 Mbps Process CMOS Internal circuit Parallel/serial converter circuit: Full-duplex channel Transmit buffer : Double Receive buffer : Quadruple Interrupt control ...
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PIN CONFIGURATION (Top View) • 40-pin plastic DIP (600 mil) : PD72001C-11, PD72001C-A8 DCDA GND WR RD C/D B/A PRO PRI INTAK INT CTSB DCDB • 44-pin plastic QFP (10 10 mm) ...
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QFP ( XI2A/SYNCA 3 XI1A/STR CTSA DCDA ...
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System CLK CLK/Stby CLK Cont. DB D7-0 Buf 0-5 WR 10-15 RD/WR C/D Cont. B/A RESET DRQR A X DMA DRQT A X DTRB/DRQR B Cont. X DTRA/DRQT B X INT INT INTAK PRI Cont. PRO Interface Cont. ...
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PIN FUNCTIONS The functions of the MPSC can be broadly classified into “system interface functions” that control interfacing with the host system, and “transmission/reception functions” to transmit or receive data. This section explains the functions of the pins of ...
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Pin Name I B I/O INT O INTAK I PRI I PRO O DRQT DRQR DTRA/DRQT DTRB/DRQR DA, ...
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Table 1-2 shows the selection operations by WR, RD, B/A, and C/D. Table 1-2. MPSC Control Signals and Operations WR RD B/A C Channel A H Channel Channel A H Channel ...
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Non-vector mode (CR2A “0”) In this mode, the PRI pin controls only the generation of interrupts because the INTAK sequence is not used interrupt vector output mode other than Type A-3 and Type B-2 is ...
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When CR2A: D1 “0, 0” or “0, 1” This pin functions as the DTRB output pin. The function of this pin is the same as the DTRA pin, except this pin is used with channel B. (b) ...
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Table 1-5. Auto Enable Bit and RTS Pin Function Auto Enable Bit Protocol Start-stop 0 synchronization 1 COP/BOP Don’t Care Note SR1: D2 1.2 Pins Related to Transmission/Reception ( (Transmit Data A) and T DB (Transmit Data B) ...
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Table 1-6. Functions of SYNC Pins and Setting of CR4 (when CR15 “0”) Operation Synchronization SYNC Pin Protocol Detection Mode Function D7 Start-stop Input synchro- nization COP Internal Output synchro- nization External Input 0 synchro- nization 0 BOP ...
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RS-232-C D/R Personal computer Terminal adapter for ISDN PD72001-11 PD98201 HDLC Dch SYNC ASYNC S-I/F Trans- former HDLC Bch SYNC ASYNC Bus PD72002-11 HDLC CPU ROM SYNC (with DMAC) ASYNC ISDN circuit RAM ...
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ELECTRICAL SPECIFICATIONS (1) PD72001-11 Absolute Maximum Ratings ( Parameter Symbol Supply voltage V DD Input voltage V I Output voltage V O Operating temperature T A Storage temperature T stg Caution If any of the ...
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Capacitance ( Parameter Symbol Input capacitance I/O capacitance AC Characteristics PD72001- – System interface: Parameter Symbol Clock cycle Clock high-pulse width Clock low-pulse ...
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Serial control: Parameter Symbol Transmit/receive data cycle STR input clock cycle X X STR input High clock pulse width Low STR delay time ...
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Modem control: Parameter Symbol CTS, DCD, SYNC pulse High t width Low CTS, DCD, SYNC INT delay time t STR SYNC setup time Communication control: Parameter Symbol Transmit enable command t DTETD1 (WR , ...
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AC Test Input/Output Waveform (except clock) 2.4 0.45 AC Test Clock Input Waveform Load Condition Caution If the load capacitance exceeds 100 pF due to the configuration of the circuit, keep the load capacitance of this device to within 100 ...
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PD72001-A8 Absolute Maximum Ratings ( Parameter Symbol Supply voltage V DD Input voltage V I Output voltage V O Operating temperature T A Storage temperature T stg Caution If any of the parameters exceeds the ...
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AC Characteristics (T = – System interface: Parameter Symbol Clock cycle Clock high-pulse width t Clock low-pulse width Clock rise time Clock fall time Address setup time (vs Address hold time (vs. RD ...
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Serial control: Parameter Symbol Transmit/receive data cycle STR input clock cycle X X STR input X X clock pulse width STR delay time DTCTD1 t DTCTD2 TR C ...
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Interrupt control: Parameter Symbol INTAK low-pulse width t INTAK high-pulse width t PRI PRO delay time t INT PRO delay time t 2nd INTAK INT delay time t SR2B read RD INT delay time t PRI setup time (vs. INTAK ...
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Communication control: Parameter Symbol Transmit enable command ( DTETD1 CTS ) T D delay time X t DTETD2 Receive enable command (DCD ) t SRERC setup time (vs. start bit, STR Note ...
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AC Test Input Waveform (except clock) 2.2 0.5 AC Test Clock Input Waveform Load Condition Caution If the load capacitance exceeds 100 pF due to the configuration of the circuit, keep the load capacitance of this device to within 100 ...
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Clock Timing CLK Read Cycle Timing C/D, B/A RD D7-0 Write Cycle Timing C/D, B/A WR D7-0 Read/Write Cycle Timing (except transfer of transmit/receive data) RD CYK t t WKH WKL SAR ...
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Transmit Cycle Timing STR CA CA DTCTD3 T DA/B X INT DRQT A/B X Receive Cycle Timing STR CA CA DA/B X INT DRQR A/B X PD72001-11, 72001-A8 t CYC t WCL ...
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Transmitter Enable Timing CTS Receiver Enable Timing STR DCD Note LSB of the first receive data (SYNC, flag) Receive Clock Setting Timing a. In ASYNC mode STR C ...
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DCD Timing, Receive Clock Hold Timing a. In ASYNC mode STR DCD b. COP/BOP mode STR Note X DCD Note This bit is the MSB ...
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DMA Cycle Timing DRQT A/B X DRQR A PRO Output Timing PRI INT t DPIPO PRO INTAK Cycle Timing PRI (when vector output is disabled) PRI (when vector output is enabled) INTAK t WIAL RD Hi-Z D7-0 ...
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E/S Timing CTSA/B, DCDA/B, SYNCA/B INT SYNC Input Timing (external synchronization mode) STR CA CA/B X Last Bit of SYNC Character Note SYNCA/B Note SYNCA/B input must be cleared to “0” at the rising edge of R character. ...
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PACKAGE 40PIN PLASTIC DIP (600 mil NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) ltem "K" to ...
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PIN PLASTIC QFP ( 10 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. PD72001-11, 72001-A8 23 ...
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PIN PLASTIC QFP ( 14 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition detail of lead ...
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PIN PLASTIC QFJ ( 750 mil NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. PD72001-11, 72001- ...
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RECOMMENDED SOLDERING CONDITIONS It is recommended to solder this product under the following conditions. For details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those ...
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PD72001GC-11-3B6 : 52-pin plastic QFP (14 PD72001GC-A8-3B6: 52-pin plastic QFP (14 Soldering Method Infrared reflow Package peak temperature: 235 C, Time: 30 seconds MAX. (210 C MIN.), Number of times: 3 MAX. VPS Package peak temperature: 215 C, Time: ...
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PD72001-11, 72001-A8 ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a ...