TE28F320C3TC90 Intel Corporation, TE28F320C3TC90 Datasheet
TE28F320C3TC90
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Intel Advanced+ Boot Block Flash Memory (C3) 28F800C3, 28F160C3, 28F320C3, 28F640C3 (x16) Product Features Flexible SmartVoltage Technology — 2.7 V– 3.6 V Read/Program/Erase — for Fast Production Programming 1.65 V–2 2.7 V–3.6 V I/O Option ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2003 *Third-party brands and names are the property of their respective owners. 2 ...
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Contents 1.0 Introduction....................................................................................................................................7 1.1 Document Purpose ...............................................................................................................7 1.2 Nomenclature .......................................................................................................................7 1.3 Conventions..........................................................................................................................7 2.0 Device Description ........................................................................................................................8 2.1 Product Overview .................................................................................................................8 2.2 Ballout Diagram ....................................................................................................................8 2.3 Signal Descriptions .............................................................................................................13 2.4 Block Diagram ....................................................................................................................14 2.5 Memory Map .......................................................................................................................15 3.0 Device Operations .......................................................................................................................17 ...
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Contents 5.6.1 Program Protection................................................................................................ 31 6.0 Power Consumption.................................................................................................................... 32 6.1 Active Power (Program/Erase/Read).................................................................................. 32 6.2 Automatic Power Savings (APS) ........................................................................................ 32 6.3 Standby Power ................................................................................................................... 32 6.4 Deep Power-Down Mode.................................................................................................... 32 6.5 Power and Reset Considerations ....................................................................................... 33 6.5.1 Power-Up/Down ...
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Revision History Date of Version Revision 05/12/98 -001 07/21/98 -002 10/03/98 -003 12/04/98 -004 12/31/98 -005 02/24/99 -006 06/10/99 -007 03/20/00 -008 04/24/00 -009 10/12/00 -010 7/20/01 -011 10/02/01 -012 2/05/02 -013 Datasheet Description Original version 48-Lead TSOP package diagram ...
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Contents Date of Version Revision 4/05/02 -014 3/06/03 -016 10/03 -017 6 Description Updated 64Mb product offerings. Updated 16Mb product offerings. Revised and corrected DC Characteristics Table. Added mechanicals for Easy BGA. Minor text edits throughout document. Complete technical update. ...
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Introduction 1.1 Document Purpose This datasheet contains the specifications for the Intel (C3) device family. These flash memories add features such as instant block locking and protection registers that can be used to enhance the security of systems. 1.2 ...
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Intel Advanced+ Boot Block Flash Memory (C3) 2.0 Device Description This section provides an overview of the Intel features, packaging, signal naming, and device architecture. 2.1 Product Overview The C3 device provides high-performance asynchronous reads in package-compatible densities with ...
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Figure 1. 48-Lead TSOP Package WE ...
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... Intel stringent quality requirements. Products affected are Intel Ordering Codes shown in Table 1. Table 1. 48-Lead TSOP Extended 64 Mbit TE28F640C3TC80 TE28F320C3TD70 TE28F640C3BC80 TE28F320C3BD70 TE28F320C3TC70 TE28F320C3BC70 TE28F320C3TC90 TE28F320C3BC90 TE28F320C3TA100 TE28F320C3BA100 TE28F320C3TA110 TE28F320C3BA110 10 £ Advanced and Advanced + Boot Block Extended 32 Mbit Extended 16 Mbit TE28F160C3TD70 TE28F160C3BD70 ...
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Figure 3. 48-Ball µBGA* and 48-Ball Very Fine Pitch BGA (VF BGA) Chip Size Package (Top View, Ball Down A13 A11 B A14 A10 C A15 A12 D A16 D14 E V D15 CCQ F GND D7 ...
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Intel Advanced+ Boot Block Flash Memory (C3) Figure 4. 64-Ball Easy BGA Package ( RP ...
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Signal Descriptions Table 2 lists the active signals used and provides a brief description of each. Table 2. Signal Descriptions Symbol Type ADDRESS INPUTS for memory addresses. Address are internally latched during a program or erase cycle. 8 Mbit: ...
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Intel Advanced+ Boot Block Flash Memory (C3) 2.4 Block Diagram V CCQ A[MAX:MIN] Input Buffer Address Latch Address Counter Output Buffer Identifier Register Status Register Power Data Reduction Comparator Control Y-Decoder Y-Gating/Sensing X-Decoder Input ...
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Memory Map The C3 device is asymmetrically blocked, which enables system code and data integration within a single flash device. The bulk of the array is divided into 32 Kword main blocks that can store code or data, and ...
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Intel Advanced+ Boot Block Flash Memory (C3) Table 4. Bottom Boot Memory Map 8-Mbit Size Memory Size Blk Blk (KW) Addressing (KW) (HEX 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 32 ...
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Device Operations The C3 device uses a CUI and automated algorithms to simplify Program and Erase operations. The CUI allows for 100% CMOS - level control inputs and fixed power supplies during erasure and programming. The internal WSM completely ...
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Intel Advanced+ Boot Block Flash Memory (C3) 3.1.4 Standby Deselecting the device by bringing CE logic - high level (V mode, which substantially reduces device power consumption without any latency for subsequent read accesses. In standby, outputs ...
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Modes of Operation 4.1 Read Mode The flash memory has four read modes (read array, read identifier, read status, and CFI query), and two write modes (program and erase). Three additional modes (erase suspend to program, erase suspend to ...
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Intel Advanced+ Boot Block Flash Memory (C3) Table 6. Device Identification Codes Item Manufacturer ID Device ID 2 Block Lock Status Block Lock-Down Status Protection Register Lock Status Protection Register NOTES: 1. The address is constructed from a base ...
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The contents of the status register are latched on the falling edge of OE# or CE# (whichever occurs last) which prevents possible bus errors that might occur if Status Register contents change while being read. CE# or OE# must be ...
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Intel Advanced+ Boot Block Flash Memory (C3) The mode enhances programming performance during the short period of time typically PP found in manufacturing processes; however not intended for extended use may be ...
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Suspending and Resuming Erase Since an Erase operation requires on the order of seconds to complete, an Erase Suspend command is provided to allow erase - sequence interruption in order to read data from—or program data to— another block ...
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Intel Advanced+ Boot Block Flash Memory (C3) Table 7. Command Bus Operations Command Read Array Read Identifier CFI Query Read Status Register Clear Status Register Program Block Erase/Confirm Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block Lock-Down Block Protection ...
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Table 8. Command Codes and Descriptions Code Device Mode (HEX) This command places the device in read-array mode, which outputs array data on the data FF Read Array pins. This is a two - cycle command. The first cycle prepares ...
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Intel Advanced+ Boot Block Flash Memory (C3) Table 8. Command Codes and Descriptions Code Device Mode (HEX) 10 Alt. Prog Set-Up Operates the same as Program Set - up command. (See 0x40/Program Set-Up) Invalid/ Unassigned commands should not be ...
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Security Modes 5.1 Flexible Block Locking The C3 device offers an instant, individual block-locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. This locking scheme offers two levels ...
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Intel Advanced+ Boot Block Flash Memory (C3) 5.1.1 Locking Operation The locking status of each block can be set to Locked, Unlocked, or Lock-Down, each of which will be described in the following sections. See page 27 and Figure ...
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Locking Operations during Erase Suspend Changes to block-lock status can be performed during an erase-suspend by using the standard locking command sequences to Unlock, Lock, or Lock Down a block. This is useful in the case when another block ...
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Intel Advanced+ Boot Block Flash Memory (C3) 5.5.1 Reading the Protection Register The protection register is read in the read-identifier mode. The device is switched to this mode by issuing the Read Identifier command (0x90). Once in this mode, ...
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Program Protection In addition to the flexible block locking, the V hardware write protection of all blocks in the flash device. When V any Program or Erase operation will result in an error, prompting the corresponding status-register bit (SR[3]) ...
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Intel Advanced+ Boot Block Flash Memory (C3) 6.0 Power Consumption Intel Flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the ...
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During program or erase modes, RP# transitioning low will abort the in-progress operation. The memory contents of the address being programmed or the block being erased are no longer valid as the data integrity has been compromised by the abort. ...
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Intel Advanced+ Boot Block Flash Memory (C3) 6.6 Power Supply Decoupling Flash memory power-switching characteristics require careful device decoupling. System designers should consider the following three supply current issues: • Standby current levels (I • Read current levels (I ...
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Operating Conditions Table 10. Temperature and Voltage Operating Conditions Symbol T Operating Temperature Supply Voltage CC1 CC V CC2 V CCQ1 V I/O Supply Voltage CCQ2 V CCQ3 V Supply Voltage PP1 V PP2 Cycling Block ...
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Intel Advanced+ Boot Block Flash Memory (C3) Table 11. DC Current Characteristics (Sheet Sym Parameter V Standby Current CC for 0.13 and 0.18 Micron Product I CCS V Standby Current CC for 0.25 Micron Product V ...
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Table 11. DC Current Characteristics (Sheet Sym Parameter I V Read Current PPR Program Current PPW Erase Current PPE Erase Suspend PPES CC I Current PPWS NOTES: ...
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Intel Advanced+ Boot Block Flash Memory (C3) 7.4 DC Voltage Characteristics Table 12. DC Voltage Characteristics V 2.7 V–3 Sym Parameter V 2.7 V–3.6 V CCQ Note Min Input Low V –0.4 IL Voltage Input High V ...
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AC Characteristics 8.1 AC Read Characteristics Table 13. Read Operations—8 Mbit Density # Sym Parameter R1 t Read Cycle Time AVAV R2 t Address to Output Delay AVQV R3 t CE# to Output Delay ELQV R4 t OE# to ...
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Intel Advanced+ Boot Block Flash Memory (C3) Table 14. Read Operations—16 Mbit Density Density 70 ns Product Para- # Sym mete r 2.7 V–3 Min Read Cycle Time AVAV t Address to AVQ ...
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Table 15. Read Operations—32 Mbit Density Density 70 ns Product Para- # Sym meter 2.7 V–3 Min Max Read Cycle Time AVAV t Address to Output AVQ R2 Delay V t CE# to Output ...
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Intel Advanced+ Boot Block Flash Memory (C3) Table 16. Read Operations — 64 Mbit Density # Sym R1 t Read Cycle Time AVAV R2 t Address to Output Delay AVQV R3 t CE# to Output Delay ELQV R4 t ...
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AC Write Characteristics Table 17. Write Operations—8 Mbit Density # Sym Parameter t / PHWL W1 RP# High Recovery to WE# (CE#) Going Low t PHEL t / ELWL W2 CE# (WE#) Setup to WE# (CE#) Going Low t ...
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Intel Advanced+ Boot Block Flash Memory (C3) Table 18. Write Operations—16 Mbit Density # Sym Parameter t / RP# High Recovery to WE# (CE#) Going PHWL W1 t Low PHEL t / ELWL W2 CE# (WE#) Setup to WE# ...
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Table 19. Write Operations—32 Mbit Density # Sym Parameter t / RP# High Recovery to WE# (CE#) PHWL W1 t Going Low PHEL t / CE# (WE#) Setup to WE# (CE#) ELWL W2 t Going Low WLEL t WLWH W3 ...
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Intel Advanced+ Boot Block Flash Memory (C3) Table 20. Write Operations—64Mbit Density # Sym t / PHWL W1 RP# High Recovery to WE# (CE#) Going Low t PHEL t / ELWL W2 CE# (WE#) Setup to WE# (CE#) Going ...
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Figure 9. Write Operations Waveform Address [A] CE# [E] WE# [W] OE# [G] Data [D/Q] W1 RP# [P] Vpp [V] 8.3 Erase and Program Timings Table 21. Erase and Program Timings Symbol 4-KW Parameter Block t BWPB Word Program Time ...
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Intel Advanced+ Boot Block Flash Memory (C3) 8.4 Reset Specifications Table 22. Reset Specifications Symbol RP# Low to Reset during Read t (If RP# is tied to V PLPH applicable) t RP# Low to Reset during Block Erase PLRH1 ...
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AC I/O Test Conditions Figure 11. AC Input/Output Reference Waveform V CCQ Input 0V NOTE: Input timing begins, and output timing ends Worst case speed conditions are when V Figure 12. Transient Equivalent Testing Load Circuit NOTE: ...
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Intel Advanced+ Boot Block Flash Memory (C3) Appendix A Write State Machine States This table shows the command state transitions based on incoming commands. Data Read Array Current State SR.7 When (FFH) Read Read Array “1” Array Read Array ...
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Read Config Read Query Current State (90H) (98H) Read Array Read Config. Read Query Read Status Read Config. Read Query Read Config. Read Config. Read Query Read Query Read Config. Read Query Lock Setup Locking Command Error Lock Cmd. Error ...
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Intel Advanced+ Boot Block Flash Memory (C3) Appendix B Flow Charts Figure 13. Word Program Flowchart Start Write 0x40, Word Address Write Data, Word Address Read Status Register 0 SR[ Full Status Check (if desired) Program Complete ...
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Figure 14. Program Suspend / Resume Flowchart Start Write 0xB0 (Program Suspend) Any Address Write 0x70 (Read Status) Any Address Read Status Register 0 SR[ SR[ Write 0xFF (Read Array) Read Array Data Done No ...
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Intel Advanced+ Boot Block Flash Memory (C3) Figure 15. Erase Suspend / Resume Flowchart Start Write 0xB0, Any Address Write 0x70, Any Address Read Status Register SR[7] = SR[6] = Write 0xFF Read Array (Read Array) Data Done Reading ...
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Figure 16. Block Erase Flowchart Start Write 0x20, (Block Erase) Block Address Write 0xD0, (Erase Confirm) Block Address Read Status Register 0 SR[ Full Erase Status Check (if desired) Block Erase Complete Read Status Register 1 SR[3] = ...
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Intel Advanced+ Boot Block Flash Memory (C3) Figure 17. Locking Operations Flowchart Start Write 0x60, Block Address Write either 0x01/0xD0/0x2F, Block Address Write 0x90 Read Block Lock Status Locking Change? Yes Write 0xFF Any Address Lock Change Complete 56 ...
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Figure 18. Protection Register Programming Flowchart Start Write 0xC0, PR Address Write PR Address & Data Read Status Register 0 SR[ Full Status Check (if desired) Program Complete Read Status Register Data SR[3], SR[ SR[3], SR[4] ...
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Intel Advanced+ Boot Block Flash Memory (C3) Appendix C Common Flash Interface This appendix defines the data structure or “database” returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information ...
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Table 25. Example of Query Structure Output of x16 Devices (Sheet 0x00014 0x00015 0x00016 0x00017 0x00018 ... C.2 Query Structure Overview The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure ...
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Intel Advanced+ Boot Block Flash Memory (C3) Table 27. Block Status Register Offset Length 1 0x(BA+2) 1 NOTES Block Address beginning location (i.e., 0x08000 is block 1’s beginning location when the block size is 32K-word). C.4 ...
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Offset Length V [programming] supply maximum program/erase voltage PP 0x1E 1 bits 0–3 BCD 100 mV bits 4–7 HEX volts 0x1F 1 “n” such that typical single word program time-out =2 0x20 1 “n” such that typical max. buffer write ...
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Intel Advanced+ Boot Block Flash Memory (C3) Table 31. Device Geometry Details 16 Mbit Address -B 0x27 --15 0x28 --01 0x29 --00 0x2A --00 0x2B --00 0x2C --02 0x2D --07 0x2E --00 0x2F --20 0x30 --00 0x31 --1E 0x32 ...
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Table 32. Primary-Vendor Specific Extended Query (Sheet Offset Length P = 0x15 (Optional Flash Features and Commands) Supported functions after suspend: Read Array, Status, Query Other supported operations are: 0x(P+9) 1 bits 1–7 reserved; undefined bits ...
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Intel Advanced+ Boot Block Flash Memory (C3) Appendix D Mechanical Specifications Figure 19. BGA* and VF BGA Package Drawing & Dimensions Ball A1 Corner Top View - Bump ...
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Figure 20. TSOP Package Drawing & Dimensions Z Pin 1 Detail B b Dimensions Package Height Standoff Package Body Thickness Lead Width Lead Thickness Plastic Body Length Package Body Width Lead Pitch Terminal Dimension Lead Tip Length Lead Count Lead ...
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Intel Advanced+ Boot Block Flash Memory (C3) Figure 21. Easy BGA Package Drawing & Dimension Ball A1 Corner Top View - Ball side down A1 A2 Dimensions ...
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Appendix E Additional Information Order Number 297938 292216 292215 Contact your Intel Representative 297874 NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. ...
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... Mbit) 320 = x16 (32 Mbit) 160 = x16 (16 Mbit) 800 = x16 (8 Mbit) VALID COMBINATIONS (All Extended Temperature) 48-Lead TSOP Extended TE28F640C3TC80 64 Mbit TE28F640C3BC80 TE28F320C3TD70 TE28F320C3BD70 TE28F320C3TC70 TE28F320C3BC70 TE28F320C3TC90 Extended 32 Mbit TE28F320C3BC90 TE28F320C3TA100 TE28F320C3BA100 TE28F320C3TA110 TE28F320C3BA110 TE28F160C3TD70 TE28F160C3BD70 TE28F160C3TC70 TE28F160C3BC70 TE28F160C3TC80 TE28F160C3BC80 ...