TC55W800FT-55 TOSHIBA Semiconductor CORPORATION, TC55W800FT-55 Datasheet

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TC55W800FT-55

Manufacturer Part Number
TC55W800FT-55
Description
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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Part Number:
TC55W800FT-55
Manufacturer:
TOSHIBA
Quantity:
4 000
524,288-WORD BY 16-BIT/1,048,576-WORD BY 8-BIT FULL CMOS STATIC RAM
DESCRIPTION
bits/1,048,576 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device
operates from a single 2.3 to 3.3 V power supply. Advanced circuit technology provides both high speed and low
power at an operating current of 3 mA/MHz and a minimum cycle time of 55 ns. It is automatically placed in
low-power mode at 0.5 mA standby current (at V
high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for
data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB )
provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of -40° to 85°C, the TC55W800FT can be used in environments exhibiting extreme temperature
conditions. The TC55W800FT is available in a plastic 48-pin thin-small-outline package (TSOP).
FEATURES
·
·
·
·
·
·
·
PIN ASSIGNMENT
The TC55W800FT is a 8,388,608-bit static random access memory (SRAM) organized as 524,288 words by 16
Low-power dissipation
Operating: 9.9 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.3 V
Power down features using CE1 and CE2
Data retention supply voltage of 1.5 to 3.3 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of -40° to 85°C
Standby Current (maximum):
48 PIN TSOP
Pin Name
Pin Name
Pin Name
Pin No.
Pin No.
Pin No.
3.3 V
3.0 V
24
1
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
I/O3 I/O11
A15
A17
17
33
1
10 mA
5 mA
(Normal)
A14
A7
18
34
(TOP VIEW)
2
I/O4 I/O12 V
A13
19
A6
35
3
A12
20
A5
36
4
48
25
A11
A4
21
37
5
DD
DD
I/O5
A10
A3
22
38
6
= 3 V, Ta = 25°C, maximum) when chip enable ( CE1 ) is asserted
I/O13 I/O6
A9
23
A2
39
7
A8
A1
24
40
8
·
·
Access Times (maximum):
Package:
I/O14 I/O7
NC
A0
25
41
Access Time
CE2 Access Time
9
CE
OE Access Time
TSOPⅠ48-P-1220-0.50 (Weight: 0.52 g typ)
PIN NAMES
1
I/O1~I/O16
CE , CE2
CE
Access Time
LB , UB
NC
A-1~A18
A0~A18
10
26
42
BYTE
GND
R/W
V
1
1
OE
NC
DD
I/O15 I/O8
GND
R/W
27
43
11
TC55W800FT-55,-70
Address Inputs (Word Mode)
Address Inputs (Byte Mode)
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Byte (´8 mode) Enable
Power
Ground
No Connection
CE2
OE
12
28
44
I/O16
55 ns
55 ns
55 ns
30 ns
I/O1
/A-1
NC
2001-10-03 1/13
13
29
45
-55
TC55W800FT
GND
I/O9
UB
14
30
46
BYTE
I/O2 I/O10
LB
15
31
47
70 ns
70 ns
70 ns
35 ns
-70
A18
A16
16
32
48

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TC55W800FT-55 Summary of contents

Page 1

... I/O5 I/O13 I/O6 I/O14 I/O7 DD TC55W800FT-55,-70 TC55W800FT - Access Time A0~A18 Address Inputs (Word Mode) A-1~A18 Address Inputs (Byte Mode CE2 Chip Enable 1 R/W Read/Write Control OE Output Enable Data Byte Control ...

Page 2

... I/O13 I/O14 I/O15 I/O16 R CE2 CONTROL BYTE CIRCUIT MEMORY CELL ARRAY 2,048 ´ 256 ´ 16 (8,388,608) SENSE AMP COLUMN ADDRESS DECODER COLUMN ADDRESS REGISTER COLUMN ADDRESS BUFFER CLOCK GENERATOR A A10 TC55W800FT-55,- GND CE A16 A11 2001-10-03 2/13 ...

Page 3

... High High High-Z RATING 40° to 85°C PARAMETER = 2.3 V~3 2.7 V~3 TC55W800FT-55,-70 I/O9~I/O15 I/O16 High-Z A-1 Output Output Output Output High-Z High-Z High-Z A-1 Input Input Input Input High-Z High-Z High-Z A-1 High-Z High-Z High-Z High-Z High-Z High-Z ...

Page 4

... DD or CE2 = 0 1.5 V~3 3.0 V BYTE = 0.2 V, these limits are assured for the condition CE2 ³ TEST CONDITION = GND GND V OUT TC55W800FT-55,-70 MIN TYP MAX ¾ ¾ ±1.0 -0.5 ¾ ¾ 2 ¾ ¾ ±1.0 ¾ ¾ ¾ ...

Page 5

... OEW t Data Setup Time DS t Data Hold Time DH AC TEST CONDITIONS PARAMETER Output load Input pulse level Timing measurements Reference level PARAMETER PARAMETER TC55W800FT-55,-70 TC55W800FT UNIT -55 -70 MIN MAX MIN MAX ¾ ¾ ¾ ¾ ¾ ¾ ...

Page 6

... OEW t Data Setup Time DS t Data Hold Time DH AC TEST CONDITIONS PARAMETER Output load Input pulse level Timing measurements Reference level PARAMETER PARAMETER TC55W800FT-55,-70 TC55W800FT UNIT -55 -70 MIN MAX MIN MAX ¾ ¾ ¾ ¾ ¾ ¾ ...

Page 7

... BYTE FUNCTION SYMBOL t BYTE Setup Time BS t BYTE Recovery Time BR TIMING DIAGRAMS BYTE CE2 CE 1 BYTE PARAMETER TC55W800FT-55,-70 MIN MAX UNIT ¾ ¾ 2001-10-03 7/13 ...

Page 8

... CO1 t CO2 OEE t COE INDETERMINATE (See Note ODW (See Note 2) (See Note 5) TC55W800FT-55,- ODO t BD VALID DATA OUT OEW Hi-Z (See Note VALID DATA IN (See Note 5) 2001-10-03 8/13 Hi-Z ...

Page 9

... I/O1~8 (Byte Mode) (See Note ODW Hi-Z t COE (See Note 5) (See Note ODW Hi-Z t COE (See Note 5) TC55W800FT-55,- Hi VALID DATA Hi VALID DATA IN 2001-10-03 9/13 ...

Page 10

... HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. (See Note 4) CONTROLLED ODW Hi-Z t COE (See Note 5) TC55W800FT-55,- Hi VALID DATA IN 2001-10-03 10/13 ...

Page 11

... -40~85°C (See Note (See Note 1) DATA RETENTION MODE (See Note 2) t CDR - 0 (See Note 3) DATA RETENTION MODE t CDR 0.2 V level, the operating current is given TC55W800FT-55,-70 ) MIN TYP MAX ¾ 1.5 3.3 ¾ ¾ 10 ¾ ¾ 1 ¾ ¾ 5 ¾ ¾ 0 ¾ ...

Page 12

... PACKAGE DIMENSIONS Weight: 0.52 g (typ) TC55W800FT-55,-70 2001-10-03 12/13 ...

Page 13

... TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. TC55W800FT-55,-70 000707EBA 2001-10-03 13/13 ...

Page 14

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