TC55VCM216ASTN55 TOSHIBA Semiconductor CORPORATION, TC55VCM216ASTN55 Datasheet

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TC55VCM216ASTN55

Manufacturer Part Number
TC55VCM216ASTN55
Description
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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TENTATIVE
262,144-WORD BY 16-BIT FULL CMOS STATIC RAM
DESCRIPTION
16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to
3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of
3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in low-power mode at 0.7 µA standby
current (at V
are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output
enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB ) provides lower and upper byte access.
This device is well suited to various microprocessor system applications where high speed, low power and battery
backup are required. And, with a guaranteed operating extreme temperature range of −40° to 85°C, the
TC55VCM216ASTN
TC55VCM216ASTN is available in a plastic 48-pin thin-small-outline package (TSOP).
FEATURES
PIN ASSIGNMENT
The TC55VCM216ASTN is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by
Low-power dissipation
Operating: 9 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using CE1 and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of −40° to 85°C
Standby Current (maximum):
48 PIN TSOP
Pin Name
Pin Name
Pin Name
Pin No.
Pin No.
Pin No.
3.6 V
3.0 V
24
1
DD
= 3 V, Ta = 25°C, typical) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low. There
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
I/O3 I/O11
A15
A17
17
33
1
10 µA
can
5 µA
(Normal)
A14
A7
18
34
(TOP VIEW)
2
be
A13
I/O4 I/O12 V
19
A6
35
3
used
A12
A5
20
36
4
in
48
25
A11
A4
21
37
DD
5
environments
I/O5
A10
A3
22
38
6
I/O13 I/O6
A9
23
A2
39
7
exhibiting
A8
A1
24
40
8
Access Times (maximum):
Package:
TSOPⅠ48-P-1214-0.50
Access Time
CE2
CE
OE
I/O14 I/O7
NC
A0
25
41
9
1
PIN NAMES
*: OP pin must be open or connected to GND.
Access Time
Access Time
Access Time
I/O1~I/O16
extreme
CE , CE2
CE
LB , UB
NC
A0~A17
10
26
42
GND
R/W
V
OP*
1
1
OE
NC
TC55VCM216ASTN40,55
DD
I/O15 I/O8
GND
R/W
27
43
11
temperature
Address Inputs
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Power
Ground
No Connection
Option
CE2
OE
12
28
44
40 ns
40 ns
40 ns
25 ns
40
TC55VCM216ASTN
I/O16 GND
I/O1
OP
2002-07-04 1/14
13
29
45
(Weight:0.35 g typ)
I/O9
UB
conditions.
14
30
46
I/O2 I/O10
NC
LB
15
31
47
55 ns
55 ns
55 ns
30 ns
55
A16
NC
16
32
48
The

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TC55VCM216ASTN55 Summary of contents

Page 1

TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 262,144-WORD BY 16-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55VCM216ASTN is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16 bits. Fabricated using Toshiba's CMOS Silicon gate ...

Page 2

BLOCK DIAGRAM A10 A11 A12 A13 A14 A15 A17 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 CE 1 CE2 LB UB R/W OE MEMORY CELL ARRAY ...

Page 3

OPERATING MODE MODE CE2 Read Write Output Deselect Standby * * * = don't care H = logic high ...

Page 4

V DC CHARACTERISTICS SYMBOL PARAMETER Input Leakage Current I Output High Current Output Low Current V OL Output Leakage ...

Page 5

AC CHARACTERISTICS AND OPERATING CONDITIONS ( − − − − 40° to 85° 2 READ CYCLE SYMBOL t Read Cycle Time RC t Address Access Time ACC ...

Page 6

AC CHARACTERISTICS AND OPERATING CONDITIONS ( − − − − 40° to 85° 2 READ CYCLE SYMBOL t Read Cycle Time RC t Address Access Time ACC ...

Page 7

AC TEST CONDITIONS PARAMETER Input pulse level Timing measurements Reference level Output load Fig.1 : Input rise and fall time V Typ DD 90% 10% GND 1 V/ TC55VCM216ASTN40,55 TEST CONDITION 0.2 V, ...

Page 8

TIMING DIAGRAMS (See Note 1) READ CYCLE Address A0~A17 CE 1 CE2 OUT Hi-Z I/O1~16 WRITE CYCLE 1 (R/W CONTROLLED) Address A0~A17 R CE2 OUT I/O1~ I/O1~16 ...

Page 9

WRITE CYCLE 2 ( CE1 CONTROLLED) Address A0~A17 CE2 OUT Hi-Z I/O1~ (See Note 5) I/O1~16 WRITE CYCLE 3 (CE2 CONTROLLED) Address A0~A17 CE2 ...

Page 10

WRITE CYCLE Address A0~A17 R CE2 OUT I/O1~ I/O1~16 Note: (1) R/W remains HIGH for the read cycle. (2) If CE1 ( goes ...

Page 11

DATA RETENTION CHARACTERISTICS ( SYMBOL V Data Retention Supply Voltage DH I Standby Current DDS2 t Chip Deselect to Data Retention Mode Time CDR t Recovery Time R CE1 CONTROLLED DATA RETENTION MODE 2 ...

Page 12

Note: (1) In CE1 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0 CE2 ≥ V − 0 (2) When CE1 is operating at the V transition of V from 2.3(2.7) ...

Page 13

PACKAGE DIMENSIONS TSOPⅠ48-P-1214-0. Weight:0.35 g (typ 12.4 0.1 14.0 0.2 TC55VCM216ASTN40,55 Unit:mm 1.0 0.1 0.1 0.05 1.2max 0.5 0.1 2002-07-04 13/14 ...

Page 14

RESTRICTIONS ON PRODUCT USE • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress ...

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