MT9075AP Mitel, MT9075AP Datasheet
MT9075AP
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MT9075AP Summary of contents
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... R/W/WR CS DS/RD DSTo ST-BUS CSTo Interface RxDLCLK RxDL MT9075AP MT9075AL Description The MT9075A is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for S The LIU interfaces the framer functions to the PCM 30 transformer-isolated four wire line ...
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MT9075A CS RESET IRQ VSS IC INT/MOT VDD R/W/WR AC0 RESET IRQ VSS IC INT/MOT 92 VDD 94 ...
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Preliminary Information Pin Description Pin # Name PLCC MQFP 1 66 OSC1 Oscillator Input. This pin is either connected via a 20.000 MHz crystal to OSC2 where a crystal is used directly driven when a 20.000 MHz oscillator ...
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MT9075A Pin Description (continued) Pin # Name PLCC MQFP 17 90 VSS Negative Power Supply (Input). Digital ground Internal Connection. Tie INT/MOT Intel/Motorola Mode Selection (Input). A high on this pin configures the ...
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Preliminary Information Pin Description (continued) Pin # Name PLCC MQFP 45 33 C4b 4.096 MHz System Clock (Input/Output). C4b is the clock for the ST-BUS sections and transmit serial PCM data of the MT9075A. In the free-run (BL/FR=0) or line ...
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MT9075A Pin Description (continued) Pin # Name PLCC MQFP 64 61 TxDLCLK Transmit Data Link Clock (Output). A gapped clock signal derived from a gated 2.048 Mbit/s clock for transmit data link 12 kHz. ...
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Preliminary Information Device Overview The MT9075A is an advanced PCM 30 framer with an on-chip Line Interface Unit (LIU) that meets or supports the latest ITU-T Recommendations for PCM 30 and ISDN primary rate including G.703, G.704, G.706, G.775, G.796, ...
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MT9075A Functional Description MT9075A Line Interface Unit (LIU) Receiver The receiver portion of the MT9075A LIU consists of an input signal peak detector, an optional two-stage equalizer, a smoothing filter, adaptive threshold comparators, data and clock slicers, and a clock ...
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Preliminary Information 0.68uF 1:2 2.4 * TTIP TRING 2 2.4 required with 75 MT9075A 1:1 RTIP 120 RRING Figure 4 - Analog Line Interface The template for the transmitted pulse, as specified in G703, is shown in Figure ...
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MT9075A MT9075A 20MHz OSC1 56pF 1M 100 OSC2 Note: the 1 H inductor is optional Figure 7 - Crystal Oscillator Circuit Jitter Attenuator (JA) The MT9075A Jitter Attenuator (JA), which consists of a Phase Locked Loop (PLL) and data FIFO, ...
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... This results in a single time slot data rate of 8 bits x 8000/sec kbits/sec. It should be noted that the Mitel ST-BUS also has 32 channels numbered 0 to 31, but the most significant bit of an eight bit channel is numbered bit 7 (see Mitel Application Note MSAN-126). Therefore, ST- BUS bit 7 is synonymous with PCM 30 bit 1 ...
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MT9075A data. Channel alignment and bit numbering is consistent with time slot alignment numbering. However, channels are numbered and relate to time slots as per Table 3. PCM 3...15 Timeslot Voice/Data x 1 ...
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Preliminary Information SYNC CRCSYN CRCIWK Table 4 - Transmit RAI setting for CRC to non CRC interworking with AUTC set low There are two CRC ...
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MT9075A of memory is selected only necessary to write to the CAR when a different page accessed. See Figures 11 and 12 for timing requirements. Please note that for microprocessors with read/write cycles less than ...
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Preliminary Information Function Mode Termination Loopbacks Deactivated Transmit FAS Transmit non-FAS 1/S Transmit MFAS (CAS) Data Link Deactivated CRC Interworking Signalling CAS Registers ABCD Bit Debounce Deactivated Interrupts Interrupt Mask Word Zero unmasked, all others masked; interrupts not suspended RxMF ...
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MT9075A The CRC-4 Alignment status CALN (page 03H, address 12H) and maskable interrupt CALNI (page 01H, address 1DH) indicate the beginning of every received CRC-4 multiframe. Maskable interrupts are available for change of state of S bits or change of ...
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Preliminary Information HDLC0 Functions When connected to the Data Link (DL) HDLC0 will operate at a selected bit rate 12 kbits/sec. HDLC0 can be selected by setting the control bit HDLC0 (bit 7) to ...
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MT9075A • A short frame exists if there are less than 25 bits between the flags. Short frames are ignored by the receiver and nothing is written to the receive FIFO. • Packets which are at least 25 bits in ...
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Preliminary Information the tag bits being loaded in the FIFO, Control Register 1 must be written to before writing to the FIFO. However, EOP and FA are reset after writing to the TX FIFO. The Transmit Byte Count Register may ...
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MT9075A The end-of-packet-detect (EOPD) interrupt indicates that the last byte written to the RX FIFO was an EOP byte. The end-of-packet-read (EOPR) interrupt indicates that the byte about to be read from the RX FIFO is an EOP byte. The ...
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Preliminary Information Two status bits, RSLIP and RSLPD (page 03H, address 15H), give indication of a slip occurrence and direction. RSLIP changes state in the event of a slip. If RSLPD=0, the slip buffer has overflowed and a frame was ...
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MT9075A >914 CRC errors in one second No CRC multiframe alignment. 8 msec. timer expired* CRC-4 multi-frame alignment Start 400 msec timer. Note 7. Start 8 msec timer. Note 7. Find two CRC frame alignment signals. Note 7. CRC multiframe ...
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Preliminary Information Notes for Synchronization State Diagram (Figure 10) 1) The basic frame alignment, signalling multiframe alignment, and CRC-4 multiframe functions operate in parallel and are independent. 2) The receive channel associated signalling bits and signalling multiframe alignment bit will ...
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MT9075A MT9075A DSTi System DSTo b) Remote Loopback (RM Loop) - RTIP and RRING to TTIP and TRING respectively at the PCM 30 side. Bit RLBK = 0 normal; RLBK = 1 activate. MT9075A System DSTo c) ST-BUS Loopback (ST ...
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Preliminary Information CRC Multiframe Counter for PRBS (PSM7-0) This eight bit counter counts receive CRC-4 multiframes. It can be directly loaded via the microport. The counter will also be automatically cleared in the event that the PRBS error counter is ...
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MT9075A (BPVE), CRC-4 errors (CRCE), FAS errors (FASE), NFAS errors (NFSE), payload (PERR) and a loss of signal error (LOSE). The LOSE function overrides the HDB3 encoding function. Per Time Slot Control There are two per time slot control pages ...
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Preliminary Information • Alarm Indication Signal (AIS) - unframed all ones signal for at least a double frame (512 bits) or two double frames (1024 bits); • Channel 16 Alarm Indication Signal - all ones signal in channel 16; • ...
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MT9075A All interrupts may be suspended, without changing the interrupt mask words, by making the SPND control bit (page 01H, address 1AH) high. Also, when pin TAIS is held low, all interrupts are suspended automatically. This allows for system initialization ...
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Preliminary Information Control and Status Registers Master Control 1 (Page 01H) Address ( 10H (Table 13) Multiframe, National Bit Buffer and Data Link Selection Word 11H (Table 14) Mode Selection ...
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MT9075A Bit Name Functional Description 7 ASEL AIS Select. This bit selects the criteria on which the detection of a valid Alarm Indication Signal (AIS) is based. If zero, the criteria is less than three zeros in a two frame ...
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Preliminary Information 1 CSYN CRC-4 Synchronization. If zero, basic CRC-4 processing is activated, and TIU0 bit and TIU1 bit programming will be overwritten. If one, CRC-4 synchronization is disabled, the first bits of channel 0 are used as international use ...
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MT9075A Bit Name Functional Description 7 HDLC0 HDLC0 Select. If one, then HDLC0 is connected to the data link on selected S bits at a rate 12 kbits/sec. If zero, HDLC0 is deselected ...
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Preliminary Information Bit Name Functional Description 7 TAIS Transmit Alarm Indication Signal. If one, an all ones signal is transmitted. TAIS=0 operation. 6 TAIS0 Transmit AIS Time Slot Zero. If one, an all transmitted in time slot zero. If zero, ...
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MT9075A Bit Name Functional Description 7 ODE Output Data Enable. If one, the DSTo and CSTo output drivers function normally. When low, DSTo and CSTo will be tristated. Note: When ODE =1, DSTo and CSTo can be individually tristated by ...
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Preliminary Information Bit Name Functional Description 7 SYNI Synchronization Interrupt. When unmasked (SYNI = 0) an interrupt is initiated when a loss of basic frame synchronization Interrupt vector = 10000000. 6 RAII Remote Alarm Interrupt. When unmasked (RAII = 0) ...
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MT9075A Bit Name Functional Description 0 SIGI Signalling (CAS) Interrupt. When unmasked and any of the receive ABCD bits of any channel changes state an interrupt is initiated unmasked masked. Interrupt vector = 00000001 Table 23 ...
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Preliminary Information Bit Name Functional Description 7 MFSYI Multiframe Interrupt. When (MFSYI = 1), an interrupt is initiated when multiframe synchronization is lost. Interrupt vector = 10000000. 6 CSYNI CRC-4 Synchronization Interrupt. When unmasked (CSYNI = 1), an interrupt is ...
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MT9075A Address ( 10H (Table 28) Error and Debounce Selection Word 11H --- 12H --- 13H (Table 29) Access Control Word 14H --- 15H --- 16H --- 17H --- 18H ...
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Preliminary Information Bit Name Functional Description 7 BPVE Bipolar Violation Error Insertion. A zero-to-one transition of this bit inserts a single bipolar violation error into the transmit PCM 30 data. A one, zero or one-to-zero transition has no function. 6 ...
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MT9075A Bit Name Functional Description 7 JAS Jitter Attenuator Select. If one, the attenuator may be connected to either the transmit or receive sides of the PCM 30 interface depend on bit 6 - JAT/JAR. If zero, the jitter attenuator ...
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Preliminary Information Master Status 1 (Page 03H) Address Register ( 10H (Table 33) Synchronization Status Word 11H (Table 34) Receive Frame Alignment Signal 12H (Table 35) Timer Status Word 13H ...
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MT9075A Bit Name Functional Description 7 SYNC Receive Basic Frame Alignment. SYNC indicates the basic frame alignment status (1 - loss acquired). 6 MFSYNC Receive Multiframe Alignment. MFSYNC indicates the multiframe alignment status (1 - loss ...
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Preliminary Information Bit Name Functional Description 7 1SEC One Second Timer Status. This bit changes state once every 0.5 second and is synchronous with the 2SEC timer. This feature is not available when operated in freerun mode. 6 2SEC Two ...
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MT9075A Bit Name Functional Description RMA1-4 Receive Multiframe Bits One to Four. These bits are received on the PCM 30 2048 kbit/ sec. link in bit positions one to four of time slot 16 of frame zero ...
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Preliminary Information Bit Name Functional Description RxEBC7 -0 Receive Eighth Bit Count. The 8 least significant bit of a counter that indicates the number of one eighth bit times there are between the ST-BUS frame pulse and ...
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MT9075A Bit Name Functional Description 7 CRCS1 Receive CRC Error Status One. If one, the evaluation of the last received submultiframe 1 resulted in an error. If submultiframe 1 was error free. Updated on a submultiframe 1 basis. 6 CRCS2 ...
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Preliminary Information Master Status 2 (Page 04H) Address ( 10H (Table 46) PRBS Error Counter 11H (Table 47) CRC Multiframe counter for PRBS 12H (Table 48) Interrupt Vector 13H (Table ...
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MT9075A Bit Name Functional Description PS7-0 PRBS Error Counter. This counter is incremented for each PRBS error detected on any of the receive channels connected to the PRBS error detector. Table 46 - PRBS Error Counter (Page ...
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Preliminary Information Bit Name Functional Description 7 PRBSO PRBS Error Counter Overflow. This bit is set to one when the PRBS Error Counter (page 04H address 10H) cleared when this register is read. 6 FEBEO E Bit Counter Overflow. This ...
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MT9075A Bit Name Functional Description EFAS7 Errored FAS Counter bit counter that is incremented once for - every receive EFAS0 signal that contains one or more errors. Table 56 - Errored Frame Alignment Signal Counter ...
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Preliminary Information Per Channel Transmit Signalling (Page 05H) Table 62 describes Page 05H, addresses 11H to 1FH, which contains the Transmit Signalling Control Words for PCM 30 channels and 16 to 30. Control of these bits is ...
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MT9075A Per Channel Receive Signalling (Page 06H) Page 06H, addresses 11H to 1FH contain the Receive Signalling Control Words for PCM 30 channels and 16 to 30. Bit Name A(n), B(n), C(n), D(n) 3 ...
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Preliminary Information Per Time Slot Control Words (Pages 07H and 08H) The control functions described by Table 69 are repeated for each PCM-30 channel. Page 07H addresses 10H to 1FH correspond to time slots 0 to 15, while page 08H ...
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MT9075A One Second Status (Page 09H) Address ( 10H MSB Latched (Table 71) E-bit Error Count 11H LSB Latched E-bit Error Count (Table 72) 12H Latched Errored Frame Alignment Signal ...
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Preliminary Information Bit Name Functional Description --- Unused LEC9 Latched E bit error counter (the most significant two bits). These - bits are sampled every second by LEC8 the internal one second timer. Table ...
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MT9075A HDLC Control and Status (Page 0BH & 0CH) Address Control (Write/Verify) 10H (Table 79) Address Recognition 1 11H (Table 80) Address Recognition 2 12H (Table81) TX FIFO & (Table 82) 13H (Table 83) HDLC Control 1 14H (Table 84) ...
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Preliminary Information Bit Name Functional Description Adr16 A six bit mask used to interrogate the first byte of the received - address. Adr16 is the MSB. Adr11 1 Adr10 This bit is used comparison, if control bit ...
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MT9075A Bit Name Functional Description 7 Adrec Address Recognition. When one this bit will recognition. This receiver to recognize only those packets having the unique address as programmed in the Receive Address Recognition Registers or if the address is an ...
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Preliminary Information Bit Name Functional Description 3, 2 Txstat2, Transmit Status. Txstat1 indicate the status of the TX FIFO as follows: Txsta Txsta FIFO full up to the selected status level or more. See Table ...
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MT9075A Bit Name Functional Description 7-0 Ga, This register is used with the EOPD, Interrupt Register to mask out the TEOP, interrupts that are not required by EOPR, the microprocessor. Interrupts that TxFl, are masked out will not produce an ...
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Preliminary Information Bit Name Functional Description Crc7 - 0 The LSB byte of the CRC received from the transmitter. These bits are as the transmitter sent them; that is, most significant inverted. This register is updated at ...
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MT9075A Bit Name Functional Description RSV These bits are reserved. 3 RXclk This bit represents the receiver clock generated after the RXEN control bit is enabled, but before zero deletion is considered. 2 TXclk This bit represents ...
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Preliminary Information Bit Name Functional Description 7 --- Unused RFFS2 - 0 These bits select the RXFF (Rx FIFO Full) interrupt threshold level: RFFS RFFS RFFS ...
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MT9075A Transmit National Bit Buffer (Page 0DH) Page 0DH, addresses 10H to 14H contain the five bytes of the transmit national bit buffer (TNBB0 - TNBB4 respectively). This feature is functional only when control bit NBTB (page 01H, address 10H) ...
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Preliminary Information Page 0FH, addresses 10H to 1FH contain the 16 bytes of transmit message buffer zero Bit Name TxB0.n.7 - Transmit Bits This byte is transmit on a time slot when selected by ...
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MT9075A Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage at Digital Inputs 3 Current at Digital Inputs 4 Voltage at Digital Outputs 5 Current at Digital Outputs 6 Storage Temperature * Exceeding these values may cause permanent damage. Functional ...
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Preliminary Information AC Electrical Characteristics Characteristics 1 DS low 2 DS High 3 CS Setup 4 R/W Setup 5 Address Setup 6 CS Hold 7 R/W Hold 8 Address Hold 9 Data Delay Read 10 Data Hold Read 11 Data ...
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MT9075A AC Electrical Characteristics Characteristics 1 RD low 2 RD High 3 CS Setup 4 CS Hold 5 Address Setup 6 Address Hold 7 Data Delay Read 8 Data Active to High Z Delay 9 Data Setup Write 10 Data ...
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Preliminary Information AC Electrical Characteristics - Transmit Data Link Timing Characteristic 1 Data Link Clock Output Delay 2 Data Link Setup 3 Data Link Hold F0b TIME SLOT 0 Bits 4,3,2,1,0 TxDLCLK TxDL TxDLCLK TxDL Figure 13 - Transmit Data ...
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MT9075A AC Electrical Characteristics - Receive Data Link Timing Characteristic 1 Data Link Clock Output Delay 2 Data Link Output Delay RxFP TIME SLOT 0 Bits 4,3,2,1,0 RxDLCLK RxDL RxDLCLK RxDL Figure 15 - Receive Data Link Functional Timing E2o ...
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Preliminary Information AC Electrical Characteristics - Transmit 64 k Common Channel Timing Characteristic 2 Transmit Common Channel Setup 3 Transmit Common Channel Hold F0b STBUS Channel Times Internal Clock CSTi Figure 17 - Transmit 64k Common Channel Functional Timing C4b ...
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MT9075A AC Electrical Characteristics - Receive 64k Common Channel Timing Characteristic 1 Receive Common Channel Output Delay Rx64KCK CSTo Figure 19 - Receive 64k Common Channel Functional Timing Rx64KCK CSTo Figure 20 - Receive 64k Common Channel Timing Diagram 4-200 ...
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Preliminary Information AC Electrical Characteristics - ST-BUS / GCI Timing Characteristic 1 C4b Clock Width High or Low 2 C4b Clock Width High or Low 3 Frame Pulse Setup 4 Frame Pulse Hold 5 Frame Pulse Delay 6 Serial Input ...
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MT9075A ST-BUS Bit Bit Cell Stream F0b (Output) t FPD C4b (Output) All Input Streams All Output Streams Figure 23 - ST-BUS Timing Diagram (Output Clocks) ST-BUS Channel 31 Bit Cells Bit 0 F0b C4b Figure 24 - GCI Functional ...
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Preliminary Information ST-BUS Bit Bit Cell Stream F0b (Input) C4b (Input) All Input Streams All Output Streams Figure 25 - GCI Timing Diagram (Input Clocks) ST-BUS Bit Bit Cell Stream F0b (Output) t FPD C4b (Output) All Input Streams All ...
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MT9075A AC Electrical Characteristics - Multiframe Timing Characteristic 1 Receive Multiframe Output Delay 2 Transmit Multiframe Setup 3 Transmit Multiframe Hold Frame 15 DSTo BIt Cells Bit 7 Bit 6 Bit 5 F0b C4b (4.096 MHz) RxMF Figure 27 - ...
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Preliminary Information F0b t MOD C4b (1) RxMF t MS (1) TxMF (1) Note : These two signals do not have a defined phase relationship Figure 29 - Multiframe Timing Diagram FRAME FRAME 15 0 TIME SLOT Most BIT Significant ...
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MT9075A Notes: 4-206 Preliminary Information ...