MT8931CE Mitel, MT8931CE Datasheet
MT8931CE
Available stocks
Related parts for MT8931CE
MT8931CE Summary of contents
Page 1
... Control XTAL1/NT XTAL2/NC Rsti HALF CMOS ST-BUS Subscriber Network Interface Circuit MT8931CE MT8931CP Description The MT8931C Subscriber Network Interface Circuit (SNIC) implements the ETSI ETS 300-012, CCITT I.430 and ANSI T1.605 Recommendations for the ISDN S and T reference points. Providing point-to- point and point-to-multipoint digital transmission, the SNIC may be used at either end of the subscriber line (NT or TE) ...
Page 2
MT8931C 28 1 HALF 2 27 C4b 26 F0b 3 25 F0od DSTi 23 DSTo 6 22 XTAL2/ XTAL1/ R/W/ DS/RD 10 AS/ALE IRQ/NDA 16 13 ...
Page 3
Pin Description (continued) Pin # Name DIP PLCC 9 16 R/W WR Read/Write or Write Input: defines the data bus transfer as a read (R/W= write / (R/W=0) in Motorola bus mode. Redefined Intel bus ...
Page 4
MT8931C Functional Description The MT8931C Subscriber Network Interface Circuit (SNIC multifunction transceiver providing a complete interface to the S/T Reference Point as specified in ETS 300-012, CCITT Recommendation I.430 and ANSI T1.605. Implementing both point-to-point and point-to-multipoint transmission, ...
Page 5
Figure 4 - ST-BUS Channel Assignment The B1 and B2 channels each have a bandwidth of 64 kbit/s and are used to carry PCM voice or data across the network. The D-channel is primarily intended to carry signalling information for ...
Page 6
MT8931C 9-76 ...
Page 7
Framing The valid frame structure transmitted by the NT and TE contains the following (refer Fig. 6 TE: - Framing bit ( and B2 channels (B1,B2 balancing bits (L) - D-channel bits (D0, D1) ...
Page 8
MT8931C The C-channel bit mapping from the parallel port to the ST-BUS is organized such that the most significant bit is transmitted or received first. State Activation The state activation controller deactivates the SNIC in response to line activity or ...
Page 9
B and D-channel and activation bit (A-bit) set to zero soon as the TE synchronizes to Info2, it responds with a valid S-Bus frame with data in the B1, B2 and D-channel (Info3). 5) ...
Page 10
MT8931C After successfully completing a transmission, the internal priority level is reduced from high to low. The internal priority will only be increased once the terminal count for the respective level of priority has been achieved. (e.g has ...
Page 11
This allows multiple TEs to share a common ST-BUS timebase. The synchronization of the loops is established by using the clock signals produced by a ...
Page 12
MT8931C filtering out jitter which may be present on the received line port. The SNIC uses the first four channels on the ST-BUS (as shown in Figure 4). distribution of the serial stream, provides a delayed frame pulse (F0od) to ...
Page 13
The parallel port on the SNIC allows complete control of the HDLC transceiver and access to all data, control and status registers. registers allows the microprocessor to monitor incoming data on the S or ST-BUS without interrupting the normal data ...
Page 14
MT8931C ii) Data The data field refers to the Address, Control and Information fields defined recommendations. A valid frame should have a data field of at least 16 bits. The first and second byte in the data field is the ...
Page 15
If the HDLC transmitter is data mode, the protocol functions are disabled and the data in the transmit FIFO is transmitted without a framing structure. To indicate that the particular byte is the last byte of the packet, the ...
Page 16
MT8931C Registers. If one byte address recognition is enabled, the address field is one byte long and it is compared with the six most significant bits in address recognition register 1. If two byte address recognition is enabled, the address ...
Page 17
BIT NAME ‘1’ will allow access to Control Register 1 and Master Status Register. A ‘0’ will prevent it. (1) B6-B3 NA Keep at ’0’ for normal operation. B2 IRQ/NDA The state of this pin will select ...
Page 18
MT8931C BIT NAME (3) B7 CH3i If ’1’, then the ST-BUS channel 3 input port is enabled (B2-channel). If ’0’, then the channel is disabled, and will read FF (3) B6 CH2i If ’1’, then the ST-BUS channel 2 input ...
Page 19
BIT NAME B7-B5 NA Keep at ’0’ for normal operation. B4 Trans A ’1’ will place the HDLC in a transparent mode. This will perform the serial to parallel or parallel to serial conversion without inserting or deleting the opening ...
Page 20
MT8931C BIT NAME B7 EnDcoll A ’1’ will enable the D-channel collision interrupt. A ’0’ will disable it. This bit is available only in TE mode. B6 EnEOPD A ’1’ will enable the received End of Packet interrupt. A ’0’ ...
Page 21
BIT NAME B7-B2 R1A7-R1A2 A six bit mask used to interrogate the first byte of the received address (where B7 is MSB). If address recognition is enabled, any packet failing the address comparison will not be stored in the Rx ...
Page 22
MT8931C BIT NAME B7-B6 Loop The status of these two bits determine which type of loopback performed FSync If ’1’, the ...
Page 23
BIT NAME B7 AR Setting this bit will initiate the activation of the S-Bus. If ’0’, the device will remain in the present state Setting this bit will initiate the deactivation of the S-Bus. If ’0’, the device ...
Page 24
MT8931C BIT NAME B7 Sync/BA This bit is set if the device has achieved frame synchronization while the activation request is asserted ( and AR = 1). If there is a deactivation request or that AR is low ...
Page 25
Applications The MT8931C is useful in a wide variety of ISDN applications. Being used at both the Network Termination (NT) and Terminal Equipment (TE) ends of the line, the SNIC finds application on digital subscriber line cards and in full ...
Page 26
MT8931C Termination Network MH89101 U Reference Point Figure 17 - NT1 using the MT8910-1 (DSLIC) and MT8931C (SNIC) MT8931C ‡ R LTx V Bias ‡ R LRx 1:2 2k Data Port IRQ + ...
Page 27
MT8931C AD0-AD7 Connections to interface to MC6809 Figure 19 - Interfacing to the MC6802 Microprocessor TS 300-012 NT&TE Line Interface Figures 20, 21 and 22 show the recommended line interface circuits for meeting the ETS 300-012 requirements. These circuits assume ...
Page 28
MT8931C In Figure 21, two types of diodes (germanium 1N270 or schottky MBD301) can be used for D5,6. 1N270 will leave more margin for pulse template and longitudinal conversion loss. However, MBD301 will leave more margin for impedance template. All ...
Page 29
MT8931C D5 LTx Bias R1 LRx Figure 21 - ETS 300-012 NT & TE Line Interface for VAC X027 or X028 ...
Page 30
MT8931C MT8931C R1 LTx Bias R2 LRx V SS Figure 23 - Proprietary NT & TE Line Interface 9-100 ...
Page 31
Absolute Maximum Ratings Parameters 1 Supply Voltage 2 Voltage on any I/O pin 3 Current on any I/O pin 4 Storage Temperature 5 Package Power Dissipation * Exceeding these values may cause permanent damage. Functional operation under these conditions is ...
Page 32
MT8931C AC Electrical Characteristics Characteristics 1 F0b input pulse width 2 Frame pulse (F0b) set-up time 3 Frame pulse (F0b) hold time 4 C4b input clock period 5 C4b pulse width High or Low 6 C4b transition time 7 F0od ...
Page 33
AC Electrical Characteristics Characteristics 1 F0b output pulse width 2 C4b to (F0b) delay 3 C4b to (F0b) hold time 4 C4b output clock period 5 C4b pulse width High or Low 6 C4b transition time 7 F0od delay 8 ...
Page 34
MT8931C AC Electrical Characteristics Characteristics 1 Chip select setup time 2 Chip select hold time 3 Address Latch pulse width 4 Address setup time 5 Address hold time 6 Data setup time - Write 7 Data hold time - Write ...
Page 35
AC Electrical Characteristics Characteristics 1 Chip select setup time 2 Chip select hold time 3 Address strobe pulse width 4 Data strobe setup time 5 Data strobe hold 6 Data strobe pulse width - Read 7 Read/Write setup time 8 ...
Page 36
MT8931C AC Electrical Characteristics Characteristics 1 Interrupt release delay 2 Reset pulse width † Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ‡ Typical figures are and are for design ...
Page 37
Package Outlines xxxx xxxxxxxxxxxxxxx xxxx xxxx x xxxx xxxxxxxxxxxxxxxxx Dim D ...
Page 38
Package Outlines Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 8-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.115 (2.92) ...
Page 39
Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 22-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.125 (3.18) 0.195 ...
Page 40
... Mitel. This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specifi ...