MCM56824AFN25 Freescale Semiconductor, Inc, MCM56824AFN25 Datasheet

MCM56824AFN25

Manufacturer Part Number

MCM56824AFN25

Description

Manufacturer

Freescale Semiconductor, Inc

Datasheet

1.MCM56824AFN25.pdf (10 pages)

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Company:

Meier Automation Equipment Co., Limited

Part Number:

MCM56824AFN25

Manufacturer:

MOTOROLA/摩托罗拉

Quantity:

20 000

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DSPRAM

8K x 24 Bit Fast Static RAM

8,192 words of 24 bits. The device integrates an 8K x 24 SRAM core with multiple

chip enable inputs, output enable, and an externally controlled single address pin

multiplexer. These functions allow for direct connection to the Motorola

DSP56001 Digital Signal Processor and provide a very efficient means for imple-

mentation of a reduced parts count system requiring no additional interface logic.

puts provides for greater system flexibility when multiple devices are used. With

either chip enable input unasserted, the device will enter standby mode, useful

in low–power applications. A single on–chip multiplexer selects A12 or X/Y as the

highest order address input depending upon the state of the V/S control input.

This feature allows one physical static RAM component to efficiently store pro-

gram and vector or scalar operands by dynamically re–partitioning the RAM

array. Typical applications will logically map vector operands into upper memory

with scalar operands being stored in lower memory. By connecting

DSP56001address A15 to the VECTOR/SCALAR (V/S) MUX control

pin, such partitioning can occur with no additional components. This al-

lows efficient utilization of the RAM resource irrespective of operand

type. See application diagrams at the end of this document for addition-

al information.

induced by output noise.

(PLCC) and a 9 x 10 grid, 86 bump surface mount PBGA.

DSPRAM is a trademark of Motorola, Inc.

MOTOROLA FAST SRAM

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

REV 2

4/95

The MCM56824A is a 196,608 bit static random access memory organized as

The availability of multiple chip enable (E1 and E2) and output enable (G) in-

Multiple power and ground pins have been utilized to minimize effects

The MCM56824A is available in a 52 pin plastic leaded chip–carrier

Motorola, Inc. 1995

Single 5 V

Fast Access and Cycle Times: 20/25/35 ns Max

Fully Static Read and Write Operations

Equal Address and Chip Enable Access Times

Single Bit On–Chip Address Multiplexer

Active High and Active Low Chip Enable Inputs

Output Enable Controlled Three State Outputs

High Board Density PLCC Package

Low Power Standby Mode

Fully TTL Compatible

For proper operation of the device, all V SS

pins must be connected to ground.

A0 – A11

A12, X/Y

V/S

E1, E2

DQ0 – DQ23

V CC

V SS

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10% Power Supply

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PIN NAMES

Address Multiplexer Control

Multiplexed Address

+5 V Power Supply

Data Input/Output

Address Inputs

No Connection

Output Enable

Write Enable

Chip Enable

Ground

DQ10

DQ9

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

V SS

Not to Scale

V CC

V SS

D11

D10

D13

D12

VIEW OF PBGA PACKAGE BOTTOM

MCM56824A

PIN ASSIGNMENTS

V SS

D14

PLCC

D15

D16

D17

86 BUMP PBGA

Order this document

CASE 896A–01

D18

D19

52–LEAD PLCC

9 x 10 GRID

FN PACKAGE

CASE 778–02

by MCM56824A/D

V SS

D20

MCM56824A

D21

D22

A10

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ15

V SS

DQ14

DQ13

D23

V/S

V SS

A12

V CC

X/Y

A11

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MCM56824AFN25 Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA DSPRAM Bit Fast Static RAM The MCM56824A is a 196,608 bit static random access memory organized as 8,192 words of 24 bits. The device integrates SRAM core with multiple ...

Page 2

V/S X A12 MUX A0 A5 A10 A11 DQ0 DQ23 TRUTH TABLE V Not Selected Not Selected ...

Page 3

DC OPERATING CONDITIONS AND CHARACTERISTICS ( 5.0 V RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * V IL (min) = – 3 (pulse width 20 ns) DC CHARACTERISTICS ...

Page 4

AC OPERATING CONDITIONS AND CHARACTERISTICS ( 5.0 V Input Timing Measurement Reference Level . . . . . . . . . . . . . . . Input Pulse Levels . . . . . . . ...

Page 5

WRITE CYCLE TIMING (Write Enable Initiated, See Note 1) Parameter Write Cycle Time Address Setup Time MUX Control Setup Time Address Valid to End of Write MUX Control Valid to End of Write Write Pulse Width Write Enable to Chip ...

Page 6

WRITE CYCLE TIMING (Chip Enable Initiated, See Note 1) Parameter Write Cycle Time Address Setup Time MUX Control Setup Time t VSVE1L t VSVE2H Address Valid to End of Write MUX Control Valid to End of Write t VSVE1H t ...

Page 7

... RAM A12 MEMORY V/S = “0” ORDERING INFORMATION (Order by Full Part Number Shipping Method (R2 = Tape and Reel, Blank = rails) Speed ( ns ns ns) Package (FN = PLCC PBGA) MCM56824AFN25 MCM56824AFN35 MCM56824AZP25 MCM56824AZP35 MCM56824A D0 – D23 A0 – A11 A12 A12 MEMORY MANAGEMENT ...

Page 8

B - -A- MCM56824A 8 PACKAGE DIMENSIONS ZP PACKAGE PBGA CASE 896A–01 0.20 (0.008) - ...

Page 9

Y BRK -L- -M- 52 LEADS ACTUAL W 1 (NOTE 0.25(0.010 0.25(0.010 0.10 (0.004 (NOTE 1) DETAIL 0.25(0.010 –M N –P ...

Page 10

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...

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