SB82371SB Intel Corporation, SB82371SB Datasheet
SB82371SB
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SB82371SB Summary of contents
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... USB ports. PIIX3 also provides support for an external IOAPIC. This document describes the PIIX3 Component. Unshaded areas describe the 82371FB PIIX. Shaded areas, like this one, describe the PIIX3 operations that differ from the 82371FB PIIX. © INTEL CORPORATION 1996, 1997 n Enhanced DMA Functions ...
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AND 82371SB (PIIX3) PCICLK AD[31:0] C/BE[3:0]# FRAME# TRDY# IRDY# PCI STOP# Bus DEVSEL# Interface SERR# PAR IDSEL PHOLD# PHOLDA# MDRQ[1:0] Mother PIIX Only Board MDAK[1:0]# (Not On PIIX3) Interface MIRQ1 MIRQ0 PWROK CPURST System RSTDRV Reset INIT PCIRST# ...
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REVISION HISTORY...................................................................................................................................... 7 1.0. SIGNAL DESCRIPTION .......................................................................................................................... 9 1.1. PCI Interface Signals ........................................................................................................................... 9 1.2. Motherboard I/O Device Interface Signals .......................................................................................... 10 1.3. IDE Interface Signals ......................................................................................................................... 11 1.4. ISA Interface Signals.......................................................................................................................... 13 1.5. DMA Signals ...................................................................................................................................... 15 1.6. Timer/Counter ...
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AND 82371SB (PIIX3) 2.2.19. SMIEN—SMI ENABLE REGISTER (Function 0) ....................................................................... 43 2.2.20. SEE—SYSTEM EVENT ENABLE REGISTER (Function 0) ...................................................... 44 2.2.21. FTMR—FAST OFF TIMER REGISTER (Function 0)................................................................. 45 2.2.22. SMIREQ—SMI REQUEST REGISTER (Function 0) ................................................................. 45 2.2.23. CTLTMR—CLOCK ...
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DMA Memory Low Page Registers ....................................................................................... 65 2.5.1.10. DMA Clear Byte Pointer Register........................................................................................ 66 2.5.1.11. DMC—DMA Master Clear Register..................................................................................... 66 2.5.1.12. DCLM—DMA Clear Mask Register ..................................................................................... 66 2.5.2. TIMER/COUNTER REGISTER DESCRIPTION .......................................................................... 66 2.5.2.1. TCW—Timer Control Word Register..................................................................................... 66 ...
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AND 82371SB (PIIX3) 3.1. Memory and I/O Address Map ........................................................................................................... 89 3.1.1. I/O Accesses ............................................................................................................................... 89 3.1.2. Memory Address Map ................................................................................................................. 89 3.1.3. BIOS MEMORY........................................................................................................................... 90 3.2. PCI Interface ...................................................................................................................................... 90 3.2.1. TRANSACTION TERMINATION ................................................................................................. 90 3.2.2. PARITY ...
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REVISION HISTORY Revision Date May 1996 -001 April 1997 -002 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document ...
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AND 82371SB (PIIX3) 8 ...
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SIGNAL DESCRIPTION This section contains a detailed description of each signal. The signals are arranged in functional groups according to their interface. Note that the ’#’ symbol at the end of a signal name indicates that the active, or ...
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AND 82371SB (PIIX3) Signal Name Type TRDY# I/O TARGET READY: Asserted when the target is ready for a data transfer. (s/t/s) IRDY# I/O INITIATOR READY: Asserted when the initiator is ready for a data (s/t/s) transfer. STOP# I/O ...
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Signal Name Type MIRQ0/IRQ0 I/O MOTHERBOARD DEVICE INTERRUPT REQUEST: The MIRQx (PIIX3 Only) signals can be internally connected to interrupts IRQ[15,14,12:9,7:3]. Each MIRQx line has a separate Route Control Register. If MIRQx and MIRQ[1:0] I PIRQx# are steered to the ...
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AND 82371SB (PIIX3) Signal Name Type IORDY I IO CHANNEL READY: This input signal is directly driven by the corresponding signal two IDE connectors (primary and secondary). SOE# O SYSTEM ADDRESS TRANSCEIVER OUTPUT ENABLE: This ...
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ISA Interface Signals Signal Name Type BALE O BUS ADDRESS LATCH ENABLE: BALE is an active high signal asserted by the PIIX/PIIX3 to indicate that the address (SA[19:0], LA[23:17]) and SBHE# signal lines are valid. AEN O ADDRESS ENABLE: ...
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AND 82371SB (PIIX3) Signal Name Type SA[7:0], I/O SYSTEM ADDRESS BUS: These bi-directional address lines define the SA[19:8]/ I/O selection with the granularity of one byte within the one-Mbyte section of DD[11:0] I/O memory defined by the LA[23:17] ...
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DMA Signals Signal Name Type DREQ I DMA REQUEST: The DREQ lines are used to request DMA service from [7:5,3:0] the PIIX/PIIX3 ’s DMA controller or for a 16-bit master to gain control of the ISA expansion bus. The ...
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AND 82371SB (PIIX3) 1.7. Interrupt Controller Signals Signal Name Type IRQ[15,14, I INTERRUPT REQUEST: The IRQ signals provide both system board 11:9, 7:3,1] components and ISA Bus I/O devices with a mechanism for asynchronously interrupting the CPU. The ...
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X-Bus Signals Signal Name Type XDIR# O X-BUS DIRECTION: XDIR# is tied directly to the direction control of a 74F245 that buffers the X-Bus data (XD[7:0]). XDIR# is asserted for all I/O read cycles, regardless if the accesses are ...
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AND 82371SB (PIIX3) Signal Name Type FERR# I NUMERIC COPROCESSOR ERROR: This signal is tied to the coprocessor error signal on the CPU. IGNNE# is only used if the PIIX/PIIX3 coprocessor error reporting function is enabled in the ...
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Universal Serial Bus Signals (PIIX3 Only) Signal Name Type USBCLK I UNIVERSAL SERIAL BUS CLOCK. This signal clocks the universial serial bus clock. USBP0+ I/O UNIVERSAL SERIAL BUS PORT 0. These signals are the differential data USBP0- pair for ...
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AND 82371SB (PIIX3) 1.13. Test Signals Signal Name Type TESTIN#/ I TEST INPUT: This signal has two functions, depending on the I programming of the APIC Chip Select bit (XBCS Register). See the APIC APICREQ# SIgnal Description for ...
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Signal State During Reset Table 1 shows the state of all PIIX/PIIX3 output and bi-directional signals during a hard reset. A hard reset is initiated when PWROK is asserted or by programming a hard reset through the RC Register. ...
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AND 82371SB (PIIX3) 2.0. REGISTER DESCRIPTION The 82371FB PIIX internal registers are organized into five groups—PCI Configuration Registers (function 0), PCI Configuration Registers (function 1), ISA-Compatible Registers, PCI Bus Master IDE Registers, and System Power Management Registers. These ...
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ISA Compatible Registers The ISA-Compatible registers (e.g., DMA registers, timer/counter registers, X-Bus registers, and NMI registers) are accessed through normal I/O space. Except for the DMA registers, the PIIX/PIIX3 positively decodes accesses to the ISA-Compatible registers. The PIIX/PIIX3 subtractively decodes ...
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AND 82371SB (PIIX3) Configuration Mnemonic Offset 0F–4Bh — 4Ch IORT 4Dh — 4Eh (PIIX) XBCS 4E–4Fh (PIIX3) 4F–5Fh (PIIX) — 50–5Fh (PIIX3) 60–63h PIRQRC[A:D] 64–68h — 69h TOM 6A–6Bh MSTAT 6C–6Fh — 70h MBIRQ0 71h MBIRQ1 — 72–75h ...
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Configuration Mnemonic Offset ACh CTLTMR Clock Scale STPCLK# Low Timer ADh — Reserved AEh CTHTMR Clock Scale STPCLK# High Timer AF–FFh — Reserved Table 3. PCI Configuration Registers—Function 1 (IDE Interface) Configuration Mnemonic Offset 00–01h VID Vendor Identification 02–03h DID ...
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AND 82371SB (PIIX3) Table 4. PCI Configuration Registers—Function 2 (Universial Serial Bus Interface) (PIIX3 Only) Configuration Mnemonic Offset 00–01h VID 02–03h DID 04–05h PCICMD 06–07h PCISTS 08h RID 09 0Bh CLASSC 0Ch — 0Dh LATTMR 0Eh HEDT 0F–19h ...
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Table 5. ISA-Compatible and Power Management Registers Address Address (bits) (hex) FEDC BA98 7654 0000h 3 0000 0000 000x 0001h 3 0000 0000 000x 0002h 3 0000 0000 000x 0003h 3 0000 0000 000x 0004h 3 0000 0000 000x 0005h ...
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AND 82371SB (PIIX3) Address Address (bits) (hex) FEDC BA98 7654 0070h 1 0000 0000 0111 0080h 2,3 0000 0000 100x 0081h 3 0000 0000 100x 0082h 3 0000 0000 1000 0083h 3 0000 0000 100x 0084h 2,3 0000 ...
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Address Address (bits) (hex) FEDC BA98 7654 00CAh 3 0000 0000 1100 00CCh 3 0000 0000 1100 00CEh 3 0000 0000 1100 00D0h 3 0000 0000 1101 00D2h 3 0000 0000 1101 00D4h 3 0000 0000 1101 00D6h 3 0000 ...
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AND 82371SB (PIIX3) Table 6. PCI Bus Master IDE I/O Registers Offset Mnemonic From Base Address 00h BMICP Bus Master IDE Command (primary) 01h — Reserved 02h BMISP Bus Master IDE Status (primary) 03h — Reserved 04–07h BMIDTPP ...
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PCI Configuration Registers—PCI To ISA Bridge (Function 0) 2.2.1. VID—VENDOR IDENTIFICATION REGISTER (Function 0) Address Offset: 00–01h Default Value: 8086h Attribute: Read Only The VID Register contains the vendor identification number. This register, along with the Device Identification Register, ...
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AND 82371SB (PIIX3) Bit 2 Bus Master Enable (BME). (Not Implemented) The PIIX/PIIX3 does not support disabling its bus master capability. This bit is hardwired Memory Access Enable (MAE). (Not Implemented) The PIIX/PIIX3 does not ...
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RID—REVISION IDENTIFICATION REGISTER (Function 0) Address Offset: 08h Default Value: Refer to applicable specification update document Attribute: Read Only This 8 bit register contains device stepping information. Writes to this register have no effect. Bit 7:0 Revision ID Byte. ...
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AND 82371SB (PIIX3) increase the delay in increments of SYSCLKs. No additional delay is inserted for back-to-back I/O "sub cycles" generated as a result of byte assembly or disassembly. This register defaults to 8 and 16-bit recovery enabled ...
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Bit 15:9 PIIX3: Reserved. 8 PIIX3: APIC Chip Select. When enabled (bit 8=1), APICCS# is asserted for PCI memory accesses to the programmable IOAPIC region. This cycle is forwarded to the ISA bus. The default IOAPIC addresses are memory FEC0_0000h ...
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AND 82371SB (PIIX3) 2.2.10. PIRQRC[A:D]—PIRQx ROUTE CONTROL REGISTERS (Function 0) Address Offset : 60h (PIRQRCA#)—63h (PIRQRCD#) Default Value: 80h Attribute: R/W These registers control the routing of the PIRQ[A:D]# signals to the IRQ inputs of the interrupt controller. ...
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Bit 3 ISA/DMA Lower BIOS Forwarding Enable. 1=Enable (forwarded to PCI, if XBCS Register bit 6=0); 0=Disable (contained to ISA). Note that If the XBCS Register bit 6=1, ISA/DMA accesses in this region are always contained to ISA. PIIX: Reserved ...
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AND 82371SB (PIIX3) Bit 6 PIIX: Reserved. PIIX3: EXTSMI# Mode Enable (ESMIME) used to enable a special SERR# handling protocol between the host-to-PCI bridge and the PIIX3. When ESMIME is enabled, the operating mode of the EXTSMI# signal ...
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Bit 0 PIIX: ISA Clock Divisor Status RO. This bit reports the strapping option on the SYSCLK signal. 1=clock divisor of 3 (PCICLK=25 MHz). 0=Clock divisor of 4 (PCICLK=33 MHz). Note that, for PCICLK=30 MHz, a clock divisor of 4 ...
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AND 82371SB (PIIX3) 2.2.14. MBDMA[1:0]—MOTHERBOARD DEVICE DMA CONTROL REGISTERS (Function 0) Address Offset : 76h—MBDMA0#; 77h—MBDMA1# Default Value: 0Ch Attribute: R/W For both the PIIX and PIIX3, these registers enable/disable a type F DMA transfer (3 SYSCLK) for ...
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PCS# signal asserted. The PCS# signal is never asserted for ISA bus masters access. Bit 15:2 PCS Address (PCSADDR). This field defines a 16-bit I/O space address (4 byte range) that causes the PCS# ...
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AND 82371SB (PIIX3) 2.2.17. DLC—DETERMINISTIC LATENCY CONTROL REGISTER (Function 0) (PIIX3 Only) Address Offset: 82h Default Value: 00h Attribute: Read/Write This register enables/disables the Delayed Transaction and Passive Release functions, respectively. When enabled, these functions make the PIIX3 ...
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SMICNTL—SMI CONTROL REGISTER (Function 0) Address Offset: A0h Default Value: 08h Attribute: Read/Write The SMICNTL Register provides Fast Off Timer control, STPCLK# enable/disable, and CPU clock scaling. This register also enables/disables the system management interrupt (SMI). Bit 7:5 Reserved ...
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AND 82371SB (PIIX3) Bit 7 APMC Write SMI Enable. 1=Enable; 0=Disable. 6 EXTSMI# SMI Enable. 1=Enable; 0=Disable. 5 Fast Off Timer SMI Enable. 1=Enable; 0=Disable. When enabled, the timer generates an SMI when it decrements to zero. 4 ...
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FTMR—FAST OFF TIMER REGISTER (Function 0) Address Offset: A8h Default Value: 0Fh Attribute: Read/Write The Fast Off Timer indicates (through an SMI) that the system has been idle for a pre-programmed period of time. When the timer expires, an ...
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AND 82371SB (PIIX3) Bit 15:9 Reserved 8 PIIX: Reserved. PIIX3: Legacy USB SMI Status (RLUSB). This bit is set indicate that the USB Legacy Keyboard logic caused an SMI. Software sets this bit to a ...
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CTHTMR—CLOCK SCALE STPCLK# HIGH TIMER (Function 0) Address Offset: AEh Default Value: 00h Attribute: Read/Write The value in this register defines the duration of the STPCLK# negated period when bit 2 in the SMICNTL Register is set to 1. ...
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AND 82371SB (PIIX3) 2.3.3. PCICMD—COMMAND REGISTER (Function 1) Address Offset: 04–05h Default Value: 0000h Attribute: Read/Write The PCICMD Register controls access to the I/O space registers. Bit 15:10 Reserved. Read 0. 9 Fast Back to Back Enable (FBE). ...
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Bit 8 Data Parity Detected (DPD). (Not Implemented) Read Fast Back to back Capable (FBC)—RO. Hardwired to 1. This bit indicates to the PCI Master that PIIX target, is capable of accepting fast back-to-back transactions. ...
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AND 82371SB (PIIX3) Bit 7:4 Master Latency Timer Count Value. PIIX-initiated PCI burst cycles can last indefinitely, as long as PHLDA# remains active. However, if PHLDA# is negated after the burst cycle is initiated, PIIX/PIIX3 limits the burst ...
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IDETIM—IDE TIMING REGISTER (Function 1) Address Offset: Primary Channel=40–41h; Secondary Channel=42–43h Default Value: 0000h Attribute: Read / Write Only This register controls the PIIX's IDE interface and selects the timing characteristics of the PCI Local Bus IDE cycle. Note ...
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AND 82371SB (PIIX3) Bit 4 Fast Timing Bank Drive Select 1 (TIME1). When TIME1=0, accesses to the data port of the enabled I/O address range use the 16-bit compatible timing PCI local bus path. When TIME1=1 and the ...
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Bit 5:4 Secondary Drive 1 Recovery Time (SRTC1). This field selects the minimum number of clocks between the last IORDY# sample point and the DIOx# strobe of the next cycle for the slave drive on the secondary channel. Bits[5:4] 00 ...
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AND 82371SB (PIIX3) 2.4.2. DID DEVICE IDENTIFICATION REGISTER (Function 2) (PIIX3) Address Offset: 02 03h Default Value: 7020h Attribute: Read Only The DID Register contains the device identification number. This register, along with the VID Register, define the ...
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DS DEVICE STATUS REGISTER (Function 2) (PIIX3) Address Offset: 06 07h Default Value: 0280h Attribute: Read/Write DSR is a 16-bit status register that reports the occurrence of a PCI master-abort by the USB HC module or a PCI target-abort ...
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AND 82371SB (PIIX3) 2.4.6. CLASSC CLASS CODE REGISTER (Function 2) (PIIX3) Address Offset: 09 0Bh Default Value: 010180h Attribute: Read Only This register contains the device programming interface information related to the Sub-Class Code and Base Class Code ...
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HEDT HEADER TYPE REGISTER (Function 2) (PIIX3) Address Offset: 0Eh Default Value: 00h Attribute: Read Only This register identifies the Serial Bus module as a single function device. Bit 7:0 Device Type (DEVICET). 00. Multi-function device capability for PIIX/PIIX3 ...
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AND 82371SB (PIIX3) 2.4.11. INTRP INTERRUPT PIN (Function 2) (PIIX3) Address Offset: 3Dh Default Value: 04h Attribute: Read only This register indicates which PCI interrupt pin is used for the Universal Serial Bus module interrupt. The USB interrupt ...
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LEGSUP LEGACY SUPPORT REGISTER (FUNCTION 2) (PIIX3) PCI Address Offset: C0 C1h Default: 2000h Attribute: Read/Write Clear This register provides control and status capability for the legacy keyboard and mouse functions. Bit 15 End OF A20GATE Pass-through Status (A20PTS) ...
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AND 82371SB (PIIX3) Bit 5 A20Gate Pass-through Enable (A20PTEN) R/W. 1=Enable A20GATE pass-through sequence. 0=Disable (default). When enabled, the logic will pass-through the following A20GATE command sequence: Cycle Address Data Write 64h D1h Write 60h xxh Read 64h ...
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ISA-Compatible Registers The ISA-Compatible registers contain the DMA, timer/counter, and interrupt registers. This group also contains the X-Bus, coprocessor, NMI, and reset registers. 2.5.1. DMA REGISTERS The PIIX/PIIX3 contains DMA circuitry that incorporates the functionality of two 82C37 DMA ...
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AND 82371SB (PIIX3) Bit 5 Address Increment/Decrement Select. 0=Increment; 1=Decrement. 4 Autoinitialize Enable. 1=Enable; 0=Disable. 3:2 DMA Transfer Type. When Bits [7:6]=11, the transfer type bits are irrelevant. Bits[3:2] Transfer Type 00 Verify transfer 01 Write transfer 10 ...
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Mask Register—Write Single Mask Bit I/O Address: Channels 0-3—0Ah; Channels 4-7—0D4h Default Value: Bits[1:0]=undefined; Bit 2=1; Bits[7:3]=0 (CPURST or a Master Clear) Attribute: Write Only A channel's mask bit is automatically set when the Current Byte/Word Count Register reaches ...
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AND 82371SB (PIIX3) 2.5.1.6. DS—DMA Status Register I/O Address: Channels 0-3—08h; Channels 4-7—0D0h Default Value: 00h Attribute: Read Only Each DMA controller has a read-only DMA Status Register that indicates which channels have reached terminal count and which ...
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DMA Base And Current Byte/Word Count Registers (Compatible Segment) I/O Address: DMA Channel 0—001h DMA Channel 1—003h DMA Channel 2—005h DMA Channel 3—007h Default Value: XXXXh (CPURST or Master Clear) Attribute: Read/Write This register determines the number of transfers ...
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AND 82371SB (PIIX3) 2.5.1.10. DMA Clear Byte Pointer Register I/O Address: Channels 0-3—00Ch; Channels 4-7—0D8h Default Value: All bits undefined Attribute: Write Only Writing to this register executes the Clear Byte Pointer Command. This command is executed prior ...
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After writing the control word, a new count can be written at any time. The new value takes effect according to the programmed mode. Bit 7:6 Counter Select. The Read Back Command is selected when bits[7:6] ...
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AND 82371SB (PIIX3) Bit 3 Counter 2 Select. When bit 3=1, Counter 2 is selected for the latch command selected with bits 4 and 5. When bit 3=0, status and/or count will not be latched. 2 Counter 1 ...
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Bit 6 Count Register Status. This bit indicates when the last count written to the Count Register (CR) has been loaded into the counting element (CE). 0=Count has been transferred from and is available for reading. 1=Count ...
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AND 82371SB (PIIX3) 2.5.3.1. ICW1—Initialization Command Word 1 Register I/O Address: INT CNTRL-1—020h; INT CNTRL-2—0A0h Default Value: All bits undefined Attribute: Write Only A write to Initialization Command Word 1 starts the interrupt controller initialization sequence. Addresses 020h ...
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ICW3—Initialization Command Word 3 Register I/O Address: INT CNTRL-1—021h Default Value: All bits undefined Attribute: Write Only The meaning of ICW3 differs between CNTRL-1 and CNTRL-2. On CNTRL-1, the master controller, ICW3 indicates which CNTRL-1 IRQ line physically connects ...
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AND 82371SB (PIIX3) 2.5.3.6. OCW1—Operational Control Word 1 Register I/O Address: INT CNTRL-1—021h; INT CNTRL-2—0A1h Default Value: 00h Attribute: Read/Write OCW1 sets and clears the mask bits in the Interrupt Mask Register (IMR). Each interrupt request line may ...
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Bit 2:0 Interrupt Level Select (L2, L1, L0). L2, L1, and L0 determine the interrupt level acted upon when the SL bit is active (bit 6). When the SL bit is inactive, bits [2:0] do not have a defined function; ...
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AND 82371SB (PIIX3) 2.5.3.9. ELCR1—Edge/Level Triggered Register I/O Address: INT CNTRL-1—4D0h Default Value: 00h Attribute: Read/Write ELCR1 register allows IRQ3 - IRQ7 to be edge or level programmable on an interrupt by interrupt basis. IRQ0, IRQ1 and IRQ2 ...
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X-BUS, COPROCESSOR, and RESET REGISTERS 2.5.4.1. Reset X-Bus IRQ12 And IRQ1 Register I/O Address: 60h Default Value: N/A Attribute: Read only This register clears the mouse interrupt function and the keyboard interrupt (IRQ1). Reads to this address are monitored ...
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AND 82371SB (PIIX3) Bit 1 System Reset (SRST). This bit is used in conjunction with bit 2 in this register to initiate a hard reset. When SRST =1, the PIIX/PIIX3 initiates a hard reset to the CPU when ...
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Bit 4 Refresh Cycle Toggle—RO. The Refresh Cycle Toggle signal toggles from either following every refresh cycle. When writing to port 061h, bit 4 must IOCHK# NMI Enable—R/W. 1=Clear ...
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AND 82371SB (PIIX3) 2.6.2. APMS—ADVANCED POWER MANAGEMENT STATUS PORT I/O Address: 0B3h Default Value: 00h Attribute: Read/Write This register passes status information between the OS and the SMI handler. The PIIX/PIIX3 operation is not effected by the data ...
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BMISTA—BUS MASTER IDE STATUS REGISTER Address Offset: Primary Channel—Base + 02h; Secondary Channel—Base + 0Ah Default Value: 00h Attribute: Read/Write Clear This register provides status information about the IDE device and state of the IDE DMA transfer. Table 8 ...
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AND 82371SB (PIIX3) Bit 2 Bit Error condition. If the IDE DMA Error bit is 1, there is a problem transferring data to/from memory. Specifics of the error have to be determined using bus-specific information. ...
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Bit 5 Software Debug (SWDBG). 1=Debug mode. 0=Normal Mode Debug mode, the Host Controller clears the Run/Stop bit after the completion of each USB transaction. The next transaction is executed when software sets the Run/Stop bit back to ...
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AND 82371SB (PIIX3) Table 9. Run/Stop, Debug Bit Interaction SWDBG Run/Stop (Bit 5) (Bit executing a command, the Host Controller completes the command and then stops. The 1.0 ms frame counter is reset and ...
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Bit 3 PCI Bus Error. The Host Controller sets this bit to 1 when a serious error occurs during a PCI access involving the Host Controller module. PCI conditions that set this bit to 1 include PCI Master Abort and ...
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AND 82371SB (PIIX3) select a particular entry in the Frame List during schedule execution. (Frame List is one of the data structures located in system memory that is processed by the Host Controller.) This register must be written ...
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This register is reset upon a Host Controller Reset or Global Reset. Software must maintain a copy of its value for reprogramming if necessary. Bit 7 Reserved. 6:0 SOF Timing Value. ...
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AND 82371SB (PIIX3) Bit 15:13 Reserved. Must written as 0s when writing this register. 12 Suspend R/W. 1=Port in suspend state. 0=Port not in supsend state. This bit should not be written global suspend ...
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Bit 1 Connect Status Change R/WC. 1=Change in Current Connect Status. 0=No change. Indicates a change has occurred in the port’s Current Connect Status (see bit 0). The hub device sets this bit for any changes to the port device ...
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AND 82371SB (PIIX3) Table 10. Behavior During Resume When Host Not In Global Suspend State Port Status and Signaled Port Response Signaling Type Port disabled and connect PORTSC Connect Status and received Connect Status Change bits are set. ...
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FUNCTIONAL DESCRIPTION This section describes each of the major functions on the PIIX/PIIX3 including the memory and I/O address map, DMA controller, interrupt controller, timer/counter, and power management. The PCI, ISA, X-Bus, and IDE interfaces. 3.1. Memory and I/O ...
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AND 82371SB (PIIX3) NOTES: 1. Except accesses to programmed memory hole. 2. Forward to main memory if bit 6=0 in the XBCS Register and bit 3=1 in the TOM Register. 3. Forward to main memory if bit 1=0 ...
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PIIX/PIIX3 As a Master—Response to Target-Initiated Termination master, the PIIX/PIIX3 responds in one of three ways to a target-termination PIIX/PIIX3 As a Target—Target-Initiated Termination: The PIIX/PIIX3 supports three forms of Target- initiated Termination Disconnect, Retry, Target Abort. 3.2.2. ...
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AND 82371SB (PIIX3) 3.3. ISA Interface The PIIX/PIIX3 incorporates a fully ISA Bus compatible master and slave interface. The PIIX/PIIX3 directly drives five ISA slots without external data buffers. External transceivers are used on the SA[19:8] and SBHE# ...
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DMA Controller The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven independently programmable channels (Channels 0-3 and Channels 5-7). DMA Channel 4 is used to cascade the two controllers and defaults to cascade mode in ...
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AND 82371SB (PIIX3) 1. For type F timing mode DMA transfers, the channel must be programmed with a memory range that will be forwarded to PCI. This means that if BIOS detects that ISA memory is used in ...
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PCI Local Bus IDE The PIIX/PIIX3 integrates a high performance interface from PCI to IDE. This interface is capable of accelerated PIO data transfers as well as acting as a PCI Bus master on behalf of an IDE DMA ...
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AND 82371SB (PIIX3) Two connectors (primary and secondary) and two drives per connector (master and slave) are supported as shown in Figure 4. PIIX/PIIX3 Figure 4. IDE Connector and Drive Nomenclature 3.5.1. ATA REGISTER BLOCK DECODE The IDE ...
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Table 13. IDE Legacy I/O port definition: COMMAND BLOCK (CS1x# chip select) IO Offset Register Function (Read / Write) 00h Data 01h Error/Features 02h Sector Count 03h Sector Number 04h Cylinder Low 05h Cylinder High 06h Drive/Head 07h Status/Command The ...
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AND 82371SB (PIIX3) 3.5.2.1. Back-To-Back PIO IDE Transactions IDE data port transaction latency consists of startup latency, cycle latency, and shutdown latency. Cycle latency consists of the I/O strobe assertion length and recovery time. Recovery time is provided ...
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Each PRD entry is 8 bytes in length. PRDs must be aligned on 64-Kbyte boundaries. The first 4 bytes specify the byte address of a physical memory region. The next two bytes specify the count of the region in bytes ...
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AND 82371SB (PIIX3) Note that the IRQ14 signal must be used to signal interrupts for the primary channel in bus master mode; MIRQ0 must be used for the secondary channel. When the last data transfer for a region ...
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A low speed length babble occurring in a frame followed by a subsequent clearing of the Run/Stop bit will cause the host controller to lock up from which it can only be restarted by a hardware reset. A length babble ...
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AND 82371SB (PIIX3) System Software Hardware USB Device Figure 6. USB System Conceptual View 3.7. Interval Timer The PIIX/PIIX3 contains three counters that are equivalent to those found in the 82C54 programmable interval timer. The three counters are ...
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Counter 1, Refresh Request Signal This counter provides the refresh request signal and is typically programmed for mode 2 operation. The counter negates refresh request for one counter period (838 ns) during each count cycle. The initial count value is ...
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AND 82371SB (PIIX3) 3.8.1. PROGRAMMING THE ICWs/OCWs The Interrupt Controller accepts two types of command words generated by the CPU or bus master: 1. Initialization Command Words (ICWs): Before normal operation can begin, each Interrupt Controller in the ...
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One or more PIRQx# lines can be routed to the same IRQx input. If interrupt steering is not required, the Route Registers can be programmed to disable steering. For the PIIX3, the Universal Serial Bus (USB) Module interrupt is ...
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AND 82371SB (PIIX3) APICCS# is generated when the PCI memory cycle address matches the APIC’s programmed address and the APICCS# function is enabled in the XBCS Register. The APIC address can be relocated by programming the APIC Base ...
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Pentium® uni-processor or dual processor with IO-APIC: Affects systems which use Local APIC in Virtual Wire mode of operation. This can include Intel 430HX PCIset based systems with PIIX3 and an IO-APIC. See recommendations below. Pentium® Pro (uni-processor or dual ...
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AND 82371SB (PIIX3) 3.12. Power Management The PIIX/PIIX3 has extensive power management capability permitting a system to operate in a low power state without being powered down typical desktop personal computer there are two states — ...
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SMM MODE SMM mode is invoked by asserting the SMI# signal to the CPU. The PIIX/PIIX3 provides a variety of programmable events that can generate an SMI. When the CPU receives an SMI, it enters SMM mode and executes ...
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AND 82371SB (PIIX3) The two APM Registers are located in normal I/O space. The PIIX/PIIX3 subtractively decodes PCI accesses to these registers and forwards the accesses to the ISA Bus. The APM Registers are not accessible by ISA ...
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Some PCI devices may drive 3.3V friendly signals directly to 3.3V devices that are not 5V tolerant. If such signals are powered from the 5V supply they must be driven low when PCIRST# is asserted. Some of these signals may ...
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AND 82371SB (PIIX3) 4.0. PINOUT AND PACKAGE INFORMATION 4.1. Pinout 1 VSS 2 VSS 3 SERR# 4 IRQ1 5 IRQ8# IOCHK SD7 SD6 8 9 SD5 10 IRQ9 11 SD4 12 DREQ2 13 SD3 14 SD2 ...
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Table 15. Alphabetical Pin Assignment Name Pin # Type AD0 206 I/O AD1 205 I/O AD2 204 I/O AD4 202 I/O AD5 201 I/O AD6 200 I/O AD7 199 I/O AD8 197 I/O AD9 194 I/O AD10 193 I/O AD11 ...
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AND 82371SB (PIIX3) Name Pin # Type DD13 37 I/O DD14 (PIIX) 36 I/O DD14/APICCS# (PIIX3) DD15/PCS# 35 I/O DDAK0# 115 O DDAK1# 116 O DDRQ0 108 I DDRQ1 111 I DEVSEL# 184 I/O DIOR# 113 O DIOW# ...
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Name Pin # Type MIRQ0/IRQ0 147 O MIRQ1 (PIIX) 146 I/O USBCLK (PIIX3) NMI 135 O OSC 136 I PAR 186 O PCICLK 132 I PCIRST# (PIIX) 128 O PICRST#/ APICACK# (PIIX3) PHLDA# 110 I PHOLD# 109 O PIRQA# (PIIX) ...
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AND 82371SB (PIIX3) Name Pin # Type VCC 54 V VCC 78 V VCC 103 V VCC 104 V VCC (PIIX) 130 V VCC3 (PIIX3) VCC 157 V VCC 158 V VCC 169 V VCC 183 V VCC ...
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PACKAGE DIMENSIONS D D1 156 157 208 1 * Note* Height Measurements same as Width Measurements Figure 12. 208 Pin Quad Flat Pack (QFP) Dimensions Table 16. 208 Pin Quad Flat Pack (QFP) Dimensions Symbol Description A Seating Height ...
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AND 82371SB (PIIX3) 5.0. TESTABILITY (PIIX/PIIX3) 5.1. Test Mode Description The test modes are decoded from the IRQ inputs (IRQ and qualified with the TESTIN# pin. Test mode selection is asynchronous. These signals need to ...
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Table 18. Perform NAND Tree Test (Pins Driven To 0) Pin # 81 83 126 Beginning with MDRQ and working counter-clockwise around the chip, each pin can be toggled and a resulting toggle observed on DACK1# or XDIR. The DACK1# ...
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AND 82371SB (PIIX3) Table 19. NAND Tree Pin # Pin Name Notes 198 C/BE0# 199 AD7 200 AD6 201 AD5 202 AD4 203 AD3 204 AD2 205 AD1 206 AD0 3 SERR# 4 IRQ1 Inverted input signal 5 ...
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Table 19. NAND Tree Pin # Pin Name Notes 74 LA22 75 IRQ11 Inverted input signal 76 LA21 77 IRQ12 Inverted input signal 80 LA20 81 IRQ15 Inverted input signal 82 LA19 83 IRQ14 Inverted input signal 84 LA18 85 ...
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AND 82371SB (PIIX3) Figure schematic of the NAND tree circuitry. MDRQ1 MDRQ0 RSTDRV DREQ1 KBCCS# XOE# Figure 13. NAND Tree Circuitry NAND Tree Timing Requirements Allow 500 ns for the input signals to propagate to ...