K4T51163QB-GCCC Samsung, K4T51163QB-GCCC Datasheet
K4T51163QB-GCCC
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K4T51163QB-GCCC Summary of contents
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... ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply ...
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B-die DDR2 SDRAM Contents 0. Ordering Information 1. Key Feature 2. Package Pinout/Mechanical Dimension & Addressing 2.1 Package Pinout & Mechanical Dimension 2.2 Input/Output Function Description 2.3 Addressing 3. Absolute Maximum Rating 4. AC & DC Operating Conditions & ...
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... All of Lead-free products are compliant for RoHS Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “Samsung’s DDR2 SDRAM Device Operation & Timing Diagram” DDR2-400 3-3-3 K4T51043QB-GCCC K4T51043QB-ZCCC K4T51083QB-GCCC K4T51083QB-ZCCC K4T51163QB-GCCC K4T51163QB-ZCCC DDR2-533 4-4-4 DDR2-400 3-3 ...
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B-die DDR2 SDRAM 2. Package Pinout/Mechanical Dimension & Addressing 2.1 Package Pinout x4 package pinout (Top View) : 60ball FBGA Package 1 VDD NC VDDQ NC VDDL NC VSS VDD Notes: 1. Pin B3 has identical capacitance as pin ...
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B-die DDR2 SDRAM x8 package pinout (Top View) : 60ball FBGA Package 1 VDD DQ6 VDDQ DQ4 VDDL NC VSS VDD Notes: 1. Pins B3 and A2 have identical capacitance as pins B7 and A8. 2. For a read, ...
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B-die DDR2 SDRAM x16 package pinout (Top View) : 84ball FBGA Package 1 VDD UDQ6 VSSQ VDDQ UDQ1 UDQ4 VSSQ VDD LDQ6 VSSQ VDDQ LDQ4 VSSQ VDDL NC VSS VDD Note : 1. VDDL and VSSDL are power and ...
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B-die DDR2 SDRAM FBGA Package Dimension(x4/x8 60- 0.45r ‡ 0.05 ‡0.2 #A1 11. INDEX MARK 6.40 0.80 1. ...
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B-die DDR2 SDRAM FBGA Package Dimension(x16 84- 0.45r ‡ 0.05 ‡0.2 #A1 11. INDEX MARK 6.40 ...
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B-die DDR2 SDRAM 2.2 Input/Output Functional Description Symbol Type Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of CK, CK Input the positive edge of CK and negative ...
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B-die DDR2 SDRAM 2.3 512Mb Addressing Configuration # of Bank Bank Address Auto precharge Row Address Column Address * Reference information: The following tables are address mapping information for other densities. 256Mb Configuration # of Bank Bank Address Auto ...
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B-die DDR2 SDRAM 3. Absolute Maximum DC Ratings Symbol Parameter VDD Voltage on VDD pin relative to Vss VDDQ Voltage on VDDQ pin relative to Vss VDDL Voltage on VDDL pin relative to Vss V V Voltage on any ...
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B-die DDR2 SDRAM Operating Temperature Condition Symbol Parameter TOPER Operating Temperature 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard ...
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B-die DDR2 SDRAM Differential input AC logic Level Symbol Parameter V ID(AC) AC differential input voltage V IX(AC) AC differential cross point voltage Notes (AC) specifies the input differential voltage |V ID and V is the complementary ...
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B-die DDR2 SDRAM OCD default characteristics Description Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Notes: 1. Absolute Specifications (0°C d d+95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V) T ...
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B-die DDR2 SDRAM IDD Specification Parameters and Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes Symbol Operating one bank active-precharge current CK(IDD ...
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B-die DDR2 SDRAM For purposes of IDD testing, the following parameters are utilized Parameter CL(IDD) t RCD(IDD) t RC(IDD) t RRD(IDD)-x4/x8 t RRD(IDD)-x16 t CK(IDD) t RASmin(IDD) t RP(IDD) t RFC(IDD) Detailed IDD7 The detailed timings are shown below ...
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... CC(DDR2-400@CL=3) 100 95 110 100 200 145 180 145 195 185 5.5 5.5 275 270 32Mx16(K4T51163QB) CC(DDR2-400@CL=3) 120 115 145 125 230 185 205 170 195 185 5.5 5.5 390 375 Page ...
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B-die DDR2 SDRAM Input/Output capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, ...
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B-die DDR2 SDRAM Timing Parameters by Speed Grade (Refer to notes for informations related to this table at the bottom) Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width ...
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B-die DDR2 SDRAM Parameter CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down ...
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B-die DDR2 SDRAM General notes, which may apply for all AC parameters 1. Slew Rate Measurement Levels a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for ...
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B-die DDR2 SDRAM 4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized ...
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B-die DDR2 SDRAM Specific Notes for dedicated AC parameters 9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is ...
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B-die DDR2 SDRAM 18. tIS and tIH (input setup and hold) derating. 2.0 V/ns 'tIS 4.0 +187 3.5 +179 3.0 +167 2.5 +150 2.0 +125 1.5 +83 1.0 0 0.9 -11 Command/ Address Slew 0.8 -25 rate(V/ns) 0.7 -43 ...
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B-die DDR2 SDRAM 19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. MIN ( tCL, tCH) ...
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B-die DDR2 SDRAM tHZ tRPST end point T1 tHZ,tRPST end point = 2*T1-T2 29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V tial data strobe crosspoint for a ...
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B-die DDR2 SDRAM 31. Input waveform timing is referenced from the input signal crossing at the V device under test. 32. Input waveform timing is referenced from the input signal crossing at the V device under test ...
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B-die DDR2 SDRAM Revision History Version 1.0 (Jan. 2004) - Initial Release Version 1.1 (Jun. 2004) - Added Lead-Free part number in ordering information. - Changed IDD2P - Corrected Typo Version 1.2 (Jan. 2005) - Removed DDR2-667 SDRAM at ...