HY5DS573222FP-33 Hynix Semiconductor, HY5DS573222FP-33 Datasheet
HY5DS573222FP-33
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HY5DS573222FP-33 Summary of contents
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... HY5DS573222F(P) 256M(8Mx32) GDDR SDRAM HY5DS573222F(P) This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Feb. 2005 1 ...
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Revision History No. 0.1 Defined Target Spec. 0.2 Supports Lead free parts for each speed grade 0.3 CL, AC parameter, IDD5 change 0.4 CL, tCK_max, tRAS, tDAL change & Comment of DLL_off condition 1) Changed IDD & VDD_max 0.5 2) ...
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... Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials. We'll add "P" character after "F" for lead free product. For example, the part number of 300Mhz Lead free product is HY5DS573222FP-33. Rev. 1.0 / Feb. 2005 • ...
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PIN CONFIGURATION (Top View) ROW and COLUMN ADDRESS TABLE Organization Row Address Column Address Bank Address Auto Precharge Flag Rev. 1.0 / Feb. 2005 Items 8Mx32 4banks A0 ~ A11 A0 ~ A7, A9 BA0, BA1 ...
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PIN DESCRIPTION PIN TYPE CK, /CK Input CKE Input /CS Input BA0, BA1 Input A0 ~ A11 Input /RAS, /CAS, /WE Input DM0 ~ DM3 Input DQS0 ~ DQS3 I/O DQ0 ~ DQ31 I Supply ...
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FUNCTIONAL BLOCK DIAGRAM 4Banks x 2Mbit x 32 I/O Double Data Rate Synchronous DRAM CLK /CLK CKE /CS Command Decoder /RAS /CAS /WE DM(0~3) Mode Register A0-11 Address Buffer BA0,BA1 Rev. 1.0 / Feb. 2005 Write Data Register 2-bit Prefetch ...
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SIMPLIFIED COMMAND TRUTH TABLE Command CKEn-1 Extended Mode Register Set H Mode Register Set H Device Deselect H No Operation Bank Active H Read H Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank ...
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WRITE MASK TRUTH TABLE Function CKEn-1 Data Write H Data-In Mask H Note : 1. Write Mask command masks burst write data with reference to DQS(0~3) and it is not related with read data. 2. DM0 corresponds to the data ...
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OPERATION COMMAND TRUTH TABLE - I Current /CS /RAS /CAS State IDLE ROW L ...
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OPERATION COMMAND TRUTH TABLE - II Current /CS /RAS /CAS State WRITE READ WITH L H AUTOPRE CHARGE ...
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OPERATION COMMAND TRUTH TABLE - III Current /CS /RAS /CAS State ROW L H ACTIVATING WRITE ...
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OPERATION COMMAND TRUTH TABLE - IV Current /CS /RAS /CAS State WRITE MODE L H REGISTER ACCESSING ...
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CKE FUNCTION TRUTH TABLE Current CKEn- CKEn State SELF REFRESH POWER DOWN ...
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SIMPLIFIED STATE DIAGRAM MODE REGISTER SET PDEN POWER DOWN READ WRITE READAP WRITE WRITEAP PRE(PALL) Rev. 1.0 / Feb. 2005 MRS SREF IDLE SREX PDEX AREF ACT POWER DOWN PDEN BST PDEX BANK ACTIVE WRITE READ READAP WITH WITH AUTOPRE- ...
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POWER-UP SEQUENCE AND DEVICE INITIALIZATION DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Except for CKE, inputs are not recognized as valid until after VREF ...
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Issue 2 or more Auto Refresh commands. 8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low. Power-Up Sequence VDD VDDQ tVTD VTT VREF /CLK CLK tIS tIH LVCMOS Low Level CKE ...
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MODE REGISTER SET (MRS) The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is program via MRS command. This command is ...
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BURST DEFINITION Burst Length Starting Address (A2,A1,A0) XX0 2 XX1 X00 X01 4 X10 X11 000 001 010 011 8 100 101 110 111 BURST LENGTH & TYPE Read and write accesses to the DDR SDRAM are burst oriented, with ...
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CAS LATENCY The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed clocks. ...
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EXTENDED MODE REGISTER SET (EMRS) The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func- tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The Extended ...
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ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative Voltage on V relative Voltage on V relative to V DDQ SS Output Short Circuit Current Power Dissipation Soldering Temperature˜Time ...
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DC CHARACTERISTICS II Parameter Symbol Operating Current I DD0 Operating Current I DD1 Precharge Standby Current I DD2P in Power Down Mode Precharge Standby Current I DD2N in Non Power Down Mode Active Standby Current in I DD3P Power Down ...
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AC OPERATING CONDITIONS Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Note ...
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AC CHARACTERISTICS - I Parameter Symbol Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Row Address to Column Address t Delay for Read Row Address to Column Address t Delay for Write Row Active to Row Active ...
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Parameter Symbol Data-In Setup Time to DQS-In (DQ & DM) Data-In Hold Time to DQS-In (DQ & DM) Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time t Write DQS Preamble Hold Time t Write DQS ...
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AC CHARACTERISTICS - II Frequency CL tRC 350MHz (2.8ns 300MHz (3.3ns 275MHz (3.6ns 250MHz (4.0ns Rev. 1.0 / Feb. 2005 tRFC tRAS tRCDRD tRCDWR ...
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CAPACITANCE o (T =25 C, f=1MHz ) A Parameter Input Clock Capacitance Input Capacitance Input / Output Capacitance Note : min. to max 2.3V to 2.7V DDQ 2. Pins not under test are ...
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PACKAGE INFORMATION 12mm x 12mm, 144ball Fine-pitch Ball Grid Array Rev. 1.0 / Feb. 2005 1HY5DS573222F(P) 28 ...