HM64YGB36100BP-33 Renesas Electronics Corporation., HM64YGB36100BP-33 Datasheet
HM64YGB36100BP-33
Related parts for HM64YGB36100BP-33
HM64YGB36100BP-33 Summary of contents
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... Asynchronous G output control Asynchronous sleep mode FC-BGA 119pin package with SRAM JEDEC standard pinout Limited set of boundary scan JTAG IEEE 1149.1 compatible Ordering Information Type No. Organization HM64YGB36100BP- Note: HM: Hitachi Memory prefix, 64: External Cache SRAM Rev.1.00 Jun 27, 2005 page DDQ ...
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HM64YGB36100 Series Pin Arrangement DDQ DQc7 E DQc5 F V DDQ G DQc3 H DQc1 J V DDQ K DQd1 L DQd3 M V DDQ N DQd5 P DQd7 ...
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HM64YGB36100 Series Pin Descriptions Name I/O type V Supply Core power supply DD V Supply Ground SS V Supply Output power supply DDQ V Supply Input reference, provides input reference voltage REF K Input Clock input, active high K Input ...
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HM64YGB36100 Series Truth Table SWE SWE SWEa SWEa SS SS SWE SWE SWEa SWEa ...
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HM64YGB36100 Series Programmable Impedance Output Drivers Output buffer impedance can be programmed by terminating the ZQ pin to V value five times the output impedance desired. The allowable range guarantee impedance matching with a ...
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HM64YGB36100 Series Note: The following DC and AC specifications shown in the tables, this device is tested under the minimum transverse air flow exceeding 500 linear feet per minute. Recommended DC Operating Conditions Parameter Power supply voltage: core Power supply ...
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HM64YGB36100 Series DC Characteristics Parameter Input leakage current Output leakage current Standby current V operating current, excluding output drivers DD Quiescent active power supply current Maximum power dissipation, including output drivers Parameter Symbol Output low voltage V OL Output high ...
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... Transitions are measured 50 mV from steady state voltage. 5. When ZZ is switching, clock input K must be at the same logic level for the reliable operation. 6. Minimum value is verified by design and tested without guardband. Rev.1.00 Jun 27, 2005 page ( + Single Differential Clock Register-Register Mode HM64YGB36100BP -33 Symbol Min Max t 3 ...
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HM64YGB36100 Series Timing Waveforms Read Cycle SWE SWEx DQ Read Cycle-2 (SS Controlled SWE SWEx DQ Rev.1.00 Jun 27, 2005 page KHKH KHKL KLKH t t ...
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HM64YGB36100 Series Read Cycle-3 (G Controlled SWE SWEx G DQ Read operation During read cycle, the address is registered during the first rising clock edge, the internal array is read between this first edge and second ...
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HM64YGB36100 Series Write Cycle SWE SWEx G DQ Notes Write operation During write cycle, the write data follows the write address by one cycle. All N bits ...
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HM64YGB36100 Series Read-Write Cycle READ t KHKH SWE SWEx Notes Control t KHKH AVKH SA t AVKH SS t ...
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HM64YGB36100 Series Input Capacitance Parameter Input capacitance Clock input capacitance I/O capacitance Notes: 1. This parameter is sampled and not 100% tested. 2. Exclude G 3. Connect pins to GND, except V AC Test Conditions Parameter Input and output timing ...
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HM64YGB36100 Series Boundary Scan Test Access Port Operations Overview In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary scan test access port (TAP) is designed to operate in a manner consistent with ...
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HM64YGB36100 Series TAP AC Operating Characteristics Parameter Test clock cycle time Test clock high pulse width Test clock low pulse width Test mode select setup Test mode select hold Capture setup Capture hold TDI valid to TCK high TCK high ...
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HM64YGB36100 Series TAP Controller Timing Diagram t THTH TCK TMS TDI TDO RAM ADDRESS Test Access Port Registers Register name Instruction register Bypass register ID register Boundary scan register TAP Controller Instruction Set IR2 IR1 IR0 Instruction ...
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HM64YGB36100 Series Boundary Scan Order (HM64YGB36100) Bit # Bump SA19 3 4T SA3 4 6R SA1 5 5T SA2 DQa8 8 7P DQa7 9 6N DQa6 10 7N DQa5 ...
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HM64YGB36100 Series ID Register Revision number Part (31:28) HM64YGB36100 0000 TAP Controller State Diagram Test-logic- 1 reset Run-test/ 0 idle Note: The value adjacent to each state transition in this figure represents the signal present at TMS at the time ...
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... HM64YGB36100 Series Package Dimensions HM64YGB36100BP Series (PRBG0119DC-A / Previous Code: BP-119F) JEITA Package Code RENESAS Code P-BGA119-14x22-1.27 PRBG0119DC-A A INDEX Rev.1.00 Jun 27, 2005 page Previous Code BP-119F D B × ...
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Revision History Rev. Date Page 0.0 Dec. 5, 2002 Initial issue 1.00 Jun. 27, 2005 Change format issued by Renesas Technology Corp. 1 Ordering Information 5 Change of 19 Package Dimensions HM64YGB36100 Series Data Sheet Description Addition of Renesas package ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...