CS5321-BL Cirrus Logic, Inc., CS5321-BL Datasheet
CS5321-BL
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CS5321-BL Summary of contents
Page 1
... The CS5321 uses Delta-Sigma modulation to pro- duce modulator oversamples, virtually eliminating the need for external analog anti-alias filters. The CS5322 linear-phase FIR digital filter decimates the output to any one of seven selectable update peri- ods: 16 ...
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... RESET Operation ............................................................................ 23 2.12. Power-down Operation .................................................................... 23 2.13. SYNC Operation .............................................................................. 24 2.14. Serial Read Operation ..................................................................... 24 2.15. Serial Write Operation ..................................................................... 24 2.16. Offset Calibration Operation ............................................................ 25 2.17. Status Bits ....................................................................................... 26 2.18. Board Layout Considerations .......................................................... 28 3. CS5321 PIN DESCRIPTIONS ....................................................................... 29 Power Supplies ......................................................................................... 29 Analog Inputs ............................................................................................ 29 Digital Inputs ............................................................................................. 30 Digital Outputs .......................................................................................... 30 4. CS5322 PIN DESCRIPTIONS ....................................................................... 31 Power Supplies ......................................................................................... 31 Digital Outputs .......................................................................................... 31 Digital Inputs ............................................................................................. 32 5 ...
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... Figure 24. 1024 Point FFT Plot with Full Scale Input, 100 Hz Input, HBR = 0, ten averages ............................................. 22 LIST OF TABLES Table 1. Output Coding for the CS5321 and CS5322 Combination ....................... 21 Table 2. Configuration Data Bits ............................................................................ 25 Table 3. Status Data (from the SOD Pin) ............................................................... 26 Table 4. Bandwidth Selection: Truth Table ............................................................ 27 DS454F3 = 62 ...
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... Full Scale Drift Offset Offset after Calibration Offset Calibration Range Offset Drift Notes: 1. CS5321-BL is guaranteed from - CS5322 output word rate. Refer to “CS5322 FILTER CHARACTERISTICS” on page 8 for details O on the FIR Filter. 3. Characterized with full scale input signal 500 Hz. ...
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... Hz. Refer to CS5322 Filter Characteristics for the values of f3. 11. All outputs unloaded. All logic inputs forced to V 12. LPWR = 0. 13. The CS5321 power dissipation can be reduced under the following conditions: a) LPWR=1; MCLK=512 kHz, HBR=1 b) LWPR=1; MCLK=1.024 MHz, HBR=0 14 ...
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... V 1.0 V Figure 1. Rise and Fall Times Figure 2. CS5321 Interface Timing, HBR=1 CS5321/ ± 5 dd1 dd2 ss1 Min Typ Max Units 0.250 1.024 1.2 MHz ...
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... CS5321 RECOMMENDED OPERATION CONDITIONS 0 V, See Note 20) Parameter DC Supply: Ambient Operating Temperature Notes: 20. The maximum voltage differential between the Positive Supply of the CS5321 and the Positive Digital Supply of the CS5322 must be less than 0.25 V. CS5321 ABSOLUTE MAXIMUM RATINGS * Parameter DC Supply: Input Current, Any Pin Except Supplies ...
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... Note 1); VD+ = 5.0 V; GND = Passband Flatness -3dB Freq (dB) (Hz) PB 0.2 1652.5 0.04 824.3 0.08 411.9 0.1 205.9 0.1 102.9 0.1 51.5 0.1 25 Figure 6. CS5322 Digital Filter Passband Ripple CS5321/22 Stopband f3 (Hz) Group Delay (Note 22) (ms) 2000 7.25 1000 14.5 500 29 250 58 125 116 62.5 232 31.25 464 250 Hz 0 DS454F3 ...
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... Figure 10. CS5322 Digital Filter Passband Ripple -5 ,2 06, 12, 18, 25, 31, 37, 43, 50, Figure 12. CS5322 Impulse Response, CS5321/ 1000 4000 8 ...
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... CS5321/22 CS5322-BL Typ Max Unit 2 0.6 2.5 mW Min Typ Max Units 0.512 1.024 1.2 MHz 100 100 100 ...
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... rdd t t rph rpl rds Serial Port Read Timing Serial Port Write Timing Figure 13. CS5322 Serial Port Timing CS5321/22 t rst t rhc t rch H i-Z LSB rsp ...
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... Symbol tds t tdh Figure 14. TDATA Setup/Hold Timing CS5321/22 Min Typ Max Units 150 - 140 - ns - 150 - ns - 140 ...
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... rite ill DS454F3 Figure 15. DRDY Timing Figure 16. RESET Timing CS5321/ ...
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... Symbol (Note 24 (Note 25) t rise (Note 25) t fall mss t msh (Note 26) t msd Figure 17. CS5321/CS5322 Interface Timing CS5321/22 Min Typ Max Units 0.512 1.024 1 100 - 50 200 - - 100 - 50 200 ...
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... CS5322 RECOMMENDED OPERATION CONDITIONS 0 V) Parameter DC Supply: Positive Negative Ambient Operating Temperature Notes: 29. The maximum voltage differential between the Positive Supply of the CS5321 and the Positive Digital Supply of the CS5322 must be less than 0.25 V. CS5322 ABSOLUTE MAXIMUM RATINGS * Parameter DC Supply: Positive Negative ...
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... The CS5322 is a monolithic digital Finite Impulse Response (FIR) filter with programmable decima- tion. The CS5322 and CS5321 are intended to be used together to form a unique high dynamic range ADC chipset. The CS5322 provides the digital anti-alias filter for the CS5321 modulator output. ...
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... Figure 19. CS5322 Block Diagram CS5321/ ...
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... The bandlimit- 18 ing may be accomplished in an amplifier stage ahead of the CS5321 modulator or with the RC in- put filter at the AIN+ and AINR input pins. The RC filter at the AIN+ and AINR pins is recommended to reduce the "charge kick" that the driving ampli- fier sees as the switched capacitor sampling is per- formed ...
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... CS5321 and guarantee that any idle tones present will lie out-of-band. The user should be certain that when OFST is active (OFST =1) that the offset voltage generated by the user cir- cuitry does not negate the offset added by the OFST pin. ...
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... S/N slightly lower (1-2 dB) than when using a 4.5 V reference. The voltage reference should be de- signed to yield less than 2 µVrms of noise in band at the VREF+ pin of the CS5321. The CS5322 filter selection will determine the bandwidth over which the voltage reference noise will affect the CS5321/22 dynamic range ...
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... When operated with the CS5322 digital filter the output codes from the CS5321/22 will range from approximately decimal -5,242,880 to +5,242,879 for an input to the CS5321 of ±4.5 V. Table 1 illus- trates the output coding for various input signal am- plitudes. Note that with a signal input defined as a full scale signal (4 ...
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... The CS5321 will exhibit about 6 ppm/°C of offset drift with MCLK = 1 and HBR = 1. Gain drift of the CS5321 itself is about 5 ppm/°C and is not affected by either modulator sample rate or by power supply variation ...
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... When used with the CS5322 digital filter, the max- imum voltage differential between the positive sup- plies of the CS5321 and the positive digital supply of the CS5322 must be less than 0.25 V. Operation beyond this constraint may result in loss of analog performance in the CS5321/22 system perfor- mance ...
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... CSEL and TDATA must not both be asserted high. 2.13 SYNC Operation The SYNC pin is used to start convolutions and synchronize the CS5322 and CS5321 to an external sampling source or timing reference. The SYNC event is recognized on the first CLKIN rising edge after the SYNC pin goes high. SYNC may remain high indefinitely ...
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... The Reserved configuration data bit must always be written low. 2.16 Offset Calibration Operation The offset calibration routine computes the offset produced by the CS5321 modulator and stores this value in the offset register. The USEOR pin or bit determines if the offset register data used to correct output words. ...
Page 26
... Status reads have no effect on OVERWRITE assert operations. The OVERWRITE bit is cleared on a status register read or RESET. The MFLG error bit reflects the CS5321 MFLG signal. Any high level on the CS5322 MFLG pin will set the MFLG status bit. The bit is cleared on a status register read or RESET operation, only if the MFLG pin on the CS5322 has returned low ...
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... CSEL- When high, TDATA is selected as the filter source. When low, the MDATA output signal from the CS5321 is selected as the input source to the fil- ter. Reserved - Always read low. DECC, DECB, and DECA - Indicate the decimation rate of the filter and are defined in Table 4 ...
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... AINR pins should be placed with their leads on the same axis, not side-by-side. If these capacitors are placed side-by-side their electric fields can interact and cause increased distortion. The chip should be surrounded with a ground plane. Trace fill should be used around the analog input components. CS5321/22 DS454F3 ...
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... CS5321 PIN DESCRIPTIONS Power Supplies V Positive Power One, PIN 2 dd1 – Positive supply voltage. Nominally +5 Volts. V Positive Power Two, PIN 22 dd2 – Positive supply voltage. Nominally +5 Volts. V Negative Power One, PIN 3 ss1 – Negative supply voltage. Nominally -5 Volts. V Negative Power Two, PIN 21 ss2 – ...
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... MCLK operating at 1.024 MHz. MDATA – Modulator Data Output, PIN 17 Inverse of the MDATA output. MFLG – Modulator Flag, PIN 24 A transition from a low to high level signals that the CS5321 modulator is unstable due to an overrange on the analog input 30 ⁄ ...
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... A CMOS-compatible clock output (nominally 1.024 MHz) that provides the necessary clock for operation of the modulator. MSYNC – Modulator Sync, Pin 5 The transition from a low to high level on this output will re-initialize the CS5321. ERROR - Error Flag, Pin 23 This signal is the output of an open pull-up NOR gate with a nominal 100 kΩ pull-up resistor to which the error status data (OVERWRITE error, MFLG error, ACC1 error and ACC2 error) are inputs ...
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... Input for user test data. MFLG – Modulator Flag, Pin 6 A transition from a low to high level signals that the CS5321 modulator is unstable due to an over-range on the analog input. A Status Bit will be set in the digital filter indicating an error condition. An internal nominal 100 kΩ pull-down resistor included on the input pin. ...
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... ORCAL - Offset Register Calibrate, Pin 19 Initiates an offset calibration cycle when SYNC goes high after ORCAL has been toggled from low to high. The offset value is output on the 57th word following SYNC. Subsequent words will have their offset correction controlled by USEOR. DS454F3 CS5321/22 33 ...
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... The change in the Full Scale value with temperature. Units in %/°C. Offset The difference between the analog ground and the analog voltage necessary to yield an output code from the CS5321/22 of 000000(H). Measurement of this parameter uses the circuit configuration illustrated in the System Connection Diagram. Units in mV. Offset Drift The change in the Offset value with temperature. Measurement of this parameter uses the circuit configuration illustrated in the System Connection Diagram. Units in µ ...
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... JEDEC #: MS-018 CS5321/22 e D2/ MILLIMETERS MAX 4.572 3.048 0.533 12.573 11.582 10.922 12.573 11.582 10.922 1.524 35 ...
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... ORDERING INFORMATION Model CS5321-BL CS5321-BLZ (Lead Free) CS5322-BL CS5322-BLZ (Lead Free) 8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5321-BL CS5321-BLZ (Lead Free) CS5322-BL CS5322-BLZ (Lead Free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 9. REVISION HISTORY Revision Date PP3 OCT 2003 Initial Release. ...