CS4235-JQ Cirrus Logic, Inc., CS4235-JQ Datasheet
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CS4235-JQ
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CS4235-JQ Summary of contents
Page 1
... The CS4235 is compatible with the Microsoft run software written to the Sound Blaster and Sound Blaster Pro interfaces. The CS4235 is fully compliant with Microsoft’s PC’97 and PC’98 audio requirements. ORDERING INFO CS4235-JQ CS4235-KQ 100 pin TQFP, 14x14x1.4mm Stereo ADC1 Stereo DAC1 ...
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... Analog Inputs ...................................................82 Analog Outputs.................................................83 MIDI Interface...................................................84 External Peripheral Signals..............................84 Joystick Interface..............................................85 CS4610 DSP Serial Port Interface...................85 CS9236 Wavetable Serial Port Interface .........85 CDROM Interface.............................................86 Volume Control.................................................87 Miscellaneous...................................................87 Power Supplies ................................................88 PARAMETER DEFINITIONS...............................89 PACKAGE PARAMETERS .................................90 APPENDIX A: DEFAULT PnP DATA.................91 APPENDIX B: CS4235 DIFFERENCES .............93 CRD4235-8 DS252PP2 ...
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... MGE or MBST = 1 (see WSS Indirect Reg I0 or X2). *Parameter definitions are given at the end of this data sheet. Specifications are subject to change without notice. DS252PP2 CrystalClear Low Cost ISA Audio System ( °C; VA, VD1, VDF1-VDF3 = + CS4235-JQ Symbol Min Typ (Note (Note ...
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... Power Supply Rejection, 1 kHz Notes 100 pF load current only. If dynamic loading exists, then the voltage reference output must be buffered or the performance of ADCs and DACs will be degraded. 4 CrystalClear Low Cost ISA Audio System (Continued) CS4235-JQ Symbol Min Typ (Note 1) 16 (Note 1) ...
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... SA<15:0>, IOR, IOW, AEN SD<7:0>, DACK<A:C> All other digital inputs Ambient Temperature Storage Temperature Warning: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. DS252PP2 CS4235-JQ Symbol Min Typ Max AUX1, AUX2 - MIC - Hardware Master - DAC1, DAC2 ...
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... VDF1-VDF3 Symbol (0-0.40xFs) ADC1 DAC1 Symbol UP/DOWN/MUTE V IH Other Digital Inputs XTALI -24 (Note - 4.0 mA (Digital Inputs) (High-Z Digital Outputs) CS4235 TM Min Typ Max 4.75 5.0 5.25 4.75 5.0 5.25 4.75 5.0 5. (Note 1) Min Typ Max Units 0 - 0.40xFs -1 ...
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... SU:STO t HSCL t LSCL HD:STA t HD:DAT PROM 2-Wire Interface Timing TM CrystalClear Low Cost ISA Audio System Min Max t 0 3.5 AA 4.0 - 4.7 - LSCL 4.0 - HSCL 4 250 - 300 F 4 SU:DAT t DH CS4235 Units SU:STO 7 ...
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... DKHDa t DKHDb (Note 1) t RESDRV (Note INIT (Note 1, 10) t EEPROM (Notes 1, 11) (Notes 1, 11) (Notes 1, 11) (Note 1) Fs (Note 1) t PD1 (Note 1) t PD2 (Note (Note CS4235 TM Min Max Units ...
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... CS4610 DSP Serial Port Timing t t DKSUa DRHD t STW t RDDV 8-Bit Mono DMA Read/Capture Cycle t RESDRV t t INIT EEPROM EEPROM read Reset Timing TM CrystalClear Low Cost ISA Audio System t h1 MSB, Left MSB, Left t DKHDb t DHD1 Codec responds to ISA activity CS4235 9 ...
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... CrystalClear Low Cost ISA Audio System t t DKSUb DRHD t STW 8-Bit Mono DMA Write/Playback Cycle t BWDN LEFT/LOW BYTE 8-Bit Stereo or 16-Bit Mono DMA Cycle t BWDN LEFT/LOW LEFT/HIGH BYTE BYTE 16-Bit Stereo DMA Cycle CS4235 TM t DKHDa t t DHD2 WDSU RIGHT/HIGH BYTE RIGHT/LOW RIGHT/HIGH BYTE BYTE DS252PP2 ...
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... DRQ<> t SUDK1 DACK<> IOR SD<> SA<> AEN DRQ<> t SUDK1 DACK<> IOW SD<> SA<> AEN DS252PP2 TM CrystalClear Low Cost ISA Audio System t SUDK2 t t RDDV t ADSU I/O Read Cycle t SUDK2 t STW t t WDSU t ADSU I/O Write Cycle CS4235 DHD1 t ADHD DHD2 t ADHD 11 ...
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... Pro- grammed I/O (PIO) access, and DMA access. A number of configuration registers must be pro- grammed prior to any accesses by the host computer. The configuration registers are pro- grammed via a Plug-and-Play configuration sequence or via configuration software provided by Cirrus Logic. CS4235 DS252PP2 ...
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... Down section). If the CDROM is needed, the circuit shown in Figure 2 can replace the SA12 through SA15 pins and provide the same func- tionality. Four cascaded OR gates, using a 74ALS32, can replace the ALS138 in Figure 2, but causes a greater delay in address decoding. CS4235 TM Logical Device 4 CDROM: I/O: CDbase ...
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... WSS Codec and the Sound Blaster Pro compatible de- vices, and the other for the MPU401 device. Interrupts are also supported for the FM Synthe- sizer, Control, and CDROM devices, but are typically not used. TM CrystalClear Low Cost ISA Audio System CS4235 DS252PP2 ...
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... The configuration sequence is as follows: 1. Host sends a software key which places all PnP cards in the sleep state (or Plug-and- Play mode). 2. The CS4235 is isolated from the system using an isolation sequence unique identifier (handle) is assigned to the part and the resource data is read. ...
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... Checksum. Of the 9-byte serial number listed above, Cirrus software uses the first two bytes to indicate the presence of a CS4235, and the fourth byte, 0x25, to indicate the CS4235; therefore, these three bytes must not be altered. The default PnP ID, in hex, is 0E634236FFFFFFFFA9 for backwards compatibility ...
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... ANSI ID = CSC0001 200h 208h 8/8 8/8 ANSI ID = CSC0010 120-FF8h 8/8 ---- ANSI ID = CSC0003 330h 330-360h 2/8 2/8 9 9,11,12,15 CS4235 TM 2 PROM interface. If the first 2 PROM port read 55h and 2 PROM data is 2 PROM is assumed not 2 PROM is required to ensure Sub optimal Sub optimal Choice 1 Choice 2 ANSI ID = WSS/SB 534-FFCh 4/4 ...
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... To use the SLAM method, see the Bypassing PnP section. The following 32 bytes, in hex, are the Crystal key: 96, 35, 9A, CD, E6, F3, 79, BC, 5E, AF, 57, 2B, 15, 8A, C5, E2, F1, F8, 7C, 3E, 9F, 4F, 27, 13, 09, 84, 42, A1, D0, 68, 34, 1A CS4235 TM DS252PP2 ...
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... SYNbase = 0x388 042h, 002h, 020h ; SBbase = 0x220 022h, 005h 02Ah, 001h 025h, 003h 033h, 001h 015h, 001h 047h, 002h, 000h ; GAMEbase = 0x200 033h, 001h CS4235 TM ; CSN=1 ; LOGICAL DEVICE 0 ; WSS & SB IRQ = 5 ; WSS & SB DMA0 = 1 ; WSS capture DMA1 = 3 ; activate logical device 0 ; LOGICAL DEVICE 1 ...
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... Crystal Key uses custom commands and is write-only; whereas, CK2 places the part in a PnP Configuration state and uses standard PnP commands to access PnP configuration registers. Since CK2 is unique to the CS4235, the PnP iso- lation sequence is bypassed CrystalClear Low Cost ISA Audio System CK2 differs from normal PnP in that the RDP is read/write instead of read-only ...
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... IRQ E/F Selection: Lower nibble = E, Upper nibble = F. DMA A/B Selection: Lower nibble = A, Upper nibble = B. and the 7th IRQ pin - IRQ G 2 PROM and are not used in the Hostload mode. Table 2. Hardware Configuration Data TM CrystalClear Low Cost ISA Audio System 2 PROM exists. 2 PROM 2 PROM CS4235 21 ...
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... CB4 CB3 CB2 Code Base Byte. Determines the code 2 base located in the E PROM. If not correct, the Firmware code after the PnP resource data is not loaded. 2 0x05 - CS4235 E PROM Load 0x06 - CS4235 Host Load CS4235 D1 D0 res res D1 D0 CB1 CB0 DS252PP2 ...
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... AUX1 analog inputs are substituted for LINE analog inputs which are no longer available. EEPROM Checksum. If set, indicates that Hardware Configuration Byte checksum for the entire EEPROM (starting after 55h/BBh). CS4235 D1 D0 EC1 EC0 D1 D0 res res ...
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... First, send the 32-byte Crystal key to I/O address port (AP). Second, configure logical device 2 base address, CTRLbase, by writing to AP (15h, 02h, 47h, xxh, xxh, 33h, 01h, 79h). Note: The two xxh represent the base_ad- dress_high and base_address_low respectively. The default is: 01h, 20h. CS4235 2 PROM DS252PP2 ...
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... Serial Identifier as being a user de- 2 fined serial number. The E change the user section of the identifier, store default resource data for PnP, Hardware Con- figuration data specific to the CS4235, and firmware patches to upgrade the core processor functionality. 2 The E PROM interface uses an industry standard 2-wire interface consisting of a bi-directional data line and a clock line driven from the part ...
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... Digital and Digital-to-Analog converters (ADCs and DACs), analog mixing, anti-aliasing and re- construction filters, line and microphone level Bank Part Read Start Address Address Acknowledge Figure 3. EEPROM Format CS4235 TM 2 PROM resource data format. 2 PROM data in successive bits to 2 PROM data sheet for- No Acknowledge Acknowledge ...
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... WSS Codec to drive data on the ISA data bus lines. Write cycles require the host to assert data on the ISA data bus lines and strobe the IOW signal. The WSS Codec will latch data into the PIO register on the rising edge of the IOW strobe. CS4235 27 ...
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... The playback of audio data will occur on the playback channel exactly as dual channel opera- tion; however, the capture audio channel is now diverted to the playback channel. Alternatively stated, the capture DMA request occurs on DMA channel select 0 for the WSS Codec. (In MODEs 2 and 3, the capture data format is al- CS4235 TM DS252PP2 ...
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... Alternate Feature Status I25 Compatibility ID I26 Mono Input Control I27 Left Master Output Volume I28 Capture Data Format I29 Right Master Output Volume I30 Capture Upper Base Count I31 Capture Lower Base Count Table 4. WSS Codec Indirect Registers CS4235 Register Name 29 ...
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... Indexed Data Register (WSSbase+1, R1 ID7 ID6 ID7-ID0 CS4235 TM Transfer Request Disable: This bit, when set, causes DMA transfers to cease when the INT bit of the Status Register (R2) is set. Independent for playback and capture interrupts Transfers Enabled (playback and ...
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... The PIO Data register is two registers mapped to the same address. Writes to this register sends data to the Playback Data register. Reads from this register will receive data from the Capture Data register. CS4235 TM be determined. However, the Alter- nate Feature Status register (I24) indicates the exact source of error. ...
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... This bit is identical to the MGE bit in I0. It controls the 20 dB gain boost for the MIC analog input. Right output loopback. Setting these bits to 11 enables the right output loopback into the input mixer. Other bit combinations disable the loop- back. CS4235 D1 D0 rbc rbc D1 D0 rbc ...
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... Auxiliary #2 input, RAUX2, to the output mixer is muted significant bit represents -1.5 dB, with 000000 = 0 dB. The total range -94.5 dB. See Table 6. Left DAC1 Output Mute. When set, the left DAC1 to the output mixer is muted. CS4235 ...
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... XRAE XA4 - MIA3 MIA2 MIA1 LOG3 LOG2 LOG1 - - - ROG3 ROG2 ROG1 CUB3 CUB2 CUB1 CLB3 CLB2 CLB1 CS4235 D0 IA0 ID0 INT CD0/PD0 LX1G0 RX1G0 LX2G0 RX2G0 LD1A0 RD1A0 C2SL PEN - ORL0 0 - PUB0 PLB0 DACZ HPF LD2A0 RD2A0 CR0 ...
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... X 189 5.600 5.600 16 X 190 5.570 5.570 5.541 16 X 191 5.541 5.512 16 X 192 5.512 5.512 16 X 192 5.483 16 X 192 5.512 5.455 . . . 16 X 192 5.512 4.150 CS4235 MIC 22.5 dB 21.0 dB 19.5 dB 18 4.5 dB 3 -19.5 dB -21.0 dB -22.5 dB muted DAC Divider 353 529 ...
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... DRQ and respond to DACK signal when this bit is en- abled and PPIO=0. If PPIO=1, PEN enables PIO playback mode. PEN may be set and reset without setting the MCE bit Playback Disabled (playback DRQ and PIO inactive Playback Enabled CS4235 D1 D0 CEN PEN DS252PP2 ...
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... SRE = 1 in I22. These bits in com- bination with DIV5-DIV0 and CS2 (I22) determine the current sample rate of the WSS Codec when SRE = 1. Note that these bits can be disabled by setting IFSE in X11 kHz < > 24 kHz kHz 11 - reserved CS4235 DTM IEN res 24 kHz 37 ...
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... Default = xxxxxxxx D7 D6 rbc rbc rbc res CS4235 TM Playback underrun: This bit is set when playback data has not arrived from the host in time to be played result, if DACZ = 0, the last valid sample will be sent to the DACs. This bit is set when an error occurs and will not clear until the Status register (R2) is read ...
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... High Pass Filter: This bit enables a DC-blocking high-pass filter in the digital filter of the ADC. This filter forces the ADC offset disabled 1 - enabled Factory Test. These bits are used for factory testing and must remain at 0 for normal operation. CS4235 D1 D0 rbc HPF 39 ...
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... Note that the part uses only one crystal to generate both clock base frequencies. This bit can be disabled by setting IFSE in X11 24.576 MHz base 1 - 16.9344 MHz base CS4235 D1 D0 CR1 CR0 D1 D0 RE1 ...
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... In this condition, the bit is set and the last valid byte is read by the host. Playback Interrupt: Indicates an interrupt is pending from the play- back DMA count registers. Capture Interrupt: Indicates an interrupt is pending from the capture DMA count registers. CS4235 ...
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... This register is fixed to indicate code compatibility with the CS4236. X25 or C1 should be used to further differentiate between parts that are compatible with the CS4236. All Chips: 00011 - CS4236, CS423xB, CS4235 00010 - CS4232/CS4232A 00000 - CS4231/CS4231A V2-V0 Version number. As enhancements are made to the part, the version ...
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... CLB5 CLB4 CLB3 CLB2 Lower Base Bits: This register is the lower byte which represents the 8 least significant bits of the 16-bit Capture Base register. Reads from this register returns the same value which was written. CS4235 D1 D0 CUB1 CUB0 D1 D0 CLB1 CLB0 43 ...
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... Space Control X24 (C8) Wavetable & Volume Control X25 Chip Version and ID X26 (Cb+0) Joystick Control 2 X27 (Cb+1) E PROM Interface X28 (Cb+2) Power Down Control 1 X29 (C9) Power Down Control 2 X30 (Cb+7) Global Status X31 Reserved Table 12. WSS Extended Registers CS4235 Register Name XA4 res rbc DS252PP2 ...
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... SRAD3 SRAD2 SRAD1 SRDA3 SRDA2 SRDA1 - - - - - - - - - - - - DSPD1 PSH - - - - - - - - - - - - - - - - WTEN VCEN DMCLK CID3 CID2 CID1 - - JR1 - DIN/EEN DOUT ADC DAC PROC - MIXCD DAC2 IMPU WDT IMV - - - CS4235 D0 IA0 ID0 - MG0 MG0 - - - - - - - - SRAD0 SRDA0 - - - - DLEN - - - - - BRES CID0 JR0 CLK FM SPORT - - 45 ...
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CS9236 SERIAL PORT CS4610 SERIAL PORT DSP Port Enable Wavetable Enable I16 C8 DSPD1 Enable X18 Loop Enable X18 Atten. I6L DAC1 I7R Mute X8L Mute X16L X17R X9R Gain I18L DAC2 I19R Mute X6L FM Syn. Enable X7R X4 ...
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... MG2 MG1 MG0 RMIM Synthesis and Input Mixer Control (X4) Default = e00exxxx D7 D6 MIMR LIS1 IFM LIS1-LIS0 CS4235 MG4 MG3 MG2 MG1 Microphone gain. The least significant bit represents 1.5 dB, with 01111 = 0 dB. These are the same bits as in X2. ...
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... I10 (OSM1,0), and I22 are ignored. X12 and X13 cannot be modified un- less this bit is set to 1. Right DAC1 Input Mixer Mute. When set to 1, the output from the Right DAC1 is muted to the Right in- put mixer. See Figure 4. CS4235 D1 D0 rbc rbc D1 D0 ...
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... rbc rbc rbc 3DEN AUX1R rbc rbc rbc PAE CS4235 rbc rbc rbc rbc rbc Right Wavetable Serial Port Mute. When set, the Right Wavetable Se- rial Input to DAC2 is muted. The default state of this bit is the inverse of WTEN in the Hardware Configura- tion Data, Global Configuration byte ...
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... Hardware Configuration data, Misc. Configuration Byte. Wavetable Serial Port Enable. When, set, the CS9236 Single-Chip Wave- table Music Synthesizer serial port pins are enabled. WTEN can be in- 2 itialized in the E PROM Hardware Configuration data, Global Configura- tion byte. CS4235 D0 res res D1 D0 DS252PP2 ...
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... Chip Identification. Distinguishes between this chip and other codec chips that support this register set. This register is identical to C1 and replaces the ID register in I25. 11101 - CS4235 V2-V0 Version Number. As enhancements are made, the version number is changed so software can distinguish between the different versions of the same chip ...
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... Control Logical Device 2 Interrupt status. A context switch interrupt is pending when set to 1. Context - WSS. Indicates the current context Sound Blaster Emulation 1 - Windows Sound System res res res res res Reserved. Could read CS4235 D1 D0 IMV res D1 D0 res res DS252PP2 ...
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... Right FM Status Port Mixer Register Address Mixer Data Port Reset FM Status Port FM Register port FM Data Port Read Data Port Command/Write Data Write Buffer Status (Bit 7) Data Available Status (Bit 7) CS4235 TM Type Read Write Write Only Read Write Write Only Write Only Read/Write ...
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... D5 D4 DATA RESET RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Table 15. SBPro Compatible Mixer Interface VOICE VOLUME RIGHT X MIC MIXING INPUT SELECT X X VSTC MASTER VOLUME RIGHT FM VOLUME RIGHT CD VOLUME RIGHT LINE VOLUME RIGHT CS4235 DS252PP2 ...
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... JBB1 JAB2 JAB1 JBCY JACX Joystick A, Coordinate X (pin 3) JACY Joystick A, Coordinate Y (pin 6) JBCX Joystick B, Coordinate X (pin 11) JBCY Joystick B, Coordinate Y (pin 13) JAB1 Joystick A, Button 1 (pin 2) JAB2 Joystick A, Button 2 (pin 7) JBB1 Joystick B, Button 1 (pin 10) JBB2 Joystick B, Button 2 (pin 14) CS4235 JBCX JACY JACX 55 ...
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... X/Y coordinates must have a 5.6 nF capacitor to ground and a 2.2 k resistor to the appropriate joystick connector pin. Figure 5 illustrates the schematic to the joystick connector. VDF 2 5.6 nF 2.2 k 2.2 k 5 Figure 5. Joystick Logic CS4235 TM series ...
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... PROM Interface CTRLbase+1, Default = 1xxxx000 D7 D6 ICH rbc CLK rbc JR1 JR0 DOUT DIN/EEN ICH CS4235 TM Register Joystick Control 2 E PROM Interface Block Power Down Control Indirect Address Reg. Control Indirect Data Register Control/RAM Access RAM Access End Global Status D5 D4 ...
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... Commands are followed by address and data information. 0x55 - Disable PnP Key 0x56 - Disable Crystal Key 0x53 - Disable Crystal Key 2 0x5A - Update Hardware Configura- tion Data. 0xAA - Download RAM. Address followed by data. (Stopped by writ- ing 0 to CTRLbase+6) CS4235 D1 D0 CA1 CA0 D1 D0 CD1 CD0 D1 ...
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... CrystalClear Low Cost ISA Audio System Register Name Control Indirect Address Control Indirect Data Register Name Reserved Version / Chip ID 3D Space Control 3D Enable Reserved Reserved Reserved Reserved Wavetable & Volume Control Power Management Table 18. Control Indirect Registers CS4235 59 ...
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... Chip Identification. Distinguishes between this chip and other codec chips that support this register set. This register is identical to the WSS X25 register. 11101 - CS4235 V2-V0 Version number. As enhancements are made, the version number is changed so software can distinguish between the different versions of the same chip ...
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... When this bit goes from software RESDRV is initiated caus- ing the entire chip to be reset and placed in its default power-up con- figuration. Access to all registers on this chip will be lost, including this one, since the power-up state for PnP is all resources unassigned. CS4235 D1 D0 SPORT 61 ...
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... CS4 CS3 CS2 D0-D5 are the 6 LSBs of the last command written to this port. Transmit Buffer Status Flag Transmit buffer not full 1 - Transmit buffer full Receive Buffer Status Flag 0 - Data in Receive buffer 1 - Receive buffer empty CS4235 D1 D0 CS1 CS0 D1 D0 CS1 CS0 DS252PP2 ...
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... Configuration Byte) must be set. This bit is also available in WSS register X4. Volume control for the internal FM synthesizer is supported through I18 and I19 in the WSS ex- tended register space. The synthesizer interface is compatible with the Adlib and Sound Blaster standards. The typical Adlib I/O address is SYNbase = 388h. CS4235 63 ...
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... DAC channels. The first format - SPF0, shown in Figure 6, is called 64-bit enhanced. This format has 64 SCLKs per frame with a one bit period wide FSYNC that precedes the frame. The first 16 bits occupy the left word and the second 16 bits oc- CS4235 TM DS252PP2 ...
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... Figure 8. 32-bit Mode (SF1,0 = 10) TM CrystalClear Low Cost ISA Audio System ... 7 zeros INT CEN PEN OVR 32 Bits INT = Interrupt Bit CEN = Capture Enable PEN = Playback Enable OVR = Left Overrange or Right Overrange ... ... 0 16 Clocks Right Data 32 No-Clock bit periods 0 ... CS4235 13 zeros Left Data 65 ...
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... The hardware connections to the CS9236 are illustrated in Figure 10. ... DAC 16 Clocks ... DAC 16 Clocks ADC 16 Clocks Figure 9. ADC/DAC Mode (SF1,0 = 11) TM CrystalClear Low Cost ISA Audio System ... ... 0 ... ... DAC 16 Clocks Right Data CS4235 DS252PP2 ...
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... This calibration mode calibrates the ADCs and the DACs, but does not calibrate any of the ana- log mixing channels. This is the second longest calibration mode, taking 321 sample periods at 44.1 kHz. Because the analog mixer is not cali- TM CrystalClear Low Cost ISA Audio System CS4235 67 ...
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... The independent sample frequency mode is enabled by setting IFSE in X11. Once enabled, the other two methods for setting Fs (I8, I10, and I22) are disabled. The capture (ADC set in X12 and the playback (DAC set in X13. CS4235 DS252PP2 ...
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... The DMA registers allow easy integration of this part into ISA systems. Peculiarities of the ISA DMA controller require an external count mechanism to notify the host CPU of a full DMA buffer via interrupt. The programmable DMA Base registers provide this service. Figure 11. Linear Transfer Functions CS4235 69 ...
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... RIGHT CrystalClear Low Cost ISA Audio System 32-bit Word Time sample 2 sample 1 MONO 32-bit Word Time sample 1 sample 1 LEFT 32-bit Word Time sample 2 sample 1 MONO 32-bit Word Time sample 1 sample 1 LEFT CS4235 DS252PP2 ...
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... WSS Codec in an appropriate amount of time. The amount of time for such data transfers depends on the fre- quency selected within the WSS Codec. Should an overrun condition occur during data capture, the last whole sample (before the over- CS4235 71 ...
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... When VCF1 = 1, the MUTE pin is not used. This is a two-button format where pressing up and down simultaneously mutes the master vol- ume. If the master volume is muted and up or down is individually pressed, the volume auto- matically un-mutes. CS4235 Up Down 100 Mute 10 nF GND ...
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... SCL, which have internal 100 APSEL selects the Address Port used to configure the part. When APSEL is left high, the Address Port is 0x279 and backwards compat- ible to previous chips and standard PnP software. CS4235 TM 2 PROM is present or not and the 2 PROM. After RESDRV ...
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... All audio inputs should be capaci- tively coupled. Since some analog inputs can be as large the circuit shown in Figure 18 can be RMS used to attenuate the analog input which is the maximum voltage allowed for the line-level inputs. CS4235 TM 6 6 ...
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... AGND. TM CrystalClear Low Cost ISA Audio System MC33078 or MC33178 0.1 F 0.33 F X7R 4.7 k 2.7 nF NPO 600 + 10 F Figure 20. Microphone Input +5VA (Low Noise) or AGND - if CMOS Source 4 MIN 0.1 F 2.7 nF Figure 21. Mono Input CS4235 VREF MIC 75 ...
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... ISA bus. The VD1 pin can be connected directly to the system digital power supply. Digital Digital Ground Noise Ground Figure 22. Suggested Motherboard Layout TM CrystalClear Low Cost ISA Audio System Analog Crystal Ground Part 1 Power Connector CS4235 DS252PP2 ...
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... Digital Ground Figure 23. Suggested Add-In Card Layout PIN 80 AGND PIN PIN 81 SGND3 Analog Digital = vias through to power/ground plane PIN 45 VD1 TM Crystal Part PIN 79 REFFLT .1 F PIN 71 TEST PIN 66 SGND2 .1 F PIN 65 VDF2 PIN 53 SGND4 PIN 46 DGND1 .1 F CS4235 77 ...
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... TM CrystalClear Low Cost ISA Audio System 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Input Frequency ( x Fs) Figure 25. ADC Filter Response Input Frequency ( x Fs) Figure 27. ADC Transition Band CS4235 0.8 0.9 1 DS252PP2 ...
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... Input Frequency ( x Fs) Figure 30. DAC Transition Band DS252PP2 0.2 0.1 0.0 -0.1 -0 -0.4 -0.5 -0.6 -0.7 -0.8 0.6 0.7 0.8 0.9 1.0 0.00 2.0 1.5 1.0 0 -1.5 -2.0 0. CrystalClear Low Cost ISA Audio System 0.05 0.10 0.15 0.20 0.25 0.30 0.35 Input Frequency ( x Fs) Figure 29. DAC Passband Ripple 0.05 0.10 0.15 0.20 0.25 0.30 0.35 Input Frequency ( x Fs) Figure 31. Deviation from Linear Phase CS4235 0.40 0.45 0.50 0.40 0.45 0.50 79 ...
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... SGND1 19 (INT15*) IRQF 20 (INT12*) IRQE 21 (INT11*) IRQD 22 (INT9*) IRQC 23 (INT7*) IRQB 24 (INT5*) IRQA 25 SA0 * Defaults - See individual pin descriptions for more details 80 CrystalClear Low Cost ISA Audio System (TOP VIEW ) CS4235 TM 75 LAUX1 74 RAUX1 73 LOUT 72 71 TEST 70 JAB1 69 JBB1 68 JACX 67 JBCX ...
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... The DRQ<A,B,C> outputs must be connected to 8-bit DMA channel request signals only. The defaults on the ISA bus are DRQA = DRQ0, DRQB = DRQ1, and DRQC = DRQ3. The defaults can be changed by modifying the Hardware Resource data. DS252PP2 TM CrystalClear Low Cost ISA Audio System CS4235 81 ...
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... Plug and Play configuration sequence. The defaults on the ISA bus are IRQA = INT5, IRQB = INT7, IRQC = INT9, IRQD = INT11, IRQE = INT12, IRQF = INT15. IRQG is new to the CS4235 and defaults to unconnected for compatibility reasons. For new designs, IRQG is typically connected to IRQ10. The defaults ...
Page 83
... VREF. A 1000 pF NPO capacitor must be attached from this pin to AGND. FLT3D - 3D Filter A 0.01 F capacitor must be attached from this pin to AGND. FLTO - Filter Output A 1000 pF NPO capacitor must be attached between this pin and FLTI. DS252PP2 TM CrystalClear Low Cost ISA Audio System max centered around RMS max centered around RMS CS4235 83 ...
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... This active low signal goes low whenever the RESDRV pin goes high. This pin is also software controllable through the BRES bit in register C8 in the Control Logical Device space. BRES provides a software power down and reset control over devices connected to the CS4235 such as the CS9236 Single-Chip Wavetable Music Synthesizer. ...
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... CS9236 Wavetable Serial Port Interface A digital interface to the CS9236 Single-Chip Wavetable Music Synthesizer is provided that allows the CS9236 PCM audio data to be summed on the CS4235 without the need for an external DAC. This serial port is enabled via the WTEN bit which is located in the Global ...
Page 86
... SDATA - Wavetable Serial Audio Data, Input This input supplies the serial audio PCM data to be mixed to the stereo DAC2 of the CS4235. The data consists of left and right channel 16-bit data delineated by LRCLK. This pin should be connected to the SOUT output pin on the CS9236. This pin should also have a weak pull-down resistor of approx ...
Page 87
... This pin will accept either a crystal, with the other pin attached to XTALO external CMOS clock. XTAL must have a crystal or clock source attached for proper operation. The crystal frequency must be 16.9344 MHz and designed for fundamental mode, parallel resonance operation. DS252PP2 TM CrystalClear Low Cost ISA Audio System series resistor CS4235 87 ...
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... These pins should be filtered, using a ferrite bead, from VD1. SGND1, SGND2, SGND3, SGND4 - Internal Digital Grounds Ground reference for the internal digital portion of the codec. Optimum layout is achieved by placing SGND1/2/3/4 on the digital ground plane with the DGND pin as shown in Figure 24 CrystalClear Low Cost ISA Audio System CS4235 DS252PP2 ...
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... Detailed information on audio testing and paths can be found in Personal Computer Audio Quality Measurements document by Dr. Steven Harris and Clif Sanchez, located at the following web address: http://www.cirrus.com/products/papers/meas/meas.html. DS252PP2 TM CrystalClear Low Cost ISA Audio System . For outputs, the tested channel is fed digital CS4235 89 ...
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... CrystalClear Low Cost ISA Audio System Description MIN Lead Count Overall Height Stand Off 0.00 b Lead Width 0.14 c Lead Thickness 0.077 Terminal Dimension 15.70 Package Body Terminal Dimension 15.70 Package Body Lead Pitch 0.40 Foot Length 0.30 T Lead Angle 0.0° CS4235 NOM MAX 100 1.66 0.20 0.26 0.127 0.177 16.00 16.30 14.0 16.00 16.30 14.0 0.50 0.60 0.50 0.70 12.0° DS252PP2 ...
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... DB 02AH, 00BH, 028H DB 022H, 0A0H, 09AH DS252PP2 TM CrystalClear Low Cost ISA Audio System ; EEPROM Validation Bytes: CS4235 ; EEPROM data length upper byte ; lower byte, Listed Size = 276 ; ACDbase Addr. Mask Length = 1 bytes ; ; MCB: IHCD ; GCB1: IFM ; Code Base Byte ...
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... End of DF for Logical Device Best Choice ; DF Acceptable Choice 1 ; End of DF for Logical Device Best Choice ; IRQ: 9 Interrupt Select Acceptable Choice 1 ; IRQ: 9,11,12,15 Interrupt Select Suboptimal Choice 1 ; End of DF for Logical Device 3 ; End of Resource Data, Resource Size = 280 CS4235 DS252PP2 ...
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... Only two modes of Hardware Volume Control are supported: 2-button, and 3-button with momen- tary mute. In addition capacitor to ground is required for switch debounce on the CS4235. 14. Pullup resistors have been added to the 4 Joystick Button pins, 3 Hardware Volume Control pins, and the MIDIN pin. ...
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