CDP68HC68W1 Intersil Corporation, CDP68HC68W1 Datasheet

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CDP68HC68W1

Manufacturer Part Number
CDP68HC68W1
Description
CMOS Serial Digital Pulse Width Modulator
Manufacturer
Intersil Corporation
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
CDP68HC68W1
Manufacturer:
INTERSIL
Quantity:
45
Part Number:
CDP68HC68W1
Manufacturer:
INTERSIL
Quantity:
45
Part Number:
CDP68HC68W1
Manufacturer:
INTERSIL
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5 510
Part Number:
CDP68HC68W1
Manufacturer:
SIEMENS
Quantity:
5 510
Part Number:
CDP68HC68W1E
Manufacturer:
INTERSIL
Quantity:
45
March 1998
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• Programmable Frequency and Duty Cycle Output
• Serial Bus Input; Compatible with Motorola/Intersil
• 8 Lead PDIP Package
• Schmitt Trigger Clock Input
• 4V to 6V Operation, -40
• 8MHz Clock Input Frequency
Pinout
Block Diagram
SPI Bus, Simple Shift-Register Type Interface
DATA
V
T
CLK
V
CS
V
SS
T
1
2
3
4
CDP68HC68W1
8 - STAGE RIPPLE
DATA REGISTER
8 - STAGE SHIFT
PULSE - WIDTH
TOP VIEW
COMPARATOR
o
COUNTER
REGISTER
(PDIP)
C to 85
|
V
Copyright
T
o
8
7
6
5
C Temperature Range
CLK
©
V
PWM
SCK
DATA
DD
Intersil Corporation 1999
RESET
LOAD
MODULATOR
INPUT CLK
CDP68HC68W1
LOGIC
SCK
CMOS Serial Digital Pulse Width Modulator
1
Description
The CDP68HC68W1 modulates a clock input to supply a
variable frequency and duty-cycle output signal. Three 8-bit
registers (pulse width, frequency and control) are accessed
serially after power is applied to initialize device operation.
The value in the pulse width register selects the high
duration of the output period. The frequency register byte
divides the clock input frequency and determines the overall
output clock period. The input clock can be further divided by
two or a low power mode may be selected by the lower two
bits in the control register. A comparator circuit allows
threshold control by setting the output low if the input at the
V
an 8 lead PDIP package (E suffix).
Ordering Information
CDP68HC68W1E
5 - STAGE 24 - STATE
T
PART NUMBER
8 - STAGE RIPPLE
CS
DATA REGISTER
8 - STAGE SHIFT
pin rises above 0.75V. The CDP68HC68W1 is supplied in
COMPARATOR
FREQUENCY
8
COUNTER
REGISTER
PWM
16
LOAD
TEMP. RANGE
24
-40 to 85
(
o
C)
CONTROL REGISTER
2 - STAGE SHIFT
8 Ld PDIP
PACKAGE
File Number
LOAD
E8.3
PKG.
NO.
1919.3

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CDP68HC68W1 Summary of contents

Page 1

... A comparator circuit allows threshold control by setting the output low if the input at the V pin rises above 0.75V. The CDP68HC68W1 is supplied lead PDIP package (E suffix). Ordering Information ...

Page 2

... NOTE measured with the component mounted on an evaluation PC board in free air Electrical Specifications PARAMETER CDP68HC68W1 10 0V Operating Voltage Range Input Voltage Range (Except V ...

Page 3

... SPI Interface Timing PARAMETER CDP68HC68W1 10 0V Serial Clock Frequency Cycle Time Enable Lead Time Enable Lag Time Serial Clock (SCK) High Time Serial Clock (SCK) Low Time Data Setup Time Data Hold Time Fall Time (70 20 200pF) ...

Page 4

... PWM-OUT = 0 (CS) FREQUENCY WORD LSB SCK DATA BIT 2 BIT 1 BIT CLK PWM-OUT CLK PWM OUT FIGURE 3. CDP68HC68W1 INTERFACE TIMING SPECIFICATIONS (CONTINUED) CDP68HC68W1 LSB MSB DON’T DON’T PWR CLOCK BIT 7 CARE CARE COUNT DIVIDE = 0 ...

Page 5

... Therefore, when using a 68HC05 microcontroller’s SPI port to provide data, program the microcontroller’s SPI control register bits CPOL, CPHA The CDP68HC68W1 latches data words after device deselection. Therefore, CS must go high (inactive) following each write to the W1. Power-Up Initialization ...

Page 6

... Assuming the frequency register contains a value of 5, the resultant PWM output would be high for 4 CLK periods, low for 2. Using the CDP68HC68W1 Programming the CDP68HC68W1 1. Select chip 2. Write to control register 3. Write to frequency register 4. Write to pulse width register 5 ...

Page 7

... CLKs high time. CDP68HC68W1 Application Example The following example was written for a system which has the CDP68HC68W1 connected to the SPI bus of a CDP68HC05C8B microcontroller. The program sets the W1 to run a divide by 200 frequency with a duty cycle of 30% by writing to the Control Register, the Frequency Data Register, ...

Page 8

... Init_W1 00120 [5] 0139 1000 bset 00121 [5] 013B 1004 bset CDP68HC68W1 SPI_xmit #99 ;set frequency to divide by 2000 SPI_xmit #29 ;set pulse width to 30% duty cycle SPI_xmit W1,PortA ;deselect the W1 which loads registers ; with values transmitted Here the CDP68HC05C8B would generally attend to other processing issues W1,PortA ...

Page 9

... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 CDP68HC68W1 E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE SYMBOL ...

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