CDP1805ACE Intersil Corporation, CDP1805ACE Datasheet

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CDP1805ACE

Manufacturer Part Number
CDP1805ACE
Description
CMOS 8-bit microprocessor with 64 bytes on-chip RAM, 5MHz
Manufacturer
Intersil Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CDP1805ACE
Manufacturer:
INTERS
Quantity:
2 856
Part Number:
CDP1805ACEX
Manufacturer:
INTERS
Quantity:
2 856
March 1997
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Features
• Instruction Time of 3.2 s, -40
• 123 Instructions - Upwards Software Compatible With
• BCD Arithmetic Instructions
• Low-Power IDLE Mode
• Pin Compatible With CDP1802 Except for Terminal 16
• 64K-Byte Memory Address Capability
• 64 Bytes of On-Chip RAM
• 16 x 16 Matrix of On-Board Registers
• On-Chip Crystal or RC Controlled Oscillator
• 8-Bit Counter/Timer
n
Ordering Information
† CDP1805AC Only
CDP1805ACE
CDP1805ACQ
CDP1805ACD
CDP1805ACDX
CDP1802
CDP1805AC
-
|
Intersil (and design) is a trademark of Intersil Americas Inc.
CDP1806ACE
CDP1806ACEX
CDP1806ACQ
CDP1806ACD
TM
CDP1806AC
o
-
C to +85
o
C
CMOS 8-Bit Microprocessor with On-Chip RAM†
TEMPERATURE RANGE
-40
-40
-40
o
o
o
C to +85
C to +85
C to +85
1
Description
The CDP1805AC and CDP1806AC are functional and per-
formance enhancements of the CDP1802 CMOS 8-bit regis-
ter-oriented microprocessor series and are designed for use
in general-purpose applications.
The CDP1805AC hardware enhancements include a 64-
byte RAM and an 8-bit presettable down counter. The
Counter/Timer which generates an internal interrupt request,
can be programmed for use in timebase, event-counting,
and
Counter/Timer underflow output can also be directed to the
Q output terminal. The CDP1806AC hardware enhance-
ments are identical to the CDP1805AC, except the
CDP1806AC contains no on-chip RAM.
The CDP1805AC and CDP1806AC software enhancements
include 32 more instructions than the CDP1802. The 32 new
software instructions add subroutine call and return capabil-
ity, enhanced data transfer manipulation, Counter/Timer con-
trol, improved interrupt handling, single-instruction loop
counting, and BCD arithmetic.
Upwards software and hardware compatibility is maintained
when substituting a CDP1805AC or CDP1806AC for other
CDP1800-series microprocessors. Pinout is identical except
for the replacement of V
the replacement of V
o
o
o
C
C
C
pulse-duration
Plastic DIP
PLCC
SBDIP
Burn-In
Burn-In
CDP1805AC,
CDP1806AC
PACKAGE
CC
CC
measurement
with V
with ME on the CDP1805AC and
DD
and Counter/Timer
on the CDP1806AC.
E40.6
N44.65
D40.6
File Number
applications.
PKG. NO.
1370.2
The

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CDP1805ACE Summary of contents

Page 1

... Pin Compatible With CDP1802 Except for Terminal 16 • 64K-Byte Memory Address Capability • 64 Bytes of On-Chip RAM † • Matrix of On-Board Registers • On-Chip Crystal or RC Controlled Oscillator • 8-Bit Counter/Timer n Ordering Information CDP1805AC CDP1806AC CDP1805ACE CDP1806ACE - CDP1806ACEX CDP1805ACQ CDP1806ACQ CDP1805ACD CDP1806ACD CDP1805ACDX - † CDP1805AC Only CAUTION: These devices are sensitive to electrostatic discharge ...

Page 2

Pinouts CDP1805AC, CDP1806AC (PDIP, SBDIP) TOP VIEW CLOCK 1 WAIT 2 CLEAR SC1 5 SC0 6 MRD 7 BUS 7 8 BUS 6 9 BUS 5 10 BUS 4 11 BUS 3 12 BUS 2 13 BUS ...

Page 3

CDP1805AC, CDP1806AC FIGURE 2. BLOCK DIAGRAM FOR CDP1805AC AND CDP1806AC 3 ...

Page 4

... +125 + .- +150 STG 0.79mm) from case for CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE MIN MAX 0.625 CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE V (NOTE 3) DD (V) MIN TYP MAX 200 5 1 0 -0 ...

Page 5

... 2 50pF - 50pF; Input -0.1V 5V, 5 PLH PHL , t PHL , t PHL 5 CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE V (NOTE 3) DD (V) MIN TYP MAX 1 2.2 2.9 3.6 5 0.9 1.9 2.8 5 0.3 0 ...

Page 6

Dynamic Electrical Specifications PARAMETER Minimum Set-Up And Hold Times (Note 2) Data Bus Input Set-Up Data Bus Input Hold DMA Set-Up DMA Hold Set-Up Hold Interrupt ...

Page 7

Timing Waveforms For Possible Operating Modes INTERNAL RAM READ CYCLE CLOCK 01 11 TPA TPB MEMORY HIGH BYTE ADDRESS MRD MWR †ME IN VALID DATA FROM MEMORY ...

Page 8

W CLOCK 00 01 TPA TPB ...

Page 9

Enhanced CDP1805AC and CDP1806AC Operation Timing Timing for the CDP1805AC and CDP1806AC is the same as the CDP1802 microprocessor series, with the following exceptions: • 4.5 Clock Cycles Are Provided for Memory Access Instead of 5. • Q Changes 1/2 ...

Page 10

MA0 to MA7 (8 Memory Address Lines) In each cycle, the higher-order byte of a 16-bit memory address appears on the memory address lines MA0-7 first. Those bits required by the memory system can be strobed into external address latches ...

Page 11

The X designator selects one of the 16 registers R(X) to “point” to the memory for an operand (or data) in certain ALU or I/O operations. The N designator can perform the following five functions depending on the type of ...

Page 12

Interrupt Servicing Register R(1) is always used as the program counter when- ever interrupt servicing is initialized. When an interrupt request occurs and the interrupt is allowed by the program (again, nothing takes place until the completion of the cur- ...

Page 13

RET MASTER S Q INTERRUPT RESET ENABLE (MIE) DIS CIE COUNTER S INTERRUPT ENABLE RESET FF CID R Q (CIE) EXTERNAL XIE S Q INTERRUPT ENABLE RESET FF R XID (XIE) FIGURE 6. INTERRUPT LOGIC CONTROL DIAGRAM ...

Page 14

STPC R TPA 32 SPMI EF1 SCMI EF2 SPM2 SCM2 DTC GEC Because of the Schmitt Trigger input oscillator can be used as shown in Figure 9. The frequency is approxi- mately 1/RC (see Figure 10 ...

Page 15

The function of the modes are defined as follows: Reset The levels on the CDP1805A and CDP1806A external signal lines will asynchronously be forced by RESET to the follow- ing states SC1, SC0 = 0,1 MRD = ...

Page 16

State Transitions The CDP1805A and CDP1806A state transitions are shown in Figure 13. Each machine cycle requires the same period of time, 8 clock pulses, except the initialization cycle (INlT) ENTER RESUME PAUSE RUN PAUSE CLOCK ...

Page 17

Instruction Set The CDP1805AC and CDP1806AC instruction summary is given in Table 1. Hexadecimal notation is used to refer to the 4-bit binary codes. In all registers, bits are numbered from the least significant bit (LSB) to the most significant ...

Page 18

TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) NO. OF MACHINE INSTRUCTION CYCLES AND IMMEDIATE SHIFT RIGHT SHIFT RIGHT WITH CARRY RING SHIFT RIGHT SHIFT LEFT SHIFT LEFT WITH CARRY RING SHIFT LEFT ARITHMETIC OPERATIONS (Note 3) ADD DECIMAL ADD ADD ...

Page 19

TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) NO. OF MACHINE INSTRUCTION CYCLES DECIMAL SUBTRACT MEMORY WITH BORROW, IMMEDIATE BRANCH INSTRUCTIONS - SHORT BRANCH SHORT BRANCH NO SHORT BRANCH (See SKP) SHORT BRANCH SHORT BRANCH IF D ...

Page 20

TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) NO. OF MACHINE INSTRUCTION CYCLES BRANCH INSTRUCTIONS - LONG BRANCH LONG BRANCH NO LONG BRANCH (See LSKP) LONG BRANCH LONG BRANCH IF D NOT 0 LONG BRANCH IF DF ...

Page 21

TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) NO. OF MACHINE INSTRUCTION CYCLES SET Q RESET Q PUSH STACK TIMER/COUNTER INSTRUCTIONS LOAD COUNTER GET COUNTER STOP COUNTER DECREMENT TIMER/COUNTER SET TIMER MODE AND START SET COUNTER MODE 1 ...

Page 22

TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) MACHINE INSTRUCTION CYCLES OUTPUT 6 OUTPUT 7 INPUT 1 INPUT 2 INPUT 3 INPUT 4 INPUT 5 INPUT 6 INPUT 7 CALL AND RETURN STANDARD CALL STANDARD RETURN NOTES: 10. Previous contents of ...

Page 23

The short-branch instructions are two or three bytes long. The first byte specifies the condition to be tested, and the second specifies the branching address, except for the branches on interrupt. For those, the first two bytes specify the ...

Page 24

TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES STATE I N MNEMONIC S1 RESET S1 INITIALIZE, NOT PROGRAMMER AC- CESSIBLE S0 FETCH IDL S1 0 1-F LDN S1 1 0-F INC ...

Page 25

TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) STATE I N MNEMONIC INP INP RET DIS ...

Page 26

TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) STATE I N MNEMONIC # LONG SKIP S1 LONG SKIP S1 LONG SKIP # LONG SKIP S1#1 ...

Page 27

TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) STATE I N MNEMONIC SPM2 SCM2 SPM1 SCM1 LDC S1 ...

Page 28

TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) STATE I N MNEMONIC # DSBI S1#1 8 0-F SCAL #2 8 0-F SCAL #3 8 0-F SCAL #4 8 0-F SCAL #5 ...

Page 29

IDL BDF IRX OUT 7 RET DIS LDXA STXD ADC LBR LBQ LBZ LBDF NOP LDX OR AND ...

Page 30

... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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