AM79C031AJC Advanced Micro Devices, AM79C031AJC Datasheet
AM79C031AJC
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AM79C031AJC Summary of contents
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Am79C02/03/031(A) Dual Subscriber Line Audio Processing Circuit (DSLAC DISTINCTIVE CHARACTERISTICS Software programmable: — SLIC impedance — Transhybrid balance — Transmit and receive gains — Equalization — Digital I/O pins — Time Slot Assigner — PCM transmit clock edge options Adaptive ...
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TABLE OF CONTENTS Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIST OF FIGURES Figure 1 Attenuation Distortion (Single Ended ...
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BLOCK DIAGRAM Analog VIN 1 Signal Processing Channel 1 (CH 1) VOUT 1 VIN 2 Signal Processing Channel 2 (CH 2) VOUT 2 SLIC CHCLK (02 & 031 only Interface ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combi- nation) is formed by a combination of the elements below. Am79C02/03/031 A Valid Combinations Am79C02 Am79C03 Am79C031 Note: * Functionality ...
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CONNECTION DIAGRAMS Top View AGND 1 RSVD VIN 1 VEE 1 VOUT 1 VCCA 1 VCCA 2 VOUT 2 VEE 2 VIN 2 AGND 2 32-Pin PLCC AGND 6 VIN VEE 1 Am79C031 9 ...
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PIN DESCRIPTIONS Pin Type Names C1 –C5 , Inputs/Outputs Control. The five SLIC control lines per channel are TTL compatible and bidirectional. They can –C5 be used to monitor or control the operation of a SLIC or ...
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Power supply for the Am79C02: AGND Analog Ground (Channel 1) 1 AGND Analog Ground (Channel 2) 2 DGND Digital Ground (Channel 1) 1 DGND Digital Ground (Channel 2) 2 PGND PCM I/O Ground VCCA +5 V Analog Power Supply (Channel ...
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ABSOLUTE MAXIMUM RATINGS Storage temperature . . . . . . . . .–60°C Ambient operating temperature . .–40°C Ambient relative humidity . . . . . . . . . . . . . 5% to 100% V with ...
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ELECTRICAL CHARACTERISTICS over operating range unless otherwise noted Typical values are for T = 25°C and nominal supply voltages. Minimum and maximum specifications are over the A temperature and supply voltage ranges shown in Operating Ranges. Symbol Parameter Descriptions V ...
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Transmission Characteristics The gain of the receive path is defined when a 0 dBm0, 1014 Hz PCM sine wave input results in a nominal 1.55 Vrms for µ-law or 1.56 Vrms for A-law analog output. The ...
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Attenuation Distortion 2 Attenuation (dB) 1 0.125 0 –0.125 (transmit only) 200 300 Figure 1. Attenuation Distortion (Single Ended) Group Delay Distortion For either transmission path, the group delay distortion is within the limits shown in Figure 2. The minimum ...
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Variation of Gain with Input Level The gain deviation relative to the gain at –10 dBm0 is within the limits shown if Figure 3 for either transmission path when the input is a sine wave signal of frequency 1014 Hz. ...
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Discrimination against Out-of-Band Input Signals When an out-of-band sine wave signal with frequency f and level A is applied to the analog input, there may be frequency components below 4 kHz at the digital output, caused by the out-of-band signal. ...
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Discrimination against 12 kHz and 16 kHz Metering Signals If the DSLAC device is used in a metering application where 12 kHz or 16 kHz tone bursts are injected onto the telephone line toward the subscriber, a portion of those ...
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Overload Compression Figure 7 shows the acceptable region of operation for input signal levels above the reference input power (0 dBm0). The conditions for this figure are: ( < GX PCM input; and (4) measurement analog-to-analog ...
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SWITCHING CHARACTERISTICS over operating range unless otherwise noted Microprocessor Interface Min and max values are valid for all digital outputs with a 150 pF load, except C1–C5 with load. Pull-up resistors of 360 are attached to TSCA ...
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Master Clock For 2.048 MHz ±100 ppm or 4.096 MHz ±100 ppm operation: No. Symbol 35 t Master Clock Period (2.048 MHz) MCY Master Clock Period (4.096 MHz Rise Time of Clock MCR 37 t Fall Time of ...
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Microprocessor Interface (Input Mode DCLK Data DIN Valid Outputs C5–C1 Microprocessor Interface (Output Mode DCLK Three-State Data OH DOUT ...
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PCM Highway Timing for (Transmit on Negative PCLK Edge PCLK 26 FS TSCA/ TSCB 30 DXA/DXB DRA/DRB 20 Time Slot Zero Clock Slot Zero ...
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PCM Highway Timing for (Transmit on Positive PCLK Edge PCLK 26 FS TSCA/ TSCB DXA/DXB DRA/DRB Note: In this mode, the PCM transmit timing is compatible with other CODEC IC’s. Time Slot Zero ...
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Operating the DSLAC Device The following describes the operation of either channel of the DSLAC device. The description is valid for either Channel VIN in this data sheet refers to either VIN or VIN , VOUT refers ...
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VIN Decimator ADC AX & HPF AISN Analog Loopback * Digital (also uses Loop- RX Cutoff) back (#21) (#13) * Inter DAC polator VOUT * programmable blocks Distortion Correction and Equalization The DSLAC device contains programmable filters ...
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TSC output turned on. For example, if the PCLK frequency is 1.544 MHz ( and the transmit clock slot is ...
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Command Description and Formats Microprocessor Interface Description A microprocessor may be used to program the DSLAC device and control its operation using the Microproces- sor Interface (MPI). Data programmed previously may be read out for verification. For each channel, com- ...
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Summary of MPI Commands** C# Hex Description 1. 00 Deactivate (Standby mode Reset Operation 4. 08 Reset to Normal Conditions 5. 0E Activate 6. 1* MCLK Selection 7. 40 Write TX Time Slot & PCM ...
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COMMAND STRUCTURE This section describes in detail each of the MPI commands. Each of the commands is shown along with the format of any additional data bytes that follow. For details of the filter coefficients of the for C Description ...
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MCLK Selection (10h/12h) Command MCLK may be selected to operate from a 2.048 MHz or 4.096 MHz external clock. MCLK selection on either channel affects both channels Write Transmit Time Slot and ...
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Write Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge (44h) Command Input Data TCS: Transmit Clock Slot number 0–7 RCS: Receive Clock Slot number 0–7 XE=0 Transmit on negative edge of PCLK Transmit on ...
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Read AISN, PCM Delay, and Analog Gains (51h) Command Output Data 15. Write SLIC Output Register (52h) Command Input Data C1 through C5 are set The data appears latched on the C1 through C5 SLIC ...
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Read SLIC Input/Output Direction, Channel Status Bit, and Power Interrupt Bit (55h) Command Output Data Power Interruption Channel Status CSTAT = 0 CSTAT = ...
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Write Operating Functions (60h) Command Input Data Adaptive B Filter ABF = 0* PCD = 1 A-law/µ-law A A Filter EGR = 0* EGR = 1 GX Filter EGX = 0* EGX = 1 ...
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Write Operating Conditions (70h) Command Input Data Cut off Transmit Path CTP = 0* CTP = 1 Cut off Receive Path CRP = 0* CRP = 1 High-Pass Filter HPF = 0* HPF = 1 Receive Path Gain RG ...
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Write GX Filter Coefficients (80h) Command Input Data Byte 1 Input Data Byte 2 The coefficient for the GX filter is defined as 25. Read GX Filter Coefficients (81h) Command Output Data Byte 1 Output Data Byte ...
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Write Z Filter Coefficients (84h) Command Input Data Byte 1 Input Data Byte 2 Input Data Byte 3 Input Data Byte 4 Input Data Byte 5 Input Data Byte 6 Input Data Byte 7 Input Data Byte 8 Input ...
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Write B Filter Coefficients (86h) Command Input Data Byte 1 Input Data Byte 2 Input Data Byte 3 Input Data Byte 4 Input Data Byte 5 Input Data Byte 6 Input Data Byte 7 Input Data Byte 8 Input ...
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Read B Filter Coefficients (87h) Command Output Data Byte 1 Output Data Byte 2 Output Data Byte 3 Output Data Byte 4 Output Data Byte 5 Output Data Byte 6 Output Data Byte 7 Output Data Byte 8 Output ...
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Read X Filter Coefficients (89h) Command Output Data Byte 1 Output Data Byte 2 Output Data Byte 3 Output Data Byte 4 Output Data Byte 5 Output Data Byte 6 Output Data Byte 7 Output Data Byte 8 Output ...
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Read R Filter Coefficients (8Bh) Command Output Data Byte 1 Output Data Byte 2 Output Data Byte 3 Output Data Byte 4 Output Data Byte 5 Output Data Byte 6 Output Data Byte 7 Output Data Byte 8 Output ...
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Read Error Level Threshold (8Fh) Command Output Data Byte 1 40. Write GZ Filter Coefficient (92h) Command Input Data RSVD Reserved. Always write as 0, but 0 is not guaranteed when read. The coefficient, GZ, is defined as: GZ ...
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Read Adaptive B Filter Coefficients (91h) New to Revision E Command Output data Output data Output data Output data Output data 44. Write Operating Functions 2 (64h) New to Revision E Command Input data Chopper Clock Control CHP = ...
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The value Equation 3 represents a decimal i number that is broken down into a sum of successive values of: –0 –1 ±1.0 multiplied ±1.0 multiplied by 1, ...
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In the continuous Adaptation mode, the algorithm is switched on (via MPI Command 19) after a call is con- nected and remains on until the call ends. In this way, the B filter is continually being optimized to the re- ...
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A-Law and -Law Companding Table 1 and Table 2 show the companding definitions used for A-law and -law PCM encoding Intervals Segment x Interval Segment Number Size End Points 128 ...
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Intervals Value at Segment x Interval Segment Number Size End Points 256 128 ...
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APPLICATIONS The DSLAC device performs a programmable codec/ filter function for two telephone lines. It interfaces to the telephone lines through either a transformer or an electronic SLIC, such as the AMD SLIC devices. The DSLAC device provides latched digital ...
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PHYSICAL DIMENSIONS PL032 .485 .447 .495 .453 .585 Pin 1 I.D. .595 .547 .553 .050 REF. .026 .032 TOP VIEW PL044 .685 .695 .650 .656 Pin 1 I.D. .685 .695 .650 .656 .026 .050 REF .032 TOP VIEW REVISION SUMMARY ...
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... Page 45, Table 2, changed values in column 7. The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifi- cations and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intel- lectual property rights is granted by this publication. Except as set forth in AMD’ ...