CY7C1360A-166AC Cypress Semiconductor Corporation., CY7C1360A-166AC Datasheet

CY7C1360A-166AC

Manufacturer Part Number

CY7C1360A-166AC

Description

256K x 36 pipelined SRAM, 166MHz

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C1360A-166AC.pdf (27 pages)

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Features

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced tri-

ple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

The

GVT71512D18 SRAMs integrate 262,144x36 and 524,288x18

SRAM cells with advanced synchronous peripheral circuitry

Selection Guide

Cypress Semiconductor Corporation

Maximum Access Time (ns)

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns

• Fast clock speed: 225, 200, 166, and 150 MHz

• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns

• Optimal for depth expansion (one cycle chip deselect

• 3.3V –5% and +10% power supply

• 3.3V or 2.5V I/O supply

• 5V tolerant inputs except I/Os

• Clamp diodes to V

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Multiple chip enables for depth expansion:

• Address pipeline capability

• Address, data, and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst se-

• Automatic power-down for portable applications

• JTAG boundary scan for B and T package version

• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid

to eliminate bus contention)

three chip enables for TA package version and two chip

enables for B and T package versions

quence)

Array) and 100-pin TQFP packages

CY7C1360A/GVT71256D36

at all inputs and outputs

and

Commercial

•

3901 North First Street

CY7C1362A/

256K x 36/512K x 18 Pipelined SRAM

PRELIMINARY

71256D36-4.4

71512D18-4.4

7C1360A-225

7C1362A-225

570

2.5

and a 2-bit counter for internal burst operation. All synchro-

nous inputs are gated by registers controlled by a posi-

tive-edge-triggered Clock Input (CLK). The synchronous in-

puts include all addresses, all data inputs, address-pipelining

Chip Enable (CE), depth-expansion Chip Enables (CE

ables (BWa, BWb, BWc, BWd, and BWE), and global write

(GW). However, the CE

the TA package version.

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). The data outputs (Q), enabled by

OE, are also asynchronous.

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address Status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance Pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate self-timed WRITE cycle. WRITE cycles can be one

to four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BWa

controls DQa. BWb controls DQb. BWc controls DQc. BWd

controls DQd. BWa, BWb, BWc, and BWd can be active only

with BWE being LOW. GW being LOW causes all bytes to be

written. The x18 version only has 18 data inputs/outputs (DQa

and DQb) along with BWa and BWb (no BWc, BWd, DQc, and

DQd).

For the B and T package versions, four pins are used to imple-

ment JTAG test capabilities: Test Mode Select (TMS), Test Da-

ta-In (TDI), Test Clock (TCK), and Test Data-Out (TDO). The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation. The TA package version

does not offer the JTAG capability.

The

GVT71512D18 operate from a +3.3V power supply. All inputs

and outputs are LVTTL compatible.

), burst control inputs (ADSC, ADSP , and ADV), Write En-

CY7C1360A/GVT71256D36

•

7C1360A-200

7C1362A-200

71256D36-5

71512D18-5

San Jose

510

3.0

CY7C1360A/GVT71256D36

CY7C1362A/GVT71512D18

chip enable input is only available for

•

7C1360A-166

7C1362A-166

71256D36-6

71512D18-6

CA 95134

425

3.5

and

•

71256D36-6.7

71512D18-6.7

7C1360A-150

7C1362A-150

408-943-2600

CY7C1362A/

May 9, 2001

380

3.5

and

Related parts for CY7C1360A-166AC

CY7C1360A-166AC Summary of contents

Page 1

... LVTTL compatible. 7C1360A-225 7C1360A-200 71256D36-4.4 71256D36-5 7C1362A-225 7C1362A-200 71512D18-4.4 71512D18-5 2.5 Commercial 570 10 • 3901 North First Street • San Jose CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 chip enable input is only available for 2 and CY7C1362A/ 7C1360A-166 7C1360A-150 71256D36-6 71256D36-6.7 7C1362A-166 7C1362A-150 71512D18-6 71512D18-6.7 3.0 3.5 3.5 ...

Page 2

... ENABLE Input Register Address Register OUTPUT REGISTER CLR D Q Binary Counter & Logic [1] BYTE b WRITE D Q BYTE a WRITE D Q ENABLE Input Register Address Register OUTPUT REGISTER D Q CLR Binary Counter & Logic 2 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 DQa,DQb DQc,DQd DQa,DQb ...

Page 3

... DQb 23 DQa 57 DQb 24 DQa CCQ 27 CCQ 53 DQa DQa NC 29 DQa CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 DPa DQa 73 DQa DQa 69 68 DQa 67 V CY7C1362A/GVT71512D18 (512K x 18) ...

Page 4

... V NC BWa SS DQb V BWE DQb MODE TMS TDI TCK TDO 4 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 CCQ DQb DQb SS DQb DQb SS DQb V SS CCQ DQb DQb DQb DQb CCQ DQa DQa SS ...

Page 5

... Linear Burst HIGH on this pin selects Interleaved Burst. ZZ Input- Snooze: This active HIGH input puts the device in low Asynchronous power consumption standby mode. For normal opera- tion, this input has to be either LOW or NC (No Connect). 5 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 Description ...

Page 6

... All synchronous inputs must meet set-up and hold times around the clock’s rising edge. CE Input- Chip Enable: This active LOW input is used to enable the Synchronous device and to gate ADSP . 6 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 Description Description . ...

Page 7

... IEEE 1149.1 test output. LVTTL-level output. Not avail- able for TA package version. V Supply Core power Supply: +3.3V –5% and +10 Ground Ground: GND I/O Supply Output Buffer Supply: +2.5V or +3.3V. CCQ Connect: These signals are not internally connected. User can leave it floating or connect CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 Description ...

Page 8

... CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 Second Third Fourth Address Address Address (internal) (internal) (internal) A...A01 A...A10 A...A11 A...A10 A...A11 A...A00 A...A11 A...A00 A...A01 A...A00 A...A01 A...A10 CLK L-H X ...

Page 9

... The bypass register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the device TAP to another device in the scan chain with minimum delay. The bypass register is set LOW (V when the BYPASS instruction is executed. 9 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 BWb BWc BWd X ...

Page 10

... TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Reserved Do not use these instructions. They are reserved for future use. 10 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 plus The ...

Page 11

... The 0/1 next to each state represents the value at TMS at the rising edge of TCK. PRELIMINARY 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- Figure 1. TAP Controller State Diagram 11 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- [11] ...

Page 12

... OLC [13, 15 100 A OHC [13 8.0 mA OLT [13 8.0 mA OHT /2, Undershoot: V (AC)<–0.5V for t<t /2, Power-up KHKH . Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 0 Selection Circuitry [12] Min. Max. 2 0.3 CC –0.3 0.8 –5.0 5.0 –30 30 –5.0 5 ...

Page 13

... CS CH 17. Test conditions are specified using the load in TAP AC test conditions. PRELIMINARY [16, 17] Over the Operating Range Description 13 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 Min. Max Unit MHz 8 ns ...

Page 14

... TEST MODE SELECT (TMS) TEST DATA IN (TDI) TEST DATA OUT (TDO) PRELIMINARY 1 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 ALL INPUT PULSES 3.0V 1.5V 1 ...

Page 15

... Do not use these instructions; they are reserved for future use. 111 Places the bypass register between TDI and TDO. This instruction does not affect device operations. 15 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 Description Reserved for revision number. Defines depth of 256K or 512K words. Defines width of x36 or x18 bits. ...

Page 16

... CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 (continued) Signal Name TQFP Bump BWa 93 5L BWb 94 5G BWc 95 3G BWd 100 2A DQc ...

Page 17

... CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 (continued) Signal Name TQFP Bump ID CLK BWa 93 5L BWb 100 2A DQb 8 1D DQb ...

Page 18

... Max. CLK frequency = 0 CC Device deselected; all inputs < > Max CLK cycle time > t Min. KC Description Test Conditions T = 25° MHz 3. CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 Ambient [18] Temperature 3.3V –5% / +10% Min. Max. 2.0 V +0.3 CC 2.0 4.6 –0.5 0.8 –5 5 –30 30 – ...

Page 19

... AC Test Loads and Waveforms for 2. 1.25V t (a) PRELIMINARY Test Conditions 4-layer PCB 317 3. 351 (b) 2. CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 Symbol TQFP Typ. Units ALL INPUT PULSES 90% 90% 10% 10% 1.0 ns (c) ALL INPUT PULSES 90% 90% 10% 10% 1.0 ns 1.0 ns (c) C/W C/W 1 ...

Page 20

... CCQ V = 2.5V 3.0 CCQ 0 0 2.5 [28] 1.5 1.5 [28] 0.5 0.5 Output Low Voltage I (mA) Max –105 –0.5 –105 0 –105 0.4 –83 0.8 –70 1.25 –30 1.6 –10 2.8 0 3.2 0 3.4 is less than t and t is less than t KQHZ KQLZ OEHZ 20 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 -5 -6 -6.7 166 MHz 150 MHz Max. Min. Max. Min. Max. 6.0 6.7 2.4 2.6 2.4 2.6 3.0 3.5 3.5 3.5 4.0 4.5 1.25 1. 3.0 1.25 4.0 1.25 4.0 3.0 3.5 3.5 3.5 4.0 4 2.5 3.5 3.5 1.5 2 ...

Page 21

... For the X18 product, there are only BWa and BWb for byte write control. PRELIMINARY OEQ t OELZ Q(A1) Q(A2) Q(A2+1) SINGLE READ , and CE are active CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) BURST READ is only available for TA package version. 2 ...

Page 22

... Switching Waveforms (continued) [29, 30] Write Timing CLK t S ADSP# ADSC ADDRESS A1 t BWa#, BWb#, H BWc#, BWd#, BWE# GW# CE# ADV# OE# t KQX DQ Q SINGLE WRITE PRELIMINARY OEHZ D(A1) D(A2) D(A2+1) D(A2+1) BURST WRITE 22 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 A3 D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2) BURST WRITE ...

Page 23

... Switching Waveforms (continued) [29, 30] Read/Write Timing CLK t S ADSP# ADSC ADDRESS A2 t BWa#, BWb#, BWc#, BWd#, BWE#, GW# CE# ADV# OE# DQ PRELIMINARY Q(A1) Q(A2) D(A3) Single Reads Single Write 23 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 A5 Q(A4) Q(A4+1) Q(A4+2) D(A5) D(A5+1) Burst Read Burst Write ...

Page 24

... CY7C1360A-225AJC/ GVT71256D36T-4.4 CY7C1360A-225AC/ GVT71256D36TA-4.4 CY7C1360A-225BGC/ GVT71256D36B-4.4 200 CY7C1360A-200AJC/ GVT71256D36T-5 CY7C1360A-200AC/ GVT71256D36TA-5 CY7C1360A-200BGC/ GVT71256D36B-5 166 CY7C1360A-166AJC/ GVT71256D36T-6 CY7C1360A-166AC/ GVT71256D36TA-6 CY7C1360A-166BGC/ GVT71256D36B-6 150 CY7C1360A-150AJC/ GVT71256D36T-6.7 CY7C1360A-150AC/ GVT71256D36TA-6.7 CY7C1360A-150BGC/ GVT71256D36B-6.7 PRELIMINARY Package Name Package Type A101 100-Lead 1.4 mm Thin Quad Flat Pack A101 100-Lead ...

Page 25

... Thin Quad Flat Pack A101 100-Lead 1.4 mm Thin Quad Flat Pack BG119 119-Lead FBGA ( 2.4 mm) A101 100-Lead 1.4 mm Thin Quad Flat Pack A101 100-Lead 1.4 mm Thin Quad Flat Pack BG119 119-Lead FBGA ( 2.4 mm) 25 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 Operating Range Commercial ...

Page 26

... Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 PRELIMINARY 26 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 51-85050-A ...

Page 27

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY 119-Lead FBGA ( 2.4 mm) BG119 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 51-85115 ...

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