LXT386LE Intel Corporation, LXT386LE Datasheet
LXT386LE
Related parts for LXT386LE
LXT386LE Summary of contents
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LXT386 QUAD T1/E1/J1 Transceiver The LXT386 is a quad short haul Pulse Code Modulation (PCM) transceiver for use in both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications. It incorporates four independent receivers and four independent transmitters in a single ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. ...
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Contents 1.0 Features ......................................................................................................................... 7 2.0 Pin Assignments and Signal Description 3.0 Functional Description 3.1 Initialization..........................................................................................................22 3.1.1 Reset Operation .....................................................................................22 3.2 Receiver ..............................................................................................................23 3.2.1 Loss of Signal Detector ..........................................................................24 3.2.1.1 E1 Mode ....................................................................................24 3.2.1.2 T1 Mode ....................................................................................24 3.2.1.3 Data Recovery ...
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LXT386 — QUAD T1/E1/J1 Transceiver 5.3 TAP Controller..................................................................................................... 45 5.4 JTAG Register Description.................................................................................. 47 5.4.1 Boundary Scan Register (BSR).............................................................. 48 5.5 Device Identification Register (IDR) .................................................................... 50 5.5.1 Bypass Register (BYR) .......................................................................... 50 5.5.2 Analog Port Scan Register (ASR) .......................................................... ...
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Output Jitter for CTR12/13 applications .............................................................. Plastic Ball Grid Array (PBGA) Package Dimensions ....................................76 37 100 Pin Low Quad Flat Packages (LQFP) Dimensions ......................................77 Tables 1 Pin Assignments and Signal Descriptions...........................................................11 2 Line Length Equalizer Inputs...............................................................................27 3 ...
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LXT386 — QUAD T1/E1/J1 Transceiver 45 JTAG Timing Characteristics .............................................................................. 61 46 Intel Mode Read Timing Characteristics ............................................................. 61 47 Intel Mode Write Timing Characteristics ............................................................. 63 48 Motorola Bus Read Timing Characteristics......................................................... 65 49 Motorola Mode Write Timing Characteristics ...
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Features • Single rail 3.3V supply with 5V tolerant inputs • Low power consumption of 150mW per channel (typical) • Superior crystal-less jitter attenuator — Meets ETSI CTR12/13, ITU G.736, G.742, G.823 and AT&T Pub 62411 specifications — Optimized ...
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LXT386 — QUAD T1/E1/J1 Transceiver Figure 2. LXT386 Detailed Block Diagram JTAG SERIAL/ PARALLEL PORT RTIP3 RRING3 TTIP3 TRING3 RTIP2/RRING2 TTIP2/TRING2 RTIP1/RRING1 TTIP1/TRING1 RTIP0 RRING0 MUX TTIP0 TRING0 HARDWARE / SOFTWARE CONTROL (JTAG INTERFACE) Transceiver 3 ...
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... Rev # LXT386LE ...
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LXT386 — QUAD T1/E1/J1 Transceiver Figure 4. LXT386 Plastic Ball Grid Array (PBGA) 160 Ball Assignments N/C N/C N/C TVCC B GND GND GND TVCC C N/C N/C N/C VCC D GND GND GND VCC ...
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Table 1. Pin Assignments and Signal Descriptions Ball # Pin # Symbol PBGA LQFP E1 78 MCLK E2 79 MODE DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 1. Pin Assignments and Signal Descriptions (Continued) Ball # Pin # Symbol PBGA LQFP DI: Digital Input; DO: Digital Output; DI/O: ...
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Table 1. Pin Assignments and Signal Descriptions (Continued) Ball # Pin # Symbol PBGA LQFP G2 90 D0/LOOP0 H3 91 D1/LOOP1 H2 92 D2/LOOP2 J4 93 D3/LOOP3 J3 94 D4/DLOOP0 J2 95 D5/DLOOP1 J1 96 D6/DLOOP2 K1 97 D7/DLOOP3 L1 ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 1. Pin Assignments and Signal Descriptions (Continued) Ball # Pin # Symbol PBGA LQFP N1 19 TCLK0 TPOS0 TDATA0 TNEG0 UBS0 1. DI: Digital Input; DO: Digital Output; DI/O: Digital ...
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Table 1. Pin Assignments and Signal Descriptions (Continued) Ball # Pin # Symbol PBGA LQFP P1 22 RCLK0 RPOS0 RDATA0 RNEG0 BPV0 K4 25 LOS0 K2 99 MUX N4 TVCC0 1. DI: Digital Input; ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 1. Pin Assignments and Signal Descriptions (Continued) Ball # Pin # Symbol PBGA LQFP N5 27 TTIP0 P5 28 TRING0 N6 TGND0 P7 30 RTIP0 N7 31 RRING0 L6 TGND1 ...
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Table 1. Pin Assignments and Signal Descriptions (Continued) Ball # Pin # Symbol PBGA LQFP TNEG3/ N12 55 UBS3 TPOS3/ N13 56 TDATA3 N14 57 TCLK3 K12 58 LOS2 RNEG2/ M12 59 BPV2 RPOS2/ M13 60 RDATA2 M14 61 RCLK2 ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 1. Pin Assignments and Signal Descriptions (Continued) Ball # Pin # Symbol PBGA LQFP DS/ WR/ J14 3 SDI/ LEN0 J13 2 RD/ LEN1 ALE/ SCLK/ J12 82 AS/ LEN2 1. ...
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Table 1. Pin Assignments and Signal Descriptions (Continued) Ball # Pin # Symbol PBGA LQFP CS/ J11 98 JASEL MOT/INTL/ H12 1 CODEN G13 76 AT2 H13 77 AT1 G12 72 TRST F11 71 TMS F14 69 TCK F13 73 ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 1. Pin Assignments and Signal Descriptions (Continued) Ball # Pin # Symbol PBGA LQFP E13 84 CLKE 2 N/C 100 RESET A6 12, 13 ...
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Table 1. Pin Assignments and Signal Descriptions (Continued) Ball # Pin # Symbol PBGA LQFP A4, B4, C4, C11 VCC 67, 68, 75, D4, D11, G1, G14, H1, H14 A11, B11 - TVCC ...
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LXT386 — QUAD T1/E1/J1 Transceiver 3.0 Functional Description Figure simplified block diagram of the LXT386. The LXT386 is a fully integrated quad line interface unit designed for T1 1.544 Mbps and E1 2.048 Mbps short haul applications. ...
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... Pub 62411 and ITU G.823, as shown in Test Specifications, Depending on the options selected, recovered clock and data signals may be routed through the jitter attenuator, through the B8ZS/HDB3/AMI decoder, and may be output to the framer as either bipolar or unipolar data. Datasheet QUAD T1/E1/J1 Transceiver — LXT386 RESET LXT386LE Figure 33. 23 ...
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LXT386 — QUAD T1/E1/J1 Transceiver 3.2.1 Loss of Signal Detector The loss of signal detector in the LXT386 uses a dedicated analog and digital loss of signal detection circuit independent of its internal data slicer comparators and complies ...
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E1 Mode One detection mode suitable for both ETSI and ITU is available when the cleared to zero. If the LACS register bit is set to one, see errata 10.3 to implement this: ETSI ETS300233 and G.775 detection The ...
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LXT386 — QUAD T1/E1/J1 Transceiver Figure 6. 50% AMI Encoding ...
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Table 2. Line Length Equalizer Inputs LEN2 LEN1 LEN0 Line length from LXT386 to DSX-1 cross-connect point. 2. Maximum cable ...
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LXT386 — QUAD T1/E1/J1 Transceiver A capacitor, charged via a measure of the driver output current and discharged by a measure of the maximum allowable current, is used to detect a secondary short failure. Secondary shorted lines draw excess current, ...
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Figure 7. External Transmit/Receive Line Circuitry TVCC TVCC 0.1 F 0.1 F 3.3V 3.3V VCC VCC 0.1 F 0.1 F GND GND 1 Common decoupling capacitor for all TVCC and TGND pins. 1 Common ...
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LXT386 — QUAD T1/E1/J1 Transceiver 3.6 Jitter Attenuation A digital Jitter Attenuation Loop (JAL) combined with a FIFO provides Jitter attenuation. The JAL is internal and requires no external crystal nor high-frequency (higher than line rate) reference clock. In Host ...
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Figure 8. Jitter Attenuator Loop TPOS RPOSi TNEG RNEGi TCLK RCLKi JASEL0 MCLK 3.7 Loopbacks The LXT386 offers three loopback modes for diagnostic purposes. In hardware mode, the loopback mode is selected with the LOOPn pins. In software ...
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LXT386 — QUAD T1/E1/J1 Transceiver 3.7.2 Digital Loopback The digital loopback function is available in software and hardware mode. When selected, the transmit clock and data inputs (TCLK, TPOS & TNEG) are looped back and output on the RCLK, RPOS ...
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Figure 12. TAOS Data Path MCLK TAOS mode TCLK TPOS TNEG RCLK RPOS RNEG * If Enabled Figure 13. TAOS with Analog Loopback MCLK TCLK TPOS TNEG RCLK RPOS RNEG * If Enabled 3.8 G.772 Performance Monitoring The LXT386 can ...
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LXT386 — QUAD T1/E1/J1 Transceiver 3.9 Hitless Protection Switching (HPS) The LXT386 transceivers include an output driver tristatability feature for T1/E1 redundancy applications. This feature greatly reduces the cost of implementing redundancy protection by eliminating external relays. Please refer to ...
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Interfacing with 5V logic The LXT386 can interface directly with 5V logic. The internal input pads are tolerant to 5V outputs from TTL and CMOS family devices. 3.12 Parallel Host Interface The LXT386 incorporates a highly flexible 8-bit parallel ...
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LXT386 — QUAD T1/E1/J1 Transceiver The R/W signal indicates the direction of the data transfer. The DS signal is the timing reference for all data transfers and typically has a duty cycle of 50%. A read cycle is indicated by ...
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INT pin is asserted Low. The output stage of the INT pin consists only of a pull-down device; an external pull-up resistor of approximately 10k ohm is required to support wired-OR operation. 3.13.2 Interrupt Clear When an interrupt ...
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LXT386 — QUAD T1/E1/J1 Transceiver 4.0 Register Descriptions Table 6. Serial and Parallel Port Register Addresses Name Symbol ID Register Analog Loopback ALOOP Remote Loopback RLOOP TAOS Enable TAOS LOS Status Monitor LOS DFM Status Monitor DFM LOS Interrupt Enable ...
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Table 7. Register Bit Names (Continued) Register Name Sym RW LOS Status Monitor LOS R DFM Status Monitor DFM R LOS Interrupt Enable LIE R/W DFM Interrupt Enable DIE R/W LOS Interrupt Status LIS R DFM Interrupt Status DIS R ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 10. Remote Loopback Register, RLOOP (02H) Bit Name 3-0 RL3-RL0 Setting a bit to “1” enables remote loopback for transceivers 3-0 respectively. Table 11. TAOS Enable Register, TAOS (03H) 1 Bit Name Setting a ...
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Table 16. LOS Interrupt Status Register, LIS (08H) Bit Name These bits are set to “1” every time a LOS status change has occurred since the last clear 3-0 LIS3-LIS0 interrupt in transceivers 3-0 respectively. Table 17. DFM Interrupt Status ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 22. Automatic TAOS Select Register, ATS (0EH) 1 Bit Name Setting a bit to “1” enables automatic TAOS generation whenever a LOS condition is 3-0 ATS3-ATS0 detected in the respective transceiver. 7-4 - Write ...
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Table 24. Pulse Shaping Indirect Address Register, PSIAD (10H) 1 Bit Name The three bit value written to these bits determine the channel to be addressed channel channel 1 0-2 LENAD 0 channel ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 28. AIS Interrupt Enable Register, AISIE (14H) 1 Bit Name 3-0 AISIE3-AISIE0 Transceiver 3-0 AIS interrupts are enabled by writing a “1” to the respective bit. 7-4 - Write “0” to these positions for ...
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JTAG Boundary Scan 5.1 Overview The LXT386 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy access to the interface pins for board testing purposes. In addition to the traditional IEE1149.1 digital boundary scan capabilities, the LXT386 ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 30. TAP State Description State In this state the test logic is disabled. The device is set to normal operation mode. While in this state, the Test Logic Reset instruction register is set to ...
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Figure 16. JTAG State Diagram 1 TEST-LOGIC RESET RUN TEST/IDLE 5.4 JTAG Register Description The following paragraphs describe each of the registers represented in Datasheet QUAD T1/E1/J1 Transceiver — LXT386 1 SELECT- CAPTURE- ...
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LXT386 — QUAD T1/E1/J1 Transceiver 5.4.1 Boundary Scan Register (BSR) The BSR is a shift register that provides access to all the digital I/O pins. The BSR is used to apply and read test patterns to/from the board. Each pin ...
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Example 1. Boundary Scan Register (BSR) (Continued) Pin I/O Bit # Signal Type Symbol LOOP0 I/O LOOP1 I/O LOOP1 I/O LOOP2 I/O LOOP2 I/O LOOP3 I/O LOOP3 I/O LOOP4 I/O LOOP4 I/O LOOP5 I/O LOOP5 I/O LOOP6 I/O LOOP6 I/O ...
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LXT386 — QUAD T1/E1/J1 Transceiver Example 1. Boundary Scan Register (BSR) (Continued) Pin I/O Bit # Signal Type RPOS0 O RPOS0 N/A - HIZ0 RNEG0 O RNEG0 LOS0 O LOS0 5.5 Device Identification Register (IDR) The IDR register provides access ...
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Table 32. Analog Port Scan Register (ASR) ASR Control Code 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 5.5.3 Instruction Register (IR) The bit shift register that loads ...
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LXT386 — QUAD T1/E1/J1 Transceiver Figure 17. Analog Test Port Application RTIP3 RRING3 TTIP3 TRING3 RTIP2 RRING2 TTIP2 TRING2 RTIP0 1K RRING0 1K AT2 AT1 52 JTAG Port ASR Register Transceiver 3 Transceiver 2 Transceiver 0 Datasheet ...
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Test Specifications Note: Table 34 through Table 53 specifications of the LXT386 and are guaranteed by test except, where noted, by design. The minimum and maximum values listed in recommended operating conditions specified in Table 34. Absolute Maximum Ratings ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 35. Recommended Operating Conditions (Continued) Parameter Average Transmitter Power Supply Current Mode 1, 4 Average Digital Power Supply Current Output load at TTIP and TRING Mode TVCC Load 75 E1 ...
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Table 36. DC Characteristics (Continued) Parameter Input leakage current Tri state leakage current Tri state output current Line short circuit current Input Leakage (TMS, TDI, TRST) 1. Output drivers will output CMOS logic levels into CMOS loads. Table 37. E1 ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 38. E1 Receive Transmission Characteristics (Continued) Parameter Data decision threshold Data slicer threshold Loss of signal threshold LOS hysteresis Consecutive zeros before loss of signal LOS reset Low limit 1Hz to 20Hz input jitter ...
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Table 39. T1 Transmit Transmission Characteristics (Continued) Parameter Output power @ 772 KHz 2 levels @ 1544 KHz 51kHz to 102 kHz Transmit return 102 kHz to 2.048 MHz 1 loss 2.048 MHz to 3.072 MHz Bipolar mode Transmit path ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 41. Jitter Attenuator Characteristics Parameter JACF = 0 E1 jitter attenuator 3dB corner frequency, host 1 mode JACF = 1 JACF = 0 T1 jitter attenuator 3dB corner frequency, host 1 mode JACF = ...
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Table 42. Analog Test Port Characteristics Parameter 3 dB bandwidth Input voltage range Output voltage range Table 43. Transmit Timing Characteristics Parameter E1 Master clock frequency T1 Master clock tolerance Master clock duty cycle E1 Output pulse width T1 E1 ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 44. Receive Timing Characteristics Parameter Clock recovery capture range 1 Receive clock duty cycle 1 Receive clock pulse width Receive clock pulse width Low time Receive clock pulse width High time 4 Rise/fall time ...
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Table 45. JTAG Timing Characteristics Parameter Cycle time J-TMS/J-TDI to J-TCK rising edge time J-CLK rising to J-TMS/L-TDI hold time J-TCLK falling to J-TDO valid Figure 20. JTAG Timing TCK TMS TDI TDO Table 46. Intel Mode Read Timing Characteristics ...
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LXT386 — QUAD T1/E1/J1 Transceiver Figure 21. Non-Multiplexed Intel Mode Read Timing ALE (pulled High INT Tristate RDY 62 tSAR ADDRESS tSCSR tVRD tPRD DATA OUT tDRDY tVRDY tHAR tHCSR tZRD tINT ...
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Figure 22. Multiplexed Intel Read Timing tVL ALE CS RD tSALR ADDRESS AD7-AD0 INT tDRDY Tristate RDY Table 47. Intel Mode Write Timing Characteristics 2 Parameter Address setup time to latch Valid address latch pulse width Latch active to active ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 47. Intel Mode Write Timing Characteristics (Continued) 2 Parameter Valid write signal pulse width Inactive write to inactive INT delay time 3 Chip select to RDY delay time Active ready Low time 3 Inactive ...
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Figure 24. Multiplexed Intel Mode Write Timing ALE tVL CS WR tSALW ADDRESS AD7-AD0 INT tDRDY Tristate RDY Table 48. Motorola Bus Read Timing Characteristics 2 Parameter Address setup time to address or data strobe Address hold time from address ...
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LXT386 — QUAD T1/E1/J1 Transceiver Figure 25. Non-Multiplexed Motorola Mode Read Timing A4-A0 ADDRESS tSAR AS (pulled High) tSRW R D7-D0 INT ACK 66 tHAR tSCS tVDS tPDS DATA OUT tDACKP tPACK tHRW tHCS tDZ tINT tDACK Datasheet ...
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Figure 26. Multiplexed Motorola Mode Read Timing AS tSRW R/W CS tASDS DS tSAR D7-D0 ADDRESS INT ACK Table 49. Motorola Mode Write Timing Characteristics 2 Parameter Address setup time to address strobe Address hold time to address strobe Valid ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 49. Motorola Mode Write Timing Characteristics (Continued) 2 Parameter Data strobe inactive to address strobe inactive delay Active data strobe to ACK output enable time DS asserted to ACK asserted delay 1. Typical figures ...
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Figure 28. Multiplexed Motorola Mode Write Timin AS tSRW R/W CS tASDS DS tSAS D7-D0 ADDRESS INT ACK Table 50. Serial I/O Timing Characteristics Parameter Rise/fall time any pin SDI to SCLK setup time SCLK to SDI hold time ...
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LXT386 — QUAD T1/E1/J1 Transceiver Figure 29. Serial Input Timing SCLK t DC LSB SDI Figure 30. Serial Output Timing CLKE = SCLK CS SDO CLKE = ...
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Table 52. G.703 2.048 Mbit/s Pulse Mask Specifications Parameter Test load impedance Nominal peak mark voltage Nominal peak space voltage Nominal pulse width Ratio of positive and negative pulse amplitudes at center of pulse Ratio of positive and negative pulse ...
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LXT386 — QUAD T1/E1/J1 Transceiver Figure 32. T1, T1.102 Mask Templates -0.80 -0.60 -0.40 72 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -0.20 0.00 0.20 0.40 -0.20 -0.40 -0.60 Tim e [UI] 0.60 0.80 1.00 1.20 Datasheet ...
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Figure 33. LXT386 Jitter Tolerance Performance 1000 UI 100 4.9 Hz AT&T 62411, Dec 1990 (T1 1 GR-499-CORE, Dec 1995 (T1 Datasheet ...
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LXT386 — QUAD T1/E1/J1 Transceiver Figure 34. Jitter Transfer Performance -10 dB -20 dB -30 dB -40 dB - 3Hz 0 40Hz =2.5 Hz ...
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Figure 35. Output Jitter for CTR12/13 applications 0.2 0.15 0.1 0. 100 Hz 6.1 Recommendations and Specifications AT&T Pub 62411 ANSI T1.102 - 199X Digital Hierarchy Electrical Interface ANSI T1.231 -1993 Digital Hierarchy Layer 1 ...
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LXT386 — QUAD T1/E1/J1 Transceiver 7.0 Mechanical Specifications Figure 36. 60 Plastic Ball Grid Array (PBGA) Package Dimensions 160 PBGA Package • Part Number LXT386BE • Extended Temperature Range (- 15.00 13.00 ±0.20 4.72 ±0.10 PIN ...
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... Figure 37. 100 Pin Low Quad Flat Packages (LQFP) Dimensions 100 Pin LQFP • Part Number LXT386LE • Extended Temperature Range (- 16.00 BSC 14.00 BSC 12.00 BSC 1.60 0.05 min max 1.40 ±0.05 0.15 max Datasheet QUAD T1/E1/J1 Transceiver — LXT386 ALL DIMENSIONS IN MILLIMETERS All dimensions and tolerances conform to ANSI Y14.5M-1982. ...
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