M38B79FFFP Renesas Electronics Corporation., M38B79FFFP Datasheet
M38B79FFFP
Related parts for M38B79FFFP
M38B79FFFP Summary of contents
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To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April ...
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MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES 38B7 http://www.infomicom.maec.co.jp/indexe.htm Before using this material, please visit the above website to confirm that this is the most current document available User’s Manual Rev. 1.3 Revision ...
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Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor prod- • ucts better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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REVISION HISTORY Rev. Date Page 1.0 07/07/00 1.1 03/10/00 74 100 1-2 Explanations of “DESCRIPTION” are partly eliminated. 1.2 11/01/01 Oscillation frequency value of “FEATURES” are partly revised. 1-2 Figure 3 is partly revised. 1-7 Figure 4 is partly revised. ...
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Preface This user’s manual describes Mitsubishi’s CMOS 8- bit microcomputers 38B7 Group. After reading this manual, the user should have a through knowledge of the functions and features of the 38B7 Group, and should be able to fully utilize the ...
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BEFORE USING THIS USER’S MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. Organization CHAPTER 1 HARDWARE This chapter describes features of the ...
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Table of contents CHAPTER 1 HARDWARE DESCRIPTION ................................................................................................................................ 1-2 FEATURES .................................................................................................................................... 1-2 APPLICATION ................................................................................................................................ 1-2 PIN CONFIGURATION .................................................................................................................. 1-3 FUNCTIONAL BLOCK .................................................................................................................. 1-4 PIN DESCRIPTION ........................................................................................................................ 1-5 PART NUMBERING ....................................................................................................................... 1-7 GROUP EXPANSION .................................................................................................................... 1-8 Memory Type ............................................................................................................................ 1-8 Memory ...
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Table of contents 2.3 Serial I/O ................................................................................................................................ 2-37 2.3.1 Memory map ................................................................................................................. 2-37 2.3.2 Relevant registers ........................................................................................................ 2-38 2.3.3 Serial I/O1 connection examples ............................................................................... 2-50 2.3.4 Serial I/O1’s modes ..................................................................................................... 2-52 2.3.5 Serial I/O1 application examples ............................................................................... 2-53 2.3.6 Serial ...
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Clock generating circuit ................................................................................................ 2-165 2.12.1 Relevant register ...................................................................................................... 2-165 2.12.2 Clock generating circuit application examples ..................................................... 2-166 2.13 Flash memory ................................................................................................................... 2-174 2.13.1 Overview .................................................................................................................... 2-174 2.13.2 Memory map ............................................................................................................. 2-174 2.13.3 Relevant registers .................................................................................................... 2-175 2.13.4 Parallel ...
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Table of contents 3.5 Control registers .................................................................................................................. 3-35 3.6 Package outline ................................................................................................................... 3-75 3.7 Machine instructions .......................................................................................................... 3-76 3.8 List of instruction code ..................................................................................................... 3-87 3.9 M35501FP .............................................................................................................................. 3-88 3.10 SFR memory map ............................................................................................................ 3-100 3.11 Pin configuration ............................................................................................................. 3-101 ...
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List of figures CHAPTER 1 HARDWARE Fig. 1 Pin configuration of M38B79MFH-XXXXFP .................................................................... 1-3 Fig. 2 Functional block diagram ................................................................................................... 1-4 Fig. 3 Part numbering .................................................................................................................... 1-7 Fig. 4 Memory expansion plan ..................................................................................................... 1-8 Fig. 5 740 Family CPU register ...
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List of figures Fig. 47 Structure of FLDC related registers (3) ...................................................................... 1-48 Fig. 48 Structure of FLDC related registers (4) ...................................................................... 1-49 Fig. 49 Segment/Digit setting example ..................................................................................... 1-50 Fig. 50 FLD automatic display RAM assignment .................................................................... 1-51 Fig. ...
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Fig. 96 Timings during erase verify........................................................................................... 1-92 Fig. 97 Timings at error checking .............................................................................................. 1-93 Fig. 98 Flash memory control register bit configuration ......................................................... 1-95 Fig. 99 Flash command register bit configuration ................................................................... 1-96 Fig. 100 CPU mode register bit ...
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List of figures Fig. 2.3.1 Memory map of registers relevant to Serial I/O .................................................... 2-37 Fig. 2.3.2 Structure of Serial I/O1 automatic transfer data pointer ...................................... 2-38 Fig. 2.3.3 Structure of Serial I/O1 control register 1 .............................................................. 2-39 Fig. 2.3.4 ...
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Fig. 2.3.53 Timing chart .............................................................................................................. 2-75 Fig. 2.3.54 Registers setting relevant to transmission side ................................................... 2-77 Fig. 2.3.55 Registers setting relevant to reception side......................................................... 2-78 Fig. 2.3.56 Control procedure of transmission side ................................................................ 2-79 Fig. 2.3.57 Control procedure of reception ...
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List of figures Fig. 2.4.39 Timing chart (at correct state) of 38B7 Group and M35501FP ...................... 2-127 Fig. 2.4.40 Timing chart (at incorrect state) of 38B7 Group and M35501FP ................... 2-127 Fig. 2.4.41 Setting of relevant registers ................................................................................. 2-128 Fig. ...
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Fig. 2.11.1 Example of power-on reset circuit ....................................................................... 2-163 Fig. 2.11.2 RAM backup system example .............................................................................. 2-163 Fig. 2.12.1 Structure of CPU mode register .......................................................................... 2-165 Fig. 2.12.2 Connection diagram ............................................................................................... 2-166 Fig. 2.12.3 Status transition diagram during power failure ...
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List of figures Fig. 3.4.1 Wiring for the RESET pin ......................................................................................... 3-28 Fig. 3.4.2 Wiring for clock I/O pins ........................................................................................... 3-29 Fig. 3.4.3 Wiring for CNVss pin ................................................................................................. 3-29 Fig. 3.4.4 Wiring for the V Fig. 3.4.5 Bypass capacitor across ...
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Fig. 3.5.43 Structure of Serial I/O3 register ............................................................................. 3-62 Fig. 3.5.44 Structure of Watchdog timer control register ....................................................... 3-63 Fig. 3.5.45 Structure of Pull-up control register 3................................................................... 3-63 Fig. 3.5.46 Structure of Pull-up control register 1................................................................... 3-64 Fig. 3.5.47 Structure ...
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List of tables CHAPTER 1 HARDWARE Table 1 Pin description (1) ........................................................................................................... 1-5 Table 2 Pin description (2) ........................................................................................................... 1-6 Table 3 List of supported products ............................................................................................. 1-8 Table 4 Push and pop instructions of accumulator or processor status register ...
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List of tables CHAPTER 3 APPENDIX Table 3.1.1 Absolute maximum ratings ....................................................................................... 3-2 Table 3.1.2 Recommended operating conditions (Vcc = 4 – unless otherwise noted) ........................................ 3-2 Table 3.1.3 Recommended operating conditions ...
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MEMORANDUM 38B7 Group User’s Manual List of tables iii ...
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HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING NOTES ON USAGE DATA REQUIRED FOR MASK ORDERS ...
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HARDWARE DESCRIPTION/FEATURES DESCRIPTION The 38B7 group is the 8-bit microcomputer based on the 740 family core technology. The 38B7 group has six 8-bit timers, one 16-bit timer, a fluorescent display automatic display circuit, 16-channel 10-bit A-D converter, a serial I/O ...
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PIN CONFIGURATION (TOP VIEW) *P2 /FLD ...
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HARDWARE FUNCTIONAL BLOCK Fig. 2 Functional block diagram 1-4 38B7 Group User’s Manual ...
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Table 1 Pin description (1) Pin Name Power source • Apply voltage of 4.0–5 CNV CNV • Connect • VPP power input pin in flash memory mode. V ...
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HARDWARE PIN DESCRIPTION Table 2 Pin description (2) Pin Name P6 /R D/FLD , I/O port P6 • 4-bit I/O port . D/FLD , • Low-voltage input level for input ports ...
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Fig. 3 Part numbering ...
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... Fig. 4 Memory expansion plan Currently supported products are listed below. Table 3 List of supported products ROM size (bytes) Product ROM size for User ( ) M38B79MFH-XXXXFP 61440 (61310) M38B79FFFP 1 1,024 RAM size (bytes) RAM size (bytes) 2048 38B7 Group User’s Manual ...
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FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 38B7 group uses the standard 740 Family instruction set. Re- fer to the table of 740 Series addressing modes and machine instructions or the 740 Series Software Manual for details on the instruction ...
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HARDWARE FUNCTIONAL DESCRIPTION ...
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The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions can be performed ...
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HARDWARE FUNCTIONAL DESCRIPTION [CPU Mode Register (CPUM)] 003B The CPU mode register contains the stack page selection bit and the internal system clock selection bit etc. The CPU mode register is allocated at address 003B b 7 Fig. 7 Structure ...
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MEMORY Special Function Register (SFR) Area The special function register (SFR) area contains control registers for I/O ports, timers and other functions. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The ...
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HARDWARE FUNCTIONAL DESCRIPTION 0000 Port P0 (P0) 16 0001 16 Port P1 (P1) 0002 16 0003 Port P1 direction register (P1D) 16 Port P2 (P2) 0004 16 0005 16 Port P3 (P3) 0006 16 0007 Port P3 direction register (P3D) ...
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I/O PORTS [Direction Registers] PiD The 38B7 group has 75 programmable I/O pins arranged in ten in- dividual I/O ports (P1, P3, P4, P5, P6, P7, P8, P9, PA and PB). The I/O ports have direction registers which determine the ...
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HARDWARE FUNCTIONAL DESCRIPTION Table 6 List of I/O port functions (1) Pin Nama Input/Output P0 /FLD – Port P0 Output /FLD FLD – Port P1 Input/output /FLD individual 7 23 bits ...
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Table 7 List of I/O port functions (2) Pin Nama Input/Output Port P9 Input/output, 0 IN3 AN individual 8 bits OUT3 CLK3 ...
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HARDWARE FUNCTIONAL DESCRIPTION ( ...
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HARDWARE FUNCTIONAL DESCRIPTION ( ...
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INTERRUPTS Interrupts occur by twenty two sources: five external, sixteen inter- nal, and one software. Interrupt Control Each interrupt except the BRK instruction interrupt has both an inter- rupt request bit and an interrupt enable bit, and is controlled by ...
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HARDWARE FUNCTIONAL DESCRIPTION Table 8 Interrupt vector addresses and priority Vector Addresses (Note 1) Interrupt Source Priority High Reset (Note 2) 1 FFFD 16 INT 2 FFFB 0 16 INT 3 FFF9 1 16 Serial I/O3 INT 4 FFF7 2 ...
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Interrupt request bit Interrupt enable bit Interrupt disable flag I Fig. 14 Interrupt control ...
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HARDWARE FUNCTIONAL DESCRIPTION TIMERS 8-Bit Timer The 38B7 group has six built-in 8-bit timers : Timer 1, Timer 2, Timer 3, Timer 4, Timer 5, and Timer 6. Each timer has the 8-bit timer latch. All timers are down-counters. When ...
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1 “ 1 ” ...
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HARDWARE FUNCTIONAL DESCRIPTION ...
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Timer Timer 16-bit timer that can be selected in one of four modes by the Timer X mode registers 1, 2 and can be controlled for the timer X write and the real time port by ...
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HARDWARE FUNCTIONAL DESCRIPTION “ 1 ” “ 0 ” ...
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SERIAL I/O Serial I/O1 Serial I/O1 is used as the clock synchronous serial I/O and has an ordinary mode and an automatic transfer mode. In the automatic transfer mode, serial transfer is performed through the serial I/O automatic transfer RAM ...
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HARDWARE FUNCTIONAL DESCRIPTION Fig. 22 Structure of serial I/O1 control registers ...
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Serial I/O1 operation Either the internal synchronous clock or external synchronous clock can be selected by the serial I/O1 synchronous clock selec- tion bits (b2 and b3 of address 0019 register 1 as synchronous clock for serial transfer. The ...
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HARDWARE FUNCTIONAL DESCRIPTION (2) 8-bit serial I/O mode Address 001B is assigned to the serial I/O1 register. 16 When the internal synchronous clock is selected, a serial transfer of the 8-bit serial I/O is started by a write signal to ...
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Fig. 25 Automatic transfer serial I/O operation A ...
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HARDWARE FUNCTIONAL DESCRIPTION (4) Handshake signal 1. S output signal STB1 The S output is a signal to inform an end of transmission/re- STB1 ception to the serial transfer destination . The S can be used only when the internal ...
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When the internal synchronous clock is selected, in the 8-bit serial I/O mode and the automatic transfer serial I/O mode (S put function outputs in 1-byte units), the S and the S output goes to “H” before 0.5 cycle (transfer ...
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HARDWARE FUNCTIONAL DESCRIPTION 4. S output signal RDY1 The S output is a transmit/receive enable signal which in- RDY1 forms the serial transfer destination that transmit/receive is ready. In the initial status, when the serial I/O initialization bit (b4) is ...
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S CLK1 S RDY1 S BUSY1 A: Internal synchronous External synchronous clock selection clock selection Fig. 34 Handshake operation at serial I/O1 mutual connecting (1) S CLK1 S RDY1 S BUSY1 A: Internal synchronous External synchronous clock selection clock selection ...
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HARDWARE FUNCTIONAL DESCRIPTION Serial I/O2 Serial I/O2 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation during serial I/O2 opera- tion. (1) Clock ...
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Asynchronous serial I/O (UART) mode The asynchronous serial I/O (UART) mode can be selected by clearing the serial I/O2 mode selection bit (b6) of the serial I/O2 control register (address 001D ) to “0”. Eight serial data transfer 16 ...
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HARDWARE FUNCTIONAL DESCRIPTION [Serial I/O2 Control Register] SIO2CON (001D The serial I/O2 control register contains eight control bits for serial I/O2 functions. [UART Control Register] UARTCON (0038 This bit register containing four control bits, of which four ...
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...
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HARDWARE FUNCTIONAL DESCRIPTION Serial I/O3 The serial I/O3 function can be used only for 8-bit clock synchro- nous serial I/O. All serial I/O pins are shared with port P9, which can be set with the serial I/O3 control register (address ...
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Transfer clock ...
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HARDWARE FUNCTIONAL DESCRIPTION FLD CONTROLLER The M38B7 group has fluorescent display (FLD) drive and control circuits. Table 9 shows the FLD controller specifications. Table 9 FLD controller specifications Item High-breakdown- FLD voltage output port controller CMOS port port Display pixel ...
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0EDF 16 Address decoder T ...
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HARDWARE FUNCTIONAL DESCRIPTION Note: When the gradation display mode is selected, the max. number of timing is 16 timing. (Be sure to set the timing number ...
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Fig. 46 Structure of FLDC related registers (2) FUNCTIONAL DESCRIPTION ...
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HARDWARE FUNCTIONAL DESCRIPTION Fig. 47 Structure of FLDC related registers (3) 1- ...
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Fig. 48 Structure of FLDC related registers (4) FUNCTIONAL DESCRIPTION Port P0 ...
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HARDWARE FUNCTIONAL DESCRIPTION FLD Automatic Display Pins are the pins capable of automatic display output for the FLD. The FLD star ts operating by setting the automatic display control bit (bit 0 at address 0EF4 ) to ...
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FLD Automatic Display RAM The FLD automatic display RAM uses the 224 bytes of addresses 0E00 to 0EDF . For FLD, the 3 modes of 16-timing•ordinary 16 16 mode, 16-timing•gradation display mode and 32-timing mode are available depending on the ...
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HARDWARE FUNCTIONAL DESCRIPTION Data Setup (1) 16-timing•ordinary mode The area of addresses 0E70 to 0EDF 16 tomatic display RAM. When data is stored in the FLD automatic display RAM, the last data of FLD port P6 is stored at address ...
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HARDWARE FUNCTIONAL DESCRIPTION ...
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Timing Setting Each timing is set by the FLDC mode register, Tdisp time set reg- ister, Toff1 time set register, and Toff2 time set register. (1) Tdisp time setting The Tdisp time means the length of display timing. In non-grada- ...
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HARDWARE FUNCTIONAL DESCRIPTION FLD Automatic Display Start Automatic display starts by setting both the automatic display con- trol bit (bit 0 of address 0EF4 ) and the display start bit (bit address 0EF4 ) to “1”. The ...
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The FLD blanking interrupt is generated when the FLD data pointer (address 0EF8 ) reaches “ play output is turned off for a duration Tdisp depending on post-interrupt settings. During this time, key scanning that ...
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HARDWARE FUNCTIONAL DESCRIPTION Expansion Function 4 7 Ports are CMOS output structure. FLD digit outputs 4 7 can be increased as many as 16 lines by connecting a decoder converting 4-bit to 16-bit data ...
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Toff Section Generate/Nothing Function The function is for reduction of useless noises which generated as every switching of ports, because of the combined capacity of among FLD ports. When the continuous data is output to each FLD port, the Toff1 ...
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HARDWARE FUNCTIONAL DESCRIPTION Digit Pulses Output Function and can output digit pulses by using the digit output set switch registers. Set the digit output set switch reg- isters by setting ...
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A-D CONVERTER The 38B7 group has a 10-bit A-D converter. The A-D converter performs successive approximation conversion. [A-D Conversion Register] ADH, ADL One of these registers is a high-order register, and the other is a low-order register. The high-order 8 ...
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HARDWARE FUNCTIONAL DESCRIPTION D-A CONVERTER The 38B7 group has one internal D-A converter with 8-bit resolu- tion. The D-A conversion is performed by setting the value in the D-A conversion register. The result of D-A conversion is output from the ...
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PWM (Pulse Width Modulation) The 38B7 group has a PWM function with a 14-bit resolution. When the oscillation frequency MHz, the minimum resolution bit IN width is 250 ns and the cycle period is 4096 s. The ...
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HARDWARE FUNCTIONAL DESCRIPTION Data Setup The PWM output pin also function as port P9 the PWM output pin by setting bit 0 of the PWM control register (address 0026 ) to “1”. The high-order 8 bits of output data are ...
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Fig. 66 Structure of PWM control register Data 6A stored at address 0035 ...
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HARDWARE FUNCTIONAL DESCRIPTION INTERRUPT INTERVAL DETERMINATION FUNCTION The 38B7 group has an interrupt interval determination circuit. This interrupt interval determination circuit has an 8-bit binary up counter. Using this counter, it determines a duration of time from the rising edge ...
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Fig. 69 Structure of interrupt interval determination control register ( “ 0 ” ...
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HARDWARE FUNCTIONAL DESCRIPTION WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software runaway). The watchdog timer consists of an ...
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BUZZER OUTPUT CIRCUIT The 38B7 group has a buzzer output circuit. One of 1 kHz, 2 kHz and 4 kHz ( 4.19 MHz) frequencies can be selected by the IN buzzer output control register (address 0EFD or P9 ...
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HARDWARE FUNCTIONAL DESCRIPTION RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for more. Then the RESET pin is returned to an “H” level (the power source voltage should be between ...
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...
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HARDWARE FUNCTIONAL DESCRIPTION CLOCK GENERATING CIRCUIT The 38B7 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between and X . Use the circuit constants in accordance OUT CIN ...
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“ 0 ” “ 1 ” ...
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HARDWARE FUNCTIONAL DESCRIPTION “1” ...
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Power Dissipation Calculating Method (Fixed number depending on microcomputer’s standard) • V output fall voltage of high-breakdown port (max.); | Current value | = • Resistor value = 48 k (min.) • Power dissipation ...
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HARDWARE FUNCTIONAL DESCRIPTION Power Dissipation Calculating Example 1 (Fixed number depending on microcomputer’s standard) • V output fall voltage of high-breakdown port (max.); | Current value | = • Resistor value ...
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Power Dissipation Calculating Example more digits turned ON at the same time) (Fixed number depending on microcomputer’s standard) • V output fall voltage of high-breakdown port (max.); | Current value | = at 18 ...
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HARDWARE FUNCTIONAL DESCRIPTION FLASH MEMORY MODE The M38B79FF has the flash memory mode in addition to the nor- mal operation mode (microcomputer mode). The user can use this mode to perform read, program, and erase operations for the in- ternal ...
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Table 14 Pin description (flash memory parallel I/O mode) Pin Name Power supply CC SS CNV V input SS PP _____ RESET Reset input X Clock input IN X Clock output OUT AV Analog supply input SS ...
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... REF 100 6 6 Fig. 85 Pin connection of M38B79FF when operating in parallel input/output mode 1-80 M38B79FFFP Package type: 100P6S-A 38B7 Group User’s Manual * ...
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Read-only Mode The microcomputer enters the read-only mode by applying V to the V pin. In this mode, the user can input the address memory location to be read and the control signals at the timing Address ...
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HARDWARE FUNCTIONAL DESCRIPTION Read command The microcomputer enters the read mode by inputting command code “00 ” in the first cycle. The command code is latched into 16 the internal command latch at the rising edge of the WE input. ...
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Program command The microcomputer enters the program mode by inputting com- mand code “40 ” in the first cycle. The command code is latched 16 into the internal command latch at the rising edge of the WE input. When the ...
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HARDWARE FUNCTIONAL DESCRIPTION Erase command The erase command is executed by inputting command code 20 in the first cycle and command code 20 cycle. The command code is latched into the internal command ___ latch at the rising edges of ...
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Reset command The reset command provides a means of stopping execution of the erase or program command safely. If the user inputs command code FF in the second cycle after inputting the erase or program 16 command in the first ...
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HARDWARE FUNCTIONAL DESCRIPTION Program START ADRS = first location WRITE PROGRAM COMMAND WRITE PROGRAM DATA DURATION = WRITE PROGRAM-VERIFY COMMAND DURATION = ...
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Table 16 DC ELECTRICAL CHARACTERISTICS (T Symbol Parameter I SB1 V supply current (at standby SB2 I V supply current (at read) CC1 supply current (at program) CC2 supply current (at erase) ...
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... Serial input/output is accomplished synchronously with the clock, beginning from the LSB (LSB first). M38B79FFFP 38B7 Group User’s Manual H to the V pin ...
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Table 19 Pin description (flash memory serial I/O mode) Pin Name Power supply CC SS CNV V input SS PP _____ RESET Reset input X Clock input IN X Clock output OUT AV Analog supply input SS ...
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HARDWARE FUNCTIONAL DESCRIPTION Functional Outline (serial I/O mode) In the serial I/O mode, data is transferred synchronously with the clock using serial input/output. The input data is read from the SDA pin into the internal circuit synchronously with the rising ...
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Program command Input command code 40 in the first transfer. Proceed and input 16 the low-order 8 bits and the high-order 8 bits of the address and then program data. Programming is initiated at the last rising edge of the ...
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HARDWARE FUNCTIONAL DESCRIPTION Erase command Input command code 20 in the first transfer and command code 16 20 again in the second transfer. When this is done, the 16 M38B79FF executes an erase command. Erase is initiated at the last ...
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Error check command Input command code 80 in the first transfer, and the M38B79FF 16 outputs error information from the SDA pin, beginning at the next falling edge of the serial clock. If the LSB bit of the 8-bit error ...
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HARDWARE FUNCTIONAL DESCRIPTION DC ELECTRICAL CHARACTERISTICS -relevant standards during read, program, and erase are the same as in the parallel input/output mode for the SCLK, SDA, BUSY, OE pins conform to the ...
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Flash memory mode 3 (CPU reprogramming mode) The M38B79FF has the CPU reprogramming mode where a built- in flash memory is handled by the central processing unit (CPU). In CPU reprogramming mode, the flash memory is handled by writing ...
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HARDWARE FUNCTIONAL DESCRIPTION CPU reprogramming mode operation procedure The operation procedure in CPU reprogramming mode is de- scribed below. < Beginning procedure > Apply the CNVss/V pin for reset release. PP Set the CPU mode register. (see ...
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Program command When “40 ” is written to the flash command register, the 16 M38B79FF enters the program mode. Subsequently to this, if the instruction (for instance, STA instruction) for writing byte data in the address to be programmed is ...
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HARDWARE FUNCTIONAL DESCRIPTION Program START ADRS = first location WRITE PROGRAM COMMAND WRITE PROGRAM DATA WAIT ERASE PROGRAM BUSY FLAG = WRITE PROGRAM-VERIFY COMMAND DURATION = ...
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NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1.” Af- ter a reset, initialize flags which affect program execution. In ...
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HARDWARE NOTES ON USAGE/ DATA REQUIRED FOR MASK ORDERS NOTES ON USAGE Handling of Power Source Pins In order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (V ...
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APPLICATION 2.1 I/O port 2.2 Timer 2.3 Serial I/O 2.4 FLD controller 2.5 A-D converter 2.6 D-A converter 2.7 PWM 2.8 Interrupt interval determination function 2.9 Watchdog timer 2.10 Buzzer output circuit ...
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APPLICATION 2.1 I/O port 2.1 I/O port This paragraph describes the setting method of I/O port relevant registers, notes etc. 2.1.1 Memory assignment Address 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F ...
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Relevant registers Port Fig. 2.1.2 Structure of port Port Fig. 2.1.3 Structure of ...
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APPLICATION 2.1 I/O port Port Fig. 2.1.4 Structure of port PB Port Pi direction register Fig. 2.1.5 Structure of port ...
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Port P8 direction register Fig. 2.1.6 Structure of port P8 direction register Port PB direction register Fig. 2.1.7 Structure of port PB direction register ...
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APPLICATION 2.1 I/O port Pull-up control register Fig. 2.1.8 Structure of pull-up control register 1 Pull-up control register Fig. 2.1.9 Structure of ...
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Pull-up control register Fig. 2.1.10 Structure of pull-up control register 3 Pull-up control register 3 (PULL3: address 0EEF ) 16 b Name Functions 0: No pull-up Ports ...
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APPLICATION 2.1 I/O port 2.1.3 Terminate unused pins Table 2.1.1 Termination of unused pins Pins P0, P2 Open at “H” output state. P1, P3–P5, P6 – • Set to the input mode and connect each ...
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Notes on I/O port (1) Notes in standby state 1 In standby state for low-power dissipation, do not make input levels of an input port and an I/O port “undefined”. Pull-up (connect the port to V resistor. When determining ...
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APPLICATION 2.1 I/O port 2.1.5 Termination of unused pins (1) Terminate unused pins Output ports : Open Input ports : Connect each pin for pins whose potential affects to operation modes such as pin INT or others, ...
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Timer This paragraph explains the registers setting method and the notes relevant to the timers. 2.2.1 Memory map 0020 ...
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APPLICATION 2.2 Timer 2.2.2 Relevant registers (1) 8-bit timer Timer Fig. 2.2.2 Structure of Timer i (i= Timer Fig. ...
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Timer 12 mode register Fig. 2.2.5 Structure of Timer 12 mode register Timer 34 mode register Fig. 2.2.6 Structure of Timer 34 mode register ...
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APPLICATION 2.2 Timer Timer 56 mode register Fig. 2.2.7 Structure of Timer 56 mode register 2-14 Timer 56 mode register (T56M: address Name Functions Timer 5 count stop ...
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Timer X (low-order, high-order Fig. 2.2.8 Structure of Timer X (low-order, high-order) Timer X (low-order, high-order) (TXL, TXH: addresses Functions • Set ...
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APPLICATION 2.2 Timer Timer X mode register Fig. 2.2.9 Structure of Timer X mode register 1 2-16 Timer X mode register 1 (TXM1: address Name Functions Timer ...
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Timer X mode register Fig. 2.2.10 Structure of Timer X mode register 2 Timer X mode register 2 (TXM2: address Name Functions 0 Real time port control ...
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APPLICATION 2.2 Timer (3) 8-bit timer, 16-bit timer Interrupt request register Fig. 2.2.11 Structure of Interrupt request register 1 2-18 Interrupt request register 1 (IREQ1 : address ...
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Interrupt request register Fig. 2.2.12 Structure of Interrupt request register 2 Interrupt request register 2 (IREQ2 : address Name Functions Timer 4 interrupt ...
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APPLICATION 2.2 Timer Interrupt control register Fig. 2.2.13 Structure of Interrupt control register 1 Interrupt control register Fig. 2.2.14 Structure of ...
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Timer application examples (1) Basic functions and uses [Function 1] Control of event interval (Timer 1 to Timer 6, Timer X: timer mode) When a certain time, by setting a count value to each timer, has passed, the timer ...
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APPLICATION 2.2 Timer (2) Timer application example 1: Clock function (measurement Outline: The input clock is divided by the timer so that the clock can count intervals. Specifications: •The clock f(X •The timer ...
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...
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APPLICATION 2.2 Timer SEI T12M ( T34M ( ...
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Timer application example 2: Piezoelectric buzzer output Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer output. Specifications: •The rectangular waveform, dividing the clock f(X 2 kHz (2048 Hz), is output from the ...
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APPLICATION 2.2 Timer ...
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Timer application example 3: Frequency measurement Outline: The following two values are compared to judge whether the frequency is within a valid range. •A value by counting pulses input to P8 •A reference value Specifications: •The pulse is input ...
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APPLICATION 2.2 Timer T12M ...
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(address (address ...
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APPLICATION 2.2 Timer (5) Timer application example 4: Measurement of FG pulse width for motor Outline: The timer X counts the “H” level width of the pulses input to the P8 underflow is detected by the timer X interrupt and ...
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P8D T i ...
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APPLICATION 2.2 Timer RESET Initialization ...
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CLT (Note 2) CLD (Note ...
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APPLICATION 2.2 Timer (6) Timer application example 5: Control of stepping motor Outline: The rotating of stepping motor is controlled by using real time output ports. Specifications: •The motor is controlled by using 2 real time output ports. •The count ...
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APPLICATION 2.2 Timer ...
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Serial I/O This paragraph explains the registers setting method and the notes relevant to the serial I/O. 2.3.1 Memory map ...
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APPLICATION 2.3 Serial I/O 2.3.2 Relevant registers (1) Serial I/O1 Serial I/O1 automatic transfer data pointer Fig. 2.3.2 Structure of Serial I/O1 automatic transfer data pointer 2-38 Serial I/O1 automatic transfer data ...
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Serial I/O1 control register Fig. 2.3.3 Structure of Serial I/O1 control register 1 Serial I/O1 control register 1 (SIO1CON1•SC11: address Name Functions 0 b1b0 Serial transfer 0 ...
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APPLICATION 2.3 Serial I/O Serial I/O1 control register Fig. 2.3.4 Structure of Serial I/O1 control register 2 2-40 Serial I/O1 control register 2 (SIO1CON2 • SC12: address ...
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Serial I/O1 register/Transfer counter Fig. 2.3.5 Structure of Serial I/O1 register/Transfer counter Serial I/O1 register/Transfer counter (SIO1: address Name Functions •At function as serial I/O1 •In 8-bit serial ...
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APPLICATION 2.3 Serial I/O Serial I/O1 control register Fig. 2.3.6 Structure of Serial I/O1 control register 3 2-42 Serial I/O1 control register 3 (SIO1CON3 • SC13: address ...
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Serial I/O2 Baud rate generator Fig. 2.3.7 Structure of Baud rate generator UART control register Fig. 2.3.8 Structure of UART control register Baud ...
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APPLICATION 2.3 Serial I/O Serial I/O2 control register Fig. 2.3.9 Structure of Serial I/O2 control register 2-44 Serial I/O2 control register (SIO2CON: address Name Functions 0 0: f(X ...
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Serial I/O2 status register Fig. 2.3.10 Structure of Serial I/O2 status register Serial I/O2 transmit/receive buffer register Fig. 2.3.11 Structure of Serial I/O2 transmit/receive ...
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APPLICATION 2.3 Serial I/O (3) Serial I/O3 Serial I/O3 control register Fig. 2.3.12 Structure of Serial I/O3 control register Serial I/O3 register Fig. 2.3.13 ...
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Serial I/O1 and Serial I/O2 Interrupt source switch register Fig. 2.3.14 Structure of Interrupt source switch register Interrupt request register Fig. 2.3.15 ...
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APPLICATION 2.3 Serial I/O Interrupt request register Fig. 2.3.16 Structure of Interrupt request register 2 2-48 Interrupt request register 2 (IREQ2 : address Name Functions Timer 4 ...
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Interrupt control register Fig. 2.3.17 Structure of Interrupt control register 1 Interrupt control register Fig. 2.3.18 Structure of Interrupt control register ...
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APPLICATION 2.3 Serial I/O 2.3.3 Serial I/O1 connection examples (1) Control of peripheral IC equipped with CS pin Figure 2.3.19 shows connection examples with peripheral ICs equipped with the CS pin. All examples can use the automatic transfer function. ( ...
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Connection with microcomputer Figure 2.3.20 shows connection examples with another microcomputer CLK S CLK11 ...
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APPLICATION 2.3 Serial I/O 2.3.4 Serial I/O1’s modes Figure 2.3.21 shows the serial I/O1’s modes ...
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Serial I/O1 application examples (1) Output of serial data (control of peripheral IC) Outline : Serial communication is performed, connecting ports with the CS pin of a peripheral IC. Figure 2.3.22 shows a connection diagram, and Figure 2.3.23 shows ...
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APPLICATION 2.3 Serial I/O Figure 2.3.24 shows the registers setting relevant to the transmission side, and Figure 2.3.25 shows the setting of transmission data ...
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Control procedure: When the registers are set as shown in Figure 2.3.24, the serial I/O1 can transmit 1-byte data by writing data to the serial I/O1 register. Thus, after setting the CS signal to “L”, write the transmission data to ...
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APPLICATION 2.3 Serial I/O (2) Transmission/Reception using automatic transfer Outline: Serial transmission/reception control is performed, using the serial automatic transfer function. Figure 2.3.27 shows a connection diagram, and Figure 2.3.28 shows a timing chart of serial data transmission/reception ...
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APPLICATION 2.3 Serial I ...
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Serial I/O2 connection examples (1) Control of peripheral IC equipped with CS pin Figure 2.3.31 shows connection examples with peripheral ICs equipped with the CS pin ...
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APPLICATION 2.3 Serial I/O (2) Connection with microcomputer Figure 2.3.32 shows connection examples with another microcomputer ...
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Serial I/O2’s modes A clock synchronous or clock asynchronous (UART) can be selected for the serial I/O2. Figure 2.3.33 shows the serial I/O2’s modes, and Figure 2.3.34 shows the serial I/O2 transfer data format ...
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APPLICATION 2.3 Serial I/O 2.3.8 Serial I/O2 application examples (1) Communication (transmission/reception) using clock synchronous serial I/O Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O. The S signal is used for communication control. RDY2 ...
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Figure 2.3.37 shows the registers setting relevant to the transmission side, and Figure 2.3.38 shows the registers setting relevant to the reception side ...
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APPLICATION 2.3 Serial I Serial I/O2 status register (address 001E ...
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Figure 2.3.39 shows a control procedure of the transmission side, and Figure 2.3.40 shows a control procedure of the reception side ...
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APPLICATION 2.3 Serial I ...
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Output of serial data (control of peripheral IC) Outline : Serial communication is performed, connecting port P7 Figure 2.3.41 shows a connection diagram, and Figure 2.3.42 shows a timing chart. 38B7 group Fig. 2.3.41 Connection diagram Specifications : • ...
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APPLICATION 2.3 Serial I/O Figure 2.3.43 shows the relevant registers setting and Figure 2.3.44 shows the setting of transmission data ...
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Figure 2.3.45 shows a control procedure ...
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APPLICATION 2.3 Serial I/O (3) Cyclic transmission or reception of block data (data of specified number of bytes) between two microcomputers Outline : When the clock synchronous serial I/O is used for communication, synchronization of the clock and the data ...
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The communication is performed according to the timing shown in Figure 2.3.47. In the slave unit, when a synchronous clock is not input within a certain time (heading adjusment time), the next clock input is processed as the beginning (heading) ...
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APPLICATION 2.3 Serial I/O Slave unit Fig. 2.3.49 Relevant registers setting in slave unit 2- ...
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Control procedure by software: Control in the master unit After setting the relevant registers shown in Figure 2.3.48, the master unit starts transmission or reception of 1-byte data by writing transmission data to the serial I/O2 transmit buffer register. To ...
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APPLICATION 2.3 Serial I/O Control in the slave unit After setting the relevant registers as shown in Figure 2.3.49, the slave unit becomes the state where a synchronous clock can be received at any time, and the serial I/O2 receive ...
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Communication (transmission/reception) using asynchronous serial I/O (UART) Outline : 2-byte data is transmitted and received, using the asynchronous serial I/O. Port P7 is used for communication control. 6 Figure 2.3.52 shows a connection diagram, and Figure 2.3.53 shows a ...
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APPLICATION 2.3 Serial I/O Table 2.3.1 shows setting examples of the baud rate generator (BRG) values and transfer bit rate values. Table 2.3.1 Setting examples of baud rate generator values and transfer bit rate values f(X Transfer bit rate BRG ...
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Figure 2.3.54 shows the registers setting relevant to the transmission side; Figure 2.3.55 shows the registers setting relevant to the reception side ...