MT90503AG Zarlink Semiconductor, MT90503AG Datasheet

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... Clock Recovery Submodule Clock Signals Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. MT90503AG For temperature range, see page 207. • TDM to ATM transmission latency less than 250 s • Support for clock recovery - Adaptive Clock ...

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... ZARLINK ASSUMES NO RESPONSIBILITY OR LIABILITY THAT MAY RESULT FROM ITS CUSTOMERS' USE OF ZARLINK PRODUCTS WITH RESPECT TO THIS PATENT. INDEMNITY IN ITS TERMS AND CONDITIONS OF SALES WHICH ARE SET OUT IN ITS SALES ACKNOWLEDGEMENTS AND INVOICES DOES NOT APPLY TO THIS PATENT. MT90503 IN PARTICULAR, ZARLINK'S PATENT 2 Zarlink Semiconductor Inc. Data Sheet ...

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... MT90503 Digital PLL MT9045 28 port AAL1 SAR T1/E1 MT90528 LIU Digital PLL MT9045 Octal/IMA T1/E1 Framers MT90220 MT9076 Figure 2 - ATM Switch Application 3 Zarlink Semiconductor Inc. Data Sheet ATM Network Uplink OC-12 Framers Optical & ATM Interface & Drivers Cell Access Traffic Management & Switching ...

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... Transmit Event Scheduler Fields Description 4.3.2.4 Scheduler Events Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3.2.5 Bandwidth Limitations for Transmit Scheduler Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3.3 Out of Bandwidth Error 4.3.3.1 Percent of Bandwidth Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.3.2 Distribution of Events by Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.4 Mapping of the Transmit Event Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.5 TX_SAR Control Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.3.5.1 TX_SAR Control Structure Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 MT90503 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...

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... Control Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3.3 Data Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3.4 Control Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.4 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.5 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.5.1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.5.2 Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.5.3 UTOPIA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.5.4 TDM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 5.5.5 TX_SAR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 MT90503 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...

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... H.110 Diode Clamp Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.3 AC Characteristics 210 9.0 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 9.1 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 9.2 UTOPIA Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 9.3 External Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 9.4 H.100/H.110 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 9.5 H.100/H.110 Clocking Signals 227 10.0 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 MT90503 Table of Contents 6 Zarlink Semiconductor Inc. Data Sheet ...

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... Figure 41 - UTOPIA Clock Generation Figure 42 - External UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 43 - Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 44 - Integer Clock Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 45 - Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 46 - Adaptive Cell Reception Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure SRTS Clock Recovery Module Figure SRTS Clock Recovery Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 MT90503 List of Figures 7 Zarlink Semiconductor Inc. Data Sheet ...

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... Figure 72 - H.100 Message Channel Clock, Transmission Delay, and Reception Delay 226 Figure 73 - H.100 Clock Skew (when chip is Master 226 Figure 74 - H.100/H.110 Clocking Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Figure 75 - TDM Bus Timing - Compatibility Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Figure 76 - TDM Data Bus Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 MT90503 List of Figures 8 Zarlink Semiconductor Inc. Data Sheet ...

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... Table 43 - PLL Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 44 - Intel/Motorola Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 45 - Intel/Motorola Address Rise Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 46 - Intel/Motorla Address Fall Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 47 - Intel/Motorola Data Out Register 108 Table 48 - Intel/Motorola Data In Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 MT90503 List of Tables 9 Zarlink Semiconductor Inc. Data Sheet ...

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... Table 91 - Port B VPI/VCI Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 92 - Port B Concatenation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 93 - Port B VPI Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 94 - Port B VPI Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 95 - Port B VCI Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 97 - Port B Cell Arrival Counter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 MT90503 List of Tables 10 Zarlink Semiconductor Inc. Data Sheet ...

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... Table 140 - GPIO Output2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Table 141 - GPIO Output Enable0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 142 - GPIO Output Enable1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 143 - GPIO Output Enable2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 144 - TDM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 MT90503 List of Tables 11 Zarlink Semiconductor Inc. Data Sheet ...

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... Table 187 - Error Timeout Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 188 - Treated Pulses Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Table 189 - Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Table 190 - Clock Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Table 191 - Status Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 192 - MCLK Alarm 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 MT90503 List of Tables 12 Zarlink Semiconductor Inc. Data Sheet ...

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... Table 236 - Integer Clock Divisor0 10 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table 237 - Integer Clock Divisor1 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table 238 - Integer Clock Divisor1 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table 239 - Integer Clock Divisor1 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Table 240 - Integer Clock Divisor1 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 MT90503 List of Tables 13 Zarlink Semiconductor Inc. Data Sheet ...

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... Table 283 - CAS Timeout High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Table 284 - CAS Timeout Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Table 285 - Treated Pulses Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Table 286 - H.100 Control 0 Register 200 Table 287 - H.100 Control 1 Register 201 Table 288 - H.100 Control 2 Register 201 MT90503 List of Tables 14 Zarlink Semiconductor Inc. Data Sheet ...

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... Table 299 - Multiplexed CPU Interface Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Table 300 - t5 Read Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Table 301 - UTOPIA Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Table 302 - Memory Interface Timing 225 Table 303 - H.100/H.110 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Table 304 - H.100/H.110 Clocking Signals 229 MT90503 List of Tables 15 Zarlink Semiconductor Inc. Data Sheet ...

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... TDM Bus TX UTOPIA Interface Figure 3 - Transmit Data Flow - TDM to UTOPIA MT90503 Path Controlled by TX SAR Module TX SAR Internal Memory UTOPIA Cell UTOPIA Output Router Path Controlled by UTOPIA Module 16 Zarlink Semiconductor Inc. Data Sheet Circular Buffers[15:8] (External Data Memory) UTOPIA Input FIFO ...

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... Per-UTOPIA-port User cell and OAM cell destination control (for VCs that do not have a LUT entry) MT90503 Path Controlled by UTOPIA Module UTOPIA Cell Router External Control CPU Module Memory Circular Buffers[7:0] (External Data Memory) Path Controlled by RX SAR Module 17 Zarlink Semiconductor Inc. Data Sheet UTOPIA Output FIFO RX SAR non-CBR Portion RX SAR CBR Portion ...

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... ATM to TDM Reception latency less than CDV + 250 s (when minimum voice latency desired, and strict multiframe alignment of voice with CAS not required) • ATM to TDM Reception latency less than CDV + 6.250 ms (when strict multiframe alignment of voice with CAS required) • Per VCC monitoring (Receive/Reassembly direction): MT90503 18 Zarlink Semiconductor Inc. Data Sheet ...

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... Parity bits on memory and UTOPIA interfaces to ensure clocking and memory access integrity • CPU-based OAM cell treatment • JTAG (IEEE 1149) Test Access Port • MCLK speed of 80 MHz • Global reset pin with I/O tri-state MT90503  with strict multiframing, 19 Zarlink Semiconductor Inc. Data Sheet  ...

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... Pins not connected: A13, B3, B4, B7, B8, B9, B12, B13, B14, B15, B16, C3, C4, C7, C8, C9, C12, C13, C14, C15, D6, D7, D8, D9, D12, D13, D14, D15, D24, E5, E8, E9, E12, E13, E14, E15, E25, M5, M28, T25, W25, AB25, AE4, AE5, AE22, AE23, AE25, AF2, AF23 MT90503 being applied to them Zarlink Semiconductor Inc. Data Sheet ...

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... (F) interrupt2 (F) Table 1 - CPU Bus Interface Pins 21 Zarlink Semiconductor Inc. Data Sheet Description Intel/Motorola interface address bus. Can be used as a GPI. Intel/Motorola interface data bus, low bits Intel/Motorola interface data bus, high bits. Can be used as a GPIO bit CPU Interface is used ...

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... I/O TTL Zarlink Semiconductor Inc. Data Sheet Description Control memory address bus 1. Control memory address bus 2. Control memory chip select 1. Control memory data bus. Control memory chip select 0 Control memory byte write select 0. Control memory byte write select 1. ...

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... Data and Control memory clocks I PECL Data and Control memory clocks, PECL I PECL Data and Control memory clocks, PECL O PECL Data and Control memory clocks, PECL O PECL Data and Control memory clocks, PECL 23 Zarlink Semiconductor Inc. Data Sheet Description Description ...

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... When this signal is ‘0’, the MT90503 will drive ct_mc low. When ‘1’, the MT90503 will not drive ct_mc (F) H.100/H.110 Message channel receive data. The level of this pin directly reflects the value of ct_mc. 24 Zarlink Semiconductor Inc. Data Sheet Description ...

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... JTAG Test Data In. Should be 1 when not in use O TTL (F) JTAG Test Data Out I TTL (F) JTAG Test Mode Select. Should be 1 when not in use. I TTL (F) JTAG Test Reset. Should be 0 when not in use. Table 7 - Test Pins 25 Zarlink Semiconductor Inc. Data Sheet Description Description ...

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... This pin can also act as a GPI. I/O TTL (F) LED signal. When LED is on, this pin will be '0'. When the LED is off, this pin will be tri-state. This pin can also act as a GPIO. Table 8 - UTOPIA Interface Pins 26 Zarlink Semiconductor Inc. Data Sheet Description ...

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... UTOPIA Port A TX Address bus I TTL (F) UTOPIA Port B RX Parity I/O TTL (F) UTOPIA Port C TX Clock I/O TTL (F) UTOPIA Port C RX Clock 1.I TTL (F) 1. UTOPIA Port C TX Cell Available (in ATM). 2.I 2. UTOPIA Port C TX Enable (in PHY). 27 Zarlink Semiconductor Inc. Data Sheet Description ...

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... Connections,” on page 34 for recommended connections. VSS pin for the FC PLL. See Figure 5, “PLL Pin Connections,” on page 34 for recommended connections. VDD pin for the FC PLL. See Figure 5, “PLL Pin Connections,” on page 34 for recommended connections. 28 Zarlink Semiconductor Inc. Data Sheet Description ...

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... D5 rxa_data[2] ct_c8_b D6 N/C GND D7 N/C VDD D8 N/C phya_alm D9 N/C N/C D10 recov_b N/C D11 recov_f rxa_data[1] D12 N/C rxa_clk D13 N/C N/C D14 N/C 29 Zarlink Semiconductor Inc. Data Sheet Pin Location D23 ct_d[11] D24 N/C D25 ct_c16+ D26 GND D27 ct_c2 D28 ct_c4 D29 GND E1 GND E2 rxa_data[7] E3 rxa_data[6] E4 rxa_data[5] E5 N/C E6 GND E7 ...

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... GND VDD N13 GND VDD N15 GND txa_data[10] N17 GND txa_data[9] N19 GND txa_data[8] N25 dmem_d[3] txa_data[7] N26 dmem_d[13] 30 Zarlink Semiconductor Inc. Data Sheet Pin Location E22 ct_d[29] E23 ct_c16- E24 mc_clock E25 N/C E26 ct_fr_comp E27 ct_sclk E28 ct_sclkx2 E29 GND ...

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... VDD AD2 txb_soc GND AD3 txb_par txb_data[7] AD4 1. txb_data[15] 2. txa_addr[4] txb_data[6] AD5 GND txb_data[5] AD25 GND txb_data[4] AD26 cmem_d[5] 31 Zarlink Semiconductor Inc. Data Sheet Pin Location T25 N/C T26 dmem_a[13] T27 dmem_a[14] T28 dmem_a[18] T29 GND U1 1. rxb_data[13] 2. txa_addr[ rxb_data[12] 2. txa_addr[ ...

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... AH19 inmo_a[7] cmem_a[17] AH20 inmo_a[4] cmem_a[13] AH21 inmo_a[0] cmem_a[9] AH22 cpu_mode[2] cmem_a[7] AH23 cmem_a[16] cmem_par[1] AH24 cmem_a[12] 32 Zarlink Semiconductor Inc. Data Sheet Pin Location AF1 GND AF2 N/C AF3 rxc_data[1] AF4 rxc_data[4] AF5 rxc_data[5] AF6 rxc_data[7] AF7 rxc_clk AF8 txc_data[2] ...

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... Table 12 - Pinout Summary 33 Zarlink Semiconductor Inc. Data Sheet Pin Location AJ22 GND AJ23 GND AJ24 cmem_a[11] AJ25 GND AJ26 GND AJ27 VDD AJ28 GND AJ29 VDD Ground N/C Total 45 45 ...

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... CPU interface. The CPU interface can only be reset by a hardware reset. 1. This product incorporates technology licensed from Melita International Corporation. MT90503 100pF 0.001uF 100pF 0.001uF 301 ohm (1%) 0.01uF (5%) Figure 5 - PLL Pin Connections 1 34 Zarlink Semiconductor Inc. Data Sheet VDD 10uF VDD 10uF ...

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... The associated status register ‘status0’ 0102h contains internal_read_timeout and inmo_read_done bits. Therefore, to de-assert the interrupt the user must write register 0102h bits internal_read_timeout and inmo_read_done respectively. Only then will the interrupt be de-asserted. MT90503 35 Zarlink Semiconductor Inc. Data Sheet ...

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... Zarlink Semiconductor Inc. Data Sheet Control Register Read/Write Data Register Address High Register Address Low Register direct_access ale inmo_a_das inmo_ale* inmo_a_das inmo_ale* inmo_a_das inmo_ale* ...

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... Reset RW 000h Upper extended address [32:20 Reset to 000. Reset 0000h Lower extended address [19:4]. In extended direct addressing, bits 19:16 are employed for 16 bit data bus and bits 19:15 are employed for 8 bit data bus. 37 Zarlink Semiconductor Inc. Data Sheet Description . . . Description Description Description ...

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... Upon assertion of the address within the page the MT90503 will read/write the data with respect to that address. The INMO_A_DAS bit is set when the data read/write occurs. When operating the CPU interface in direct mode with a 16-bit data bus, extended_a[19:16], are employed for the lower address word register 000Ah. MT90503 38 Zarlink Semiconductor Inc. Data Sheet ...

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... Initialize the data and control memory types via registers 0240h, 0242h, 0244h, 0248h, 024Ah, and 024Ch 8 Select UTOPIA clocking methodology at register addresses 0230h, 0232h, 0234h and 0236h. 9 Configure the interrupts’ active_level for interrupt1 and interrupt2 in register 0224h and 0226h. MT90503 39 Zarlink Semiconductor Inc. Data Sheet ...

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... T1 channel signals and one multiframe which is common to all the E1 channel signals. On the input, the multiframing is independent for each TSST and the MT90503 synchronises all of them to its multiframe. MT90503 timeslot * 32 + stream for 8MHz streams (timeslot * 2+ stream for 4MHz streams (timeslot * 4+ stream for 2MHz streams 40 Zarlink Semiconductor Inc. Data Sheet ...

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... A’s cas[3] ’s cas[2] A’s cas[1] A’s cas[0] A’s cas[3] ’s cas[2] A’s cas[1] A’s cas[0] A’s cas[3] ’s cas[2] A’s cas[1] A’s cas[0] A’s cas[3] ’s cas[2] A’s cas[1] A’s cas[ Zarlink Semiconductor Inc. Data Sheet TDM Data Path Controler FIG tdm6 ...

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... When the data is received at the time slot memory sent via the TDM datapath to the external data memory. According to which time slot is currently being used, the TDM control structures are read. MT90503 42 Zarlink Semiconductor Inc. Data Sheet  35 ns window ...

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... Figure 8 - TDM Data Path Controller b12 b11 b10 TX/RX Circular Buffer Address and Size RBW Zarlink Semiconductor Inc. Data Sheet RX TDM Time-Slot Memories Read Data Latch Memory bits Data Memory DMA Controler Reserved ...

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... CPU, the software can check that the count has not returned to zero (which happens if the cells start to arrive again) at some interval equivalent to the cell-loss integration period. MT90503 b12 b11 b10 TX/RX Circular Buffer Address and Size Count 44 Zarlink Semiconductor Inc. Data Sheet Reserved ...

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... When the TDM bus first obtains an external multiframe, it writes the offset field to the correct value between 0 and MT90503 b13 b12 b11 b10 TX/RX Circular Buffer Address and Size RBW Offset CAS Force EI 45 Zarlink Semiconductor Inc. Data Sheet Last TX CAS CM CASWE ...

Page 46

... Man RX CAS is the value of CAS that can be inserted in the place of the one received. This value is only used if the ME bit is set • ME bit Manual CAS insert MT90503 b12 b11 b10 TX/RX Circular Buffer Address and Size Count Man RX CAS Last RX CAS 46 Zarlink Semiconductor Inc. Data Sheet Reserved ...

Page 47

... Address[21:11 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 FIG tdm18 47 Zarlink Semiconductor Inc. Data Sheet New CAS FIG tdm26 ...

Page 48

... Figure 15 - Silent Pattern Buffer A/B in Control Memory MT90503 b10 Pattern B Byte 0 Pattern B Byte 1 Pattern B Byte 2 Pattern B Byte (n-2) Pattern B Byte (n-1) 48 Zarlink Semiconductor Inc. Data Sheet  CDV can be compensated. The Silent Pattern Buffer is n words long, n ranging from 0 to 65535. ...

Page 49

... RX Byte 16 TX Byte 17 RX Byte 17 TX Byte 18 RX Byte 18 TX Byte 19 RX Byte 19 TX Byte 20 RX Byte 20 TX Byte 21 RX Byte 21 TX Byte 22 RX Byte 22 TX Byte 23 RX Byte 23 RX CAS Reserved Underrun Detection Bits 49 Zarlink Semiconductor Inc. Data Sheet ...

Page 50

... RX Byte 8 TX Byte 9 RX Byte 9 TX Byte 10 RX Byte 10 TX Byte 11 RX Byte 11 TX Byte 12 RX Byte 12 TX Byte 13 RX Byte 13 TX Byte 14 RX Byte 14 TX Byte 15 RX Byte 15 RX CAS Underrun Detection Bits 50 Zarlink Semiconductor Inc. Data Sheet ...

Page 51

... RX Byte (Being written by TDM Byte (Being read by TDM Underrun Detection Bits 51 Zarlink Semiconductor Inc. Data Sheet tdm _read_pnt Valid TDM Bytes Waiting to be sent on the TDM Bus rx_sar_write_pnt Valid rx_sar_write_pnt Positions Valid tx_sar_read_pnt Positions ...

Page 52

... TDM side. Therefore, to ensure that the CAS of the multiframe is written by the RX_SAR before the TDM reads it, the pointer passed to the RX_SAR is incremented by one multiframe minus one frame. Therefore, if the TDM_read_pointer would have been 2.5 (two multiframes, five frames), the TDM_read_pnt passed to the RX_SAR is 3.4 (three multiframes, four frames). MT90503 52 Zarlink Semiconductor Inc. Data Sheet ...

Page 53

... RX MultiFrame 1 TX MultiFrame 2 RX MultiFrame 2 TX MultiFrame 3 RX MultiFrame 3 TX MultiFrame 4 RX MultiFrame 4 TX MultiFrame (n/32)-2 RX MultiFrame (n/32)-2 TX MultiFrame (n/32)-1 RX MultiFrame (n/32)-1 Valid rx_sar_write_pnt Positions Reserved Valid tx_sar_read_pnt Positions 53 Zarlink Semiconductor Inc. Data Sheet offset tdm _read_pnt 1 MF offset MINIMUM tdm _cas_read_pnt rx_sar_write_pnt ] ...

Page 54

... RX MultiFrame 1 TX MultiFrame 2 RX MultiFrame 2 TX MultiFrame 3 RX MultiFrame 3 TX MultiFrame 4 RX MultiFrame 4 TX MultiFrame (n/32)-2 RX MultiFrame (n/32)-2 TX MultiFrame (n/32)-1 RX MultiFrame (n/32)-1 Valid rx_sar_write_pnt Positions Reserved Valid tx_sar_read_pnt Positions 54 Zarlink Semiconductor Inc. Data Sheet offset tdm _read_pnt 1 byte offset MINIMUM tdm _cas_read_pnt rx_sar_write_pnt ...

Page 55

... RX MultiFrame 1 TX MultiFrame 2 RX MultiFrame 2 RX MultiFrame 3 TX MultiFrame 3 TX MultiFrame 4 RX MultiFrame 4 TX MultiFrame (n/32)-2 RX MultiFrame (n/32)-2 TX MultiFrame (n/32)-1 RX MultiFrame (n/32)-1 Valid rx_sar_write_pnt Positions Reserved Valid tx_sar_read_pnt Positions 55 Zarlink Semiconductor Inc. Data Sheet offset tdm _read_pnt 1 MF offset MINIMUM tdm _cas_read_pnt rx_sar_write_pnt ...

Page 56

... RX MultiFrame 1 TX MultiFrame 2 RX MultiFrame 2 RX MultiFrame 3 TX MultiFrame 3 TX MultiFrame 4 RX MultiFrame 4 TX MultiFrame (n/32)-2 RX MultiFrame (n/32)-2 TX MultiFrame (n/32)-1 RX MultiFrame (n/32)-1 Valid rx_sar_write_pnt Positions Reserved Valid tx_sar_read_pnt Positions 56 Zarlink Semiconductor Inc. Data Sheet offset tdm _cas_read_pnt tdm _read_pnt 1 byte offset MINIMUM rx_sar_write_pnt ...

Page 57

... Payload Byte #0 Payload Byte #1 Payload Byte #1 Payload Byte #2 Payload Byte #2 Payload Byte #3 Payload Byte #45 Payload Byte #46 Payload Byte #46 Payload Byte #47 Figure 23 - ATM Cell Formats 57 Zarlink Semiconductor Inc. Data Sheet AAL5 Cell 40 Payload Bytes VPI GFC VPI VCI VPI VCI VCI PTI CL ...

Page 58

... An analogy can be made of the above process to a continuous “spinning wheel”, where there is a continual selection and reading of events for each transmit event scheduler frame. Table 19 - Scheduler Event Fields provides a description of the fields for one of the transmit event schedulers. Refer to Figure 24 - Transmit Event Scheduler Process to locate the fields. MT90503 58 Zarlink Semiconductor Inc. Data Sheet ...

Page 59

... MT90503 Figure 24 - Transmit Event Scheduler Process 59 Zarlink Semiconductor Inc. Data Sheet ...

Page 60

... LSBs of this field must be 0. +6/b10:b0 Last Frame = (number of frames in the scheduler Last Frame = 0, the scheduler is one frame long, if Last Frame = 1, the scheduler is two frames long, etc. 60 Zarlink Semiconductor Inc. Data Sheet (Num Env)+1 . The same Events Read ...

Page 61

... This field is the pointer to the TX_SAR Structure used to assemble an ATM cell each time this event is read. This field is appended with "00000" as the LSBs to form a 20-bit address. Table 19 - Scheduler Event Fields Maximum Number of Events per Frame 61 Zarlink Semiconductor Inc. Data Sheet 7 45 183 ...

Page 62

... Frame 1 32 Events Figure 25 - Unsyncrhonised Schedulers Scheduler 0 Scheduler 1 23 Events 17 Events Frame 0 6 Events 24 Events Frame 1 Figure 26 - Synchronised Schedulers Scheduler 0 Scheduler 1 20 Events 5 Events Frame 0 27 Events 12 Events Frame 1 16 Events Frame 2 7 Events Frame 3 62 Zarlink Semiconductor Inc. Data Sheet ...

Page 63

... This means the first event in the transmit event scheduler is always a p-byte event and contains a zero value pointer indicating the start of a structure. MT90503 Transmit Event Scheduler size in KB Number of Frames 48 375 47 240 750 1125 63 Zarlink Semiconductor Inc. Data Sheet (e.g. 32 events per frame 5.875 30 94 141 ...

Page 64

... Base address of control structure from Event 1 TX/RX Circular Buffer Pointer (Same pointer in Channel Association Memory and in TX_SAR Control Structure) Byte read by TX_SAR tdm_write_pnt TX Side RX Side Byte written by TDM Transmit 64 Zarlink Semiconductor Inc. Data Sheet Scheduler 0, Frame 1 Event 0 Event 1 Event 63 TDM Channel 1’s Circular Buffer (in the Data Memory) ...

Page 65

... A is set. The A bit is set by software. If the A bit is reset, the control structure will always be ignored. If the A bit is set, hardware may ignore it for other reasons, such as the control structure not being initialised. 65 Zarlink Semiconductor Inc. Data Sheet ...

Page 66

... AAL1 without pointer. Includes a Sequence number packaged with the cell, as well as the possibility of transmitting SRTS on the AAL1 with pointer. Includes a Sequence number packaged with the cell, and the possibility of transmitting SRTS on the VC 66 Zarlink Semiconductor Inc. Data Sheet ...

Page 67

... The TXD field is used to tell the UTOPIA Module the destination of the assembled ATM cell. The TX_SAR Destination field is decoded as follows: 0000 = Discard ATM cell 0XX1 = Send to TXA port 0X1X = Send to TXB port 01XX = Send to TXC port Others = Reserved Broadcasting to multiple ports is allowed. 67 Zarlink Semiconductor Inc. Data Sheet ...

Page 68

... Whenever a p-byte needs to be generated, the seven LSBs of the P-byte Counter are the value of the p-byte, with parity added as the MSB. The decrementing continues until the value of the P-byte Counter reaches 0 and wraps around again, ending the multiframe and beginning a new one. 68 Zarlink Semiconductor Inc. Data Sheet ...

Page 69

... When this bit is high the channel is active. When this bit is ’0’, the programmable null byte, found in register 0420h, will be transmitted. This field is a pointer to the TX/RX Circular Buffer associated with this channel. "0000 0000" will be appended to this field as the LSBs to form a 22-bit address in data memory. 69 Zarlink Semiconductor Inc. Data Sheet ...

Page 70

... For each VC directed to the SAR portion of the RX_SAR, an RX_SAR control structure exists in external control memory. The structure, similar to that of the TX_SAR, contains information on how to process a cell including: • what type of traffic is being carried (AAL1, CBR-AAL0, AAL5-VTOA) MT90503 Global pointers are shared between the RX_SAR and TDM modules. 70 Zarlink Semiconductor Inc. Data Sheet ...

Page 71

... First entry field gives the position within the structure of the pointer to the first channel. The field is a word pointer and is constant with a value of 0xB. To allow for future structure updates, its value is programmable. Channel 0’s address is located at base_add + (2 * First Entry). 71 Zarlink Semiconductor Inc. Data Sheet ...

Page 72

... Last Entry is the word offset from the 8 kB boundary containing the structure to the last circular buffer pointer in the structure. When set, overrun and underrun slips will generate an RX_SAR Error Report Structure (Figure 32) in the error FIFO in control memory. 72 Zarlink Semiconductor Inc. Data Sheet ...

Page 73

... Pointer” being read from the structure. Current Entry is initialised to the value of First Entry, increments up to Last Entry, and then wraps around to First Entry. This field should be initialised by software to 0Bh. Note: This field should not be written to while the VC is active. 73 Zarlink Semiconductor Inc. Data Sheet ...

Page 74

... When this bit is high the channel is active. When this bit is reset, all received bytes on the channel are discarded. This field is a pointer to the TX/RX Circular Buffer associated with this channel. "0000 0000" will be appended to this field as the LSBs to form a 22-bit address in external data memory. 74 Zarlink Semiconductor Inc. Data Sheet ...

Page 75

... P-byte received = 0x52, Structure length for that VC = 0x18. P-byte is too large AAL1 cells P-byte is 0x15 when 0x17 was expected. AAL1 cells all cells See Figure 31. all cells See Figure 31. Table 25 - RX_SAR errors 75 Zarlink Semiconductor Inc. Data Sheet Payload Size Example ...

Page 76

... VALID BYTE VALID BYTE VALID BYTE VALID BYTE VALID BYTE VALID BYTE VALID BYTE RX_SAR VALID BYTE INVALID BYTE Overrun 76 Zarlink Semiconductor Inc. Data Sheet INVALID BYTE INVALID BYTE INVALID BYTE RX_SAR TDM read INVALID BYTE pointer Write INVALID BYTE Pointer ...

Page 77

... The p-byte detected did not match its parity bit. +2/b12 There was an error detected in the CRC-3. +2/b11 The AAL1 byte detected did not match its parity bit. 77 Zarlink Semiconductor Inc. Data Sheet Seq ...

Page 78

... The sequence number of the cell indicated that a cell was misinserted. This error is always preceded by a single cell loss. +2/b7 The sequence number of the cell indicated that multiple cells were lost. +2/b6 The sequence number of the cell indicated that a single cell was lost. 78 Zarlink Semiconductor Inc. Data Sheet ...

Page 79

... Known cells Append RX LUT Structure Pointer AAL1 Byte A B SRTS and Adaptive Clock Recovery Interface mclk domain Figure 33 - UTOPIA Module 79 Zarlink Semiconductor Inc. Data Sheet TXA UTOPIA Cell FIFO Interface (32 cells) (external) Cell FIFO TXB UTOPIA (32 cells) Interface (external) Cell FIFO ...

Page 80

... Data received on all of the three ports is examined for parity errors and an interrupt is raised if an error is found. Cells are not discarded if a parity error is detected. Register 0304h indicates on which port the parity error is detected. The ATM HEC is not examined on received cells. MT90503 80 Zarlink Semiconductor Inc. Data Sheet ...

Page 81

... OR rx_soc=0 tx_enb=0* rx_enb=1** 53 bytes sent <53 Bytes AND rx_enb=1** Idle rx_enb=1** rx_enb=0* Receive State Machine Figure 35 - PHY Mode State Machines 81 Zarlink Semiconductor Inc. Data Sheet Idle No room for 1 cell (rx_enb=1) Room for 1 cell rx_clav=0 Idle OR (rx_enb=0) rx_soc=0 AND Rx 1st Byte rx_clav=0 rx_clav=1 < ...

Page 82

... TX_SAR input FIFO does not contain any field beyond TXD. The TXD field is not written in any of the output FIFOs Note: The HEC field of the ATM cell is calculated and added for outgoing cells after the cell leaves the FIFO. 82 Zarlink Semiconductor Inc. Data Sheet CLP Reserved ...

Page 83

... Routed according to LUT entry For each bit, result = (match XOR header) AND mask Figure 38 - Match & Mask Example 83 Zarlink Semiconductor Inc. Data Sheet A (See Figure 39 on page 84) Yes Replace VPI[11:8] in NNI = ’ ...

Page 84

... SAR portion of the RX_SAR OCR: OAM Cell Routing ’0000’ = discard ’xxx1’ = send to TXA port ’xx1x’ = send to TXB port ’x1xx’ = send to TXC port ’1xxx’ = send to data cell FIFO (in external control memory) via the RX_SAR 84 Zarlink Semiconductor Inc. Data Sheet ...

Page 85

... LUT Base Address (reg. 0320h) LUT Entry Address b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 Zarlink Semiconductor Inc. Data Sheet vci_na (reg. 0324h VCI Bits num_vci_vpi_bits (reg. 322h ...

Page 86

... ATM mode or PHY mode (Figure 42 on page 87). Please note that the I/O direction of the pins remains the same. MT90503 One of three UTOPIA clock generators Inversion Divider by n (n=1 to 16) One of six UTOPIA Clocks utopia_clk_1 utopia_clk_2 rxa_clk utopia_clk_3 Figure 41 - UTOPIA Clock Generation 86 Zarlink Semiconductor Inc. Data Sheet utopia_clk_1 ...

Page 87

... Figure 42 - External UTOPIA Interface 87 Zarlink Semiconductor Inc. Data Sheet MT90503 - PHY Mode txa_clk (H3) txa_enb ( J5 ) txa_clav ( H2 ) txa_soc (N2) txa_d ( txa_par (N3) rxa_clk (C6) rxa_enb ( A6 ) rxa_clav ( B6 ) rxa_soc (H4) rxa_d ( rxa_par (G2) Port A, PHY mode ...

Page 88

... There are eleven multiplexers (see Table 28, “Source Selection,” on page 89) with 36 possible inputs each (see Table 29, “idclk_a Register,” on page 91): local_netref_16m MT90503 Signal Address recov_a 0860h recov_b 0860h recov_c 0862h recov_d 0862h recov_e 0864h recov_f 0864h recov_g 0866h recov_h 0866h ct_netref1 0868h ct_netref2 0868h 086Ah Table 27 - Multiplexer Registers 88 Zarlink Semiconductor Inc. Data Sheet Bits 13:8 5:0 13:8 5:0 13:8 5:0 13:8 5:0 13:8 5:0 5:0 ...

Page 89

... Table 28 - Source Selection 89 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 90

... TDM clock ct_frame_b TDM clock ct_netref1 TDM clock ct_netref2 TDM clock ref_vca cell arrival ref_vcb cell arrival phy_alm_a PHY Alarm UTOPIA A phy_alm_b PHY Alarm UTOPIA B mclk master clock Table 28 - Source Selection (continued) 90 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 91

... Table 29 - idclk_a Register 91 Zarlink Semiconductor Inc. Data Sheet ) required when n ...

Page 92

... Duty Cycle Modifier 08A0h[2] Clock Frequency Checker 08B0-08B4h Divider 08CAh, 08C0h[1:0] 50% Duty Cycle Modifier Clock Frequency 08C0h[2] Checker 08D0-08D4h Figure 44 - Integer Clock Processor 92 Zarlink Semiconductor Inc. Data Sheet 0880h [2] 0880h [4] idclk_a idclk_valid_a 08A0h [2] 08A0h [4] idclk_b idclk_valid_b 08C0h [2] 08C0h [4] idclk_c idclk_valid_c ...

Page 93

... PLL is in reset state integer divider of pclk_b fractional divider of pclk_b Table 30 - pclk registers f mclk ----------------------------------------- - f = pclk pclk frc ---------------- - pclk + div 65536 1 Module A ’1’ activates adaptive clock recovery S ’1’ activates SRTS clock recovery 2 Table 31 - adapsrts0 Registers 93 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 94

... X" and write to external memory S pclk must be divided order to match the interval of 8 SRTS carrying cells, where normally the number of frames in the scheduler, i.e. 375 for fully filled structured AAL1 the number of channels open 2 (continued) 94 Zarlink Semiconductor Inc. Data Sheet ...

Page 95

... Precise Clock Generator pclk pclk mclk Counter Counter pclk_integer[31:0] pclk_fraction[15:0] cell_counter [31:0] Point Generation Process Cell Counter Figure 45 - Adaptive Clock Recovery 95 Zarlink Semiconductor Inc. Data Sheet mclk_counter[31:0] Write Points to External Control Point Elimination Memory (keeps 1 point out of x cells) ...

Page 96

... Generate two ’ref_vcx’ pulses (lost cell detected Last SN - Yes 1 & Last SN = Discard Cell SecLast (misinserted cell detected) No Discard Cell (multiple cell loss detected) Figure 46 - Adaptive Cell Reception Flow - derived from the local TDM clock, ct_c8_x Zarlink Semiconductor Inc. Data Sheet ...

Page 97

... SRTS Value write_now concatenation srts_value[3:0] RX SRTS Value Writter Lost and (to external memory) bad_srts_value Misinserted Cell Compensation 97 Zarlink Semiconductor Inc. Data Sheet ) (e.g., a stratum 3 clock). This n To external control memory Local To external control memory Remote ...

Page 98

... Tx SRTS is greater than the number of values read by the Tx SAR set if the number of Tx SRTS values is less than that read by the Tx SAR Interrupt Enables P = number of frames in the scheduler Q = number of channels open Table SRTS Registers 98 Zarlink Semiconductor Inc. Data Sheet change srts To TXSAR Description ...

Page 99

... Cell Counter [31:16] +C Cell Counter [15:0] +E Bits Used b12 Set if the accompanying RX SRTS value is valid b11:b8 The 4-bit SRTS value from the incoming ATM cells on the designated VC. b3:b0 The 4-bit SRTS value calculated based on pclk and fnxi 99 Zarlink Semiconductor Inc. Data Sheet Reserved Description ...

Page 100

... It should be noted that turnaround cycles restrict the memory bandwidth and therefore the operation MT90503. Maximum throughput is achieved with full clock speed on MCLK and without pipelined synchronous RAM and turnaround cycles. MT90503 100 Zarlink Semiconductor Inc. Data Sheet ...

Page 101

... RX SAR Output FIFO 33FEh UTOPIA Port A Output FIFO 43FEh UTOPIA Port B Output FIFO 53FEh UTOPIA Port C Output FIFO BFFEh TDM Channel Association Memory 2FFFFEh External Control Memory 7FFFFEh External Data Memory Table 34 - MT90503 Memory Map 101 Zarlink Semiconductor Inc. Data Sheet Name ...

Page 102

... CPU is described in more detail the CPU module section (See 4.1 on page 34). The memory controller generates the CRC-32 needed for each AAL5-VTOA cell. MT90503 Agent Access types TX_SAR Reads RX_SAR Writes TDM transmit Writes TDM receive Reads CPU Reads and writes 102 Zarlink Semiconductor Inc. Data Sheet ...

Page 103

... TDM Module • TX_SAR Module • RX_SAR Module • Clock Registers • Miscellaneous Registers • H.100/H.110 Bus Registers MT90503 Agent Access types Reads and writes Reads and writes Reads and writes CPU Reads and writes 103 Zarlink Semiconductor Inc. Data Sheet ...

Page 104

... If this bit is '1', the average latency to perform a write will be reduced, but the worst-case latency will be increased. RW Reserved. Must be set t o "0". TS When '1', all the status bits in the register will be set. Table 37 - CPU Control Register 104 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 105

... Indicates state of counters and status bits. "00" = normal mode, "01" = reset, "1x" = test mode. These bits are only present for tests and should never be used. RW Reserved. Must be "0000_0000_0000_00" Table 40 - CPU Counter Register 105 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 106

... MHz. RW Divides fast_clk to generate mem_clk RW If '1', mclk_src divided by pll_div_x becomes fast_clk, bypassing the fast_clk PLL RW Resets the module that divides mclk_src before being used as the REF pin of the fast_clk PLL RO Reserved. Always read as "000" 106 Zarlink Semiconductor Inc. Data Sheet ...

Page 107

... This bit is set if the corresponding pin goes for '0' to '1' ROL This bit is set if the corresponding pin goes for '0' to '1' ROL This bit is set if the corresponding pin goes for '0' to '1' RO Reserved. Always read as "0:" 107 Zarlink Semiconductor Inc. Data Sheet ...

Page 108

... This is the value sent out on the corresponding pin, used in conjuction with the OE bit RW This is the value sent out on the corresponding pin, used in conjuction with the OE bit RW This is the value sent out on the corresponding pin, used in conjuction with the OE bit 108 Zarlink Semiconductor Inc. Data Sheet ...

Page 109

... Current level of the corresponding pin RO Current level of the corresponding pin RO Current level of the corresponding pin RO Current level of the corresponding pin RO Current level of the corresponding pin RO Current level of the corresponding pin RO Current level of the corresponding pin RO Reserved. Always read as "0000_0000" 109 Zarlink Semiconductor Inc. Data Sheet ...

Page 110

... This bit is set if the corresponding pin goes for '1' to '0' ROL This bit is set if the corresponding pin goes for '1' to '0' Type RO Reserved. Always read as "0000_0000_0000_000" TS When '1', all the status bits in the register will be set. Table 50 - Main Control Register 110 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 111

... When '1' and the corresponding status bit is '1', an interrupt will be generated When '1' and the corresponding status bit is '1', an interrupt will be generated When '1' and the corresponding status bit is '1', an interrupt will be generated. RW Reserved. Must be "0000_0000_0000" 111 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 112

... When '1', indicates that the interrupt request for this module is active When '1', indicates that the interrupt request for this module is active When '1', indicates that the interrupt request for this module is active. Table 54 - Interrupt Flags Register 112 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 113

... Interrupt polarity and output enable. "00"=active low (open-collector); "01"=active high (open-collector); "10" = drive low; "11" = drive high. Drive low or drive high means that the pin's value will not change regardless of internal interrupts. 113 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 114

... RW When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0 When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. Table 57 - Interrupt1 Enable Register 114 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 115

... When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1 When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1 When '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. Table 58 - Interrupt2 Enable Register 115 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 116

... This should only be enabled if the chip is to drive these clocks, and only after the clock generation has been correctly programmed This bit must be ’0’ as UTOPIA port C clocks must be input only. Table 59 - Utopia Clock Register 116 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 117

... RW Inverts the output of the clock divisor 10:8 RW "000"=txa_clk_in; "001"=txb_clk_in; "010"=txc_clk_in; "011"=rxa_clk_in; "100"=rxb_clk_in;"101"=rxc_clk_in; "110"=mclk; "111"=fast_clk When ’0’, the clock divisor module is held in reset. 117 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 118

... Written to '1' when the source, divisor and inv. have been correctly programmed Inverts the output of the clock divisor 10:8 RW "000"=txa_clk_in; "001"=txb_clk_in; "010"=txc_clk_in; "011"=rxa_clk_in; "100"=rxb_clk_in;"101"=rxc_clk_in; "110"=mclk; "111"=fast_clk. 118 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 119

... Bit Type Position 15:0 RW Mask of address bits [15: used to generate parity for the control memory. A '1' in one of these bits indicates that the corresponding address bit will be used to generate parity. 119 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 120

... RO Reserved. Always read as "0" 15:8 RW Mask of data bits to be used to generate parity for the data memory. A '1' in one of these bits indicates that the corresponding data bit will be used to generate parity. 120 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 121

... Enables UTOPIA port RXA 0' = chip acts as PHY, '1' = chip acts as SAR 0' = 8-bit UTOPIA bus, '1' = 16-bit UTOPIA bus Enables UTOPIA port RXB 0' = chip acts as PHY, '1' = chip acts as SAR 0' = 8-bit UTOPIA bus, '1' = 16-bit UTOPIA bus Table 69 - Utopia Control Register 121 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 122

... This bit should be set to '1' after all PHY/SAR register bits have been programmed, but before all rx_ena bits are set. RW "00" = PHY alarm disabled, "01" = PHY alarm active-high, "10" = PHY alarm active-low, "11" = reserved. Table 70 - Utopia Control1 Register 122 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 123

... Indicates an overflow in the output buffer for port TXA ROL Indicates an overflow in the output buffer for port TXB ROL Indicates an overflow in the output buffer for port TXC CRL Indicates that the cell_loss_counter register has wrapped Table 71 - Utopia Status 0 Register 123 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 124

... Bit is set when look-up engine gives a pulse on clock recovery VC A. Used for tests. Bit is set when look-up engine gives a pulse on clock recovery VC B. Used for tests. Reserved. Must always be "0000_0000_0000" Table 72 - Utopia Status 2 Register 124 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 125

... When emul_mode = "11", writing '1' to this bit will increment the ic_arr counter by 1 When emul_mode = "11", writing '1' to this bit will increment the oc_dep counter by 1 Reserved. Must always be "0000_0" Table 74 - Utopia Counters Register 125 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 126

... A. 0001h = 1 bit used, FFFFh = 16 bits used. When subtracted from vci_n, this indicates the number of VPI bits used. Type RW Indicates the number of VCI bits used to decode the look-up address for port A. 126 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 127

... Reserved. Must always be "0000" Table 80 - Port A VCI Mask Register Type RW For a cell from port considered valid, any bits in its VCI whose corresponding bits in reg 32Eh are '1' must have the value contained in this register. 127 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 128

... Position 15:0 CNT Freerunning counter of the number of cells received on port A. Bit Type Position 15:0 CNT Freerunning counter of the number of cells received on port A. Bit Type Position 15:0 CNT Freerunning counter of the number of cells transmitted on port A. 128 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 129

... Table 87 - Port A Overflow0 Register RW If the cell fill of the Port C output FIFO becomes greater than this value, cells from the port A input FIFO will be blocked backpressure RW Reserved. Must always be "0000_0000_000" Table 88 - Port A Overflow1 Register 129 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 130

... When subtracted from vci_n, this indicates the number of VPI bits used. Bit Type RW Indicates the number of VCI bits used to decode the look-up address for port B. RW Reserved. Must always be "0000_0000_000" 130 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 131

... Table 94 - Port B VPI Mask Register Type RW For a cell from port considered valid, any bits in its VCI whose corresponding bits in reg 34Eh are '1' must have the value contained in this register. Table 95 - Port B VCI Match Register 131 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 132

... Table 96 - Port B VCI Mask Register Type CNT Freerunning counter of the number of cells received on port B. Type CNT Freerunning counter of the number of cells received on port B. Type CNT Freerunning counter of the number of cells transmitted on port B. 132 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 133

... Table 101 - Port B Overflow0 Register Type RW If the cell fill of the Port C output FIFO becomes greater than this value, cells from the port B input FIFO will be blocked backpressure RW Reserved. Must always be "0000_0000_000" 133 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 134

... Type RW For a cell from port considered valid, any bits in its VPI whose corresponding bits in reg 34Ah are '1' must have the value contained in this register. Table 106 - Port C VPI Match Register 134 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 135

... Table 108 - Port C VCI Match Register For a cell from port considered valid, any bits in its VCI whose corresponding bits in this register are '1' must have the value contained in reg 34Ch. Table 109 - Port C VCI Match Register 135 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 136

... Freerunning counter of the number of cells received on port C. Type CNT Freerunning counter of the number of cells received on port C. Type CNT Freerunning counter of the number of cells transmitted on port C. Type CNT Freerunning counter of the number of cells transmitted on port C. 136 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 137

... C input FIFO will be blocked backpressure RW Reserved. Must always be "0000_0000_000" Table 115 - Port C Overflow1 Register Bits [31:16 SAR arrival cell counter. Counts the number of cells received by UTOPIA from the TX SAR 137 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 138

... TX SAR input FIFO will be blocked backpressure If the cell fill of the Port B output FIFO becomes greater than this value, cells from the TX SAR input FIFO will be blocked backpressure Reserved. Must always be "0" 138 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 139

... Normal cell routing for unknow cells received on port C. "xxx1" = Port A, "xx1x" = Port B, "x1xx" = Port C, "1xxx" RX SAR. Cells can be broadcast to multiple destinations by setting multiple bits in this field to '1'. Reserved. Must always be "0000" 139 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 140

... Reserved. Must always be "0000" Type RO Current level of txa_data pins [15:8] RO Current level of rxa_data pins [15:8] Table 125 - GPIO Input0 Register Type RO Current level of txb_data pins [15:8] RO Current level of rxb_data pins [15:8] Table 126 - GPIO Input1 Register 140 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 141

... This bit is set when corresponding pin changes from '1' to '0' ROL This bit is set when corresponding pin changes from '0' to '1' ROL This bit is set when corresponding pin changes from '1' to '0' Table 128 - TXA Data Status Register 141 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 142

... When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. 142 Zarlink Semiconductor Inc. Data Sheet ...

Page 143

... Table 130 - RXA Data Status Register Type IE When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. 143 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 144

... This bit is set when corresponding pin changes from '0' to '1' This bit is set when corresponding pin changes from '1' to '0' This bit is set when corresponding pin changes from '0' to '1' Table 132 - TXB Data Status Register 144 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 145

... When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. 145 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 146

... When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. 146 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 147

... When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. 147 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 148

... This bit is set when corresponding pin changes from '0' to '1' ROL This bit is set when corresponding pin changes from '1' to '0' ROL This bit is set when corresponding pin changes from '0' to '1' Table 136 - GPIO Status Register 148 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 149

... When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. Table 137 - GPIO Status Register 149 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 150

... This is the value sent out on the corresponding pin, used in conjuction with the OE bit RW This is the value sent out on the corresponding pin, used in conjuction with the OE bit Table 140 - GPIO Output2 Register 150 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 151

... OE bit RW Reserved. Must always be "0000_0000_0000" Type RW This is OE bit used to drive the txa_data [15:8] pins RW Reserved. Must always be "0000_0000" Type RW This is OE bit used to drive the txb_data [15:8] pins RW Reserved. Must always be "0000_0000" 151 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 152

... This register is only used for tests: in real operation, it should be left to "00" (32 streams). RW Reserved. Must always be "0000_0000_00" TS When '1', all the status bits in the register will be set. Table 144 - TDM Control Register 152 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 153

... Indicates the TSST on which the last cut VC error occurred. RO Reserved. Always read as "0000" Table 146 - Cut VC TSST Register Type RO Indicates the TSST on which the last underrun error occurred. RO Reserved. Always read as "0000" Table 147 - TSST Underrun Register 153 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 154

... MHz; "10" = 8.192 MHz; "11" = reserved. RW ct_d[11:8] stream clock speed. "00" = 2.048 Mhz; "01" = 4.096 MHz; "10" = 8.192 MHz; "11" = reserved. Table 150 - TDM Interrupt 1 Register 154 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 155

... Polarity of the CAS enable bit on the TDM bus. RW Reserved. Must always be "0000" Bit Type n 9:0 RO The current value of the TDM write pointer sent to the TX SAR. Only used for tests. RO Reserved. Always read as "0000_00" 155 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 156

... Only used for tests. Table 154 - TDM Read Pointer Register Bit Type 14:0 RO Reserved. Always read as "0000_0000_0000_000" When '1', all the status bits in the register will be set. Table 155 - TX_SAR Control Register 156 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 157

... When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. IE Reserved. Always read as ""0000_0000_0000_00" Type 0 PUL Resets the band_per register field. RO Reserved. Always read as "0000_0000_0000_000" 157 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 158

... Reserved. Must always be "00" Type Description RW Bits 19:6 of the address of the FIFO in external memory RW Reserved. Always read as "00" Type Description RW Size of data cell FIFO in 1 cell increments. All zeros = 16k cells. Minimum 4 cells. RW Reserved. Must always be "00" 158 Zarlink Semiconductor Inc. Data Sheet ...

Page 159

... This means that at least some of the frames in the wheels are overloaded. ROL Reserved. Always read as "0000_0000_0000_000" Table 165 - Scheduler Status Register Description When '1' and the corresponding status bit is '1', an interrupt will be generated. Reserved. Always read as "0000_0000_0000_000" 159 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 160

... Enable for wheel 2. Configuration of wheel 2. "000" = normal, "100" = T1, "101" = E1, others reserved. Enable for wheel 3. Configuration of wheel 3. "000" = normal, "100" = T1, "101" = E1, others reserved. Type RW Enable for wheel 4. RW Configuration of wheel 4. "000" = normal,"100" = T1, "101" = E1, others reserved. 160 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 161

... Enable for wheel 9. Configuration of wheel 9. "000" = normal, "100" = T1, "101" = E1, others reserved. Enable for wheel 10. Configuration of wheel 10. "000" = normal, "100" = T1, "101" = E1, others reserved. Enable for wheel 11. Configuration of wheel 11. "000" = normal, "100" = T1, "101" = E1, others reserved. 161 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 162

... When '1', all the status bits in the register will be set. Table 172 - RX_SAR Control Register Bit Type 0 ROL Overflow in the RX SAR data memory access cache. Fatal chip error. 1 ROL Overflow in the data cell FIFO in external memory. Table 173 - RX_SAR Status Register 162 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 163

... When '1' and the corresponding status bit is '1', an interrupt will be generated. IE When '1' and the corresponding status bit is '1', an interrupt will be generated. IE Reserved. Always read as "0000_0000_0000_0" Type RW The CPU's read pointer to the AAL0 cell FIFO. RW Reserved. Must always be "00" 163 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 164

... Reserved. Must always be "00" Type RW Size of data cell FIFO in 1 cell increments. All zeros = 16k cells. RW Reserved. Must always be "00" Type RW The CPU's read pointer to the error report structure FIFO. 164 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 165

... Description RW Bits 19:3 of the address of the error FIFO in external memory RW Reserved. Must always be "0000_0000_0000_000" Type Description RW Bits 19:3 of the address of the error FIFO in external memory Type Description RW Size of the error structure FIFO (in number of error structures, 8-bytes each). 165 Zarlink Semiconductor Inc. Data Sheet ...

Page 166

... Bit Type 3:0 RW Time, in us, that an error structure can wait in the FIFO before an alarm is generated. 15:4 RW Reserved. Must always be "0000_0000_0000" Type RW Time, in us, that an error structure can wait in the FIFO before an alarm is generated. 166 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 167

... Indicates that bits 31:16 of the mclk_count have reached the value contained in the mclk_count_high_alarm1 field. ROL Indicates that bits 31:16 of the mclk_count have reached the value contained in the mclk_count_high_alarm2 field. ROL Reserved. Always read as "0000_0000_0000_0" Table 190 - Clock Status Register 167 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 168

... Reserved. Always read as "0000_0000_0000_0" Type RW This register in conjuction with an interrupt enable can be used as a scheduler Periodic Interrupt Controler. Table 192 - MCLK Alarm 0 Register Type RO Freerunning counter of mclk. Type RO Freerunning counter of mclk. 168 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 169

... Reserved. Must always be "0000_0" RW Selects which pins must be used as the fnxi to generate the TX SRTS value. See Table 28, “Source Selection,” on page 89 for a full description. RW Reserved. Must always be "00" Table 197 - TX_SRTS 0 Register 169 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 170

... For example channel AAL1 structured fully filled channel would require (375 / 24) = 15.625. K must then be converted to the values P and Q using the following equation rouding errors must be made in this conversion. Table 200 - TX_SRTS 4 Register 170 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 171

... When this bit is written to '1', the pclk_div and pclk_frc are loaded into the digital PLL used to synthesize the pclk When '0', the digital PLL used to synthesize pclk is put in reset state. When '1 not longer in reset. 15:8 RW Reserved. Must always be "0000_0000" 171 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 172

... ROL Reserved. Always read as "0000_000" Bit Type Position 0 IE When '1' and the corresponding status bit is '1', and interrupt will be generated. 172 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 173

... RO Reserved. Always read as "00" 13 SRTS mode, this selects the fnxi input used in the RX SRTS block. See Table 28, “Source Selection,” on page 89" for more details. 15:14 RO Reserved. Always read as "00" 173 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 174

... SRTS carrying cells. For example channel AAL1 structured fully filled channel would require (375 / 24) = 15.625 . K must then be converted to the values P and Q using the following equation rouding errors must be made in this conversion. 174 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 175

... The integer part written in the form X / 65536, where X is written in the adapsrts0_pclk_frc register. Type RW For a description see adapsrts0_pclk_div adapsrts0_pclk_div above. Bit Type Position 0 RW See adapsrts0 registers 820h to 83Eh 175 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 176

... RW 15:8 RW Reserved. Must always be "0000_0000" Bit Type Position 0 ROL See Address: 822h, Table 203, “Adaptive SRTS0 1 Register,” on page 172. 1 ROL 2 ROL 3 ROL 4 ROL ROL 7 ROL 8 ROL 15:9 ROL Reserved. Always read as "0000_000" 176 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 177

... IE See "Address: 842h" on page 176 15:9 IE Reserved. Always read as "0000_000" Bit Type Position 5:0 RW See "Address: 826h" on page 173. 7:6 RO 13:8 RW 15:14 RO Bit Position Type 15:0 RW 177 Zarlink Semiconductor Inc. Data Sheet Description Description Description See "Address: 828h" on page 174. ...

Page 178

... Reserved. Must always be "0000_0000" Bit Type Position 15:0 RW See "Address: 82Ch" on page 174. Bit Type 15:0 RW See "Address: 82Eh" on page 175. Table 219 - Adaptive SRTS1 7 Register Bit Type 15:0 RW See "Address: 830h" on page 175. 178 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 179

... Selection" on page 89 for more details. 7:6 RO Reserved. Always read as "00" 13:8 RW This field selects the recov_c output. See Table 28 - "Source Selection" on page 89 for more details. RO Reserved. Always read as "00" Table 223 - Pin Mux 1 Register 179 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 180

... Selection" on page 89 for more details. 7:6 RO Reserved. Always read as "00" 13:8 RW This field selects the ct_netref1 output. See Table 28 - "Source Selection" on page 89 for more details. RO Reserved. Always read as "00" Table 226 - Pin Mux 4 Register 180 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 181

... When '1', the output of the integer clock divisor will be inverted before being sent out. 12:7 RW Reserved. Must always be "0000_00" 13:8 RW This field selects the input of the integer clock divisor. See Table 28 - "Source Selection" on page 89 for more details. 15:14 RW Reserved. Must always be "00" 181 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 182

... When '1' and the corresponding status bit is '1', and interrupt will be generated Reserved. Always read as "00" When '1' and the corresponding status bit is '1', and interrupt will be generated Reserved. Always read as "00" 15:6 RO Reserved. Always read as "0000_0000_00" 182 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 183

... RW When a loss is detected, the output signal indicating this loss is activated (i.e. the value is this register is sent out). '0' = output loss active low; '1' = output loss active high. 15:8 RW Reserved. Must always be "0000_0000" 183 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 184

... Type Position 15:0 RW This regsiter defines the maximum number of mclk cycles between two rising edges of the input clock divided by diviclk0_freqchck_div second rising edge has not been detected in diviclk0_freqchck_max_mclk_cycles, the diviclk0_freq_too_low will be detected. 184 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 185

... Bit Type Position 0 PUL See regsiters 880h to 89Eh 13:8 RW 15:14 RW Reserved. Must always be "00" Bit Type 0 ROLO See register 882h ROLO 3 RO 185 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 186

... RO 15:6 RO Reserved. Always read as "0000_0000_00" Bit Type Position 0 IE See register 884h 15:6 RO Reserved. Always read as "0000_0000_00" Bit Type Position 0 RW See register 886h 186 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 187

... Bit Type Position 5 RW 15:6 RW Reserved. Must always be "0000_0000_00" Bit Type Position 5:0 RW See register 888h 15:8 RW Reserved. Must always be "0000_0000" Bit Type Position 15:0 RW See register 88Ah. Bit Type 15:0 RW See register 890h. 187 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 188

... Table 246 - Integer Clock Divisor2 0 Register MT90503 Bit Type Position 15:0 RW See register 892h. Bit Type Position 15:0 RW See register 894h. Bit Type Position 0 PUL See registers 880h to 89Eh 13:8 RW 15:14 RW Reserved. Must always be "00" 188 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 189

... MT90503 Bit Type Position 0 ROLO See register 8A2h ROLO ROLO 5 RO 15:6 RO Reserved. Always read as "0000_0000_00" Bit Type Position 0 IE See register 8A4h 15:6 RO Reserved. Always read as "0000_0000_00" 189 Zarlink Semiconductor Inc. Data Sheet Description Description ...

Page 190

... Bit Type Position 0 RW See register 8A6h 15:6 RW Reserved. Must always be "0000_0000_00" Bit Type Position 5:0 RW See register 8A8h 15:8 RW Reserved. Must always be "0000_0000" Type RW See register 8AAh. 190 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 191

... Bit Type Position 15:0 RW See register 8B2h. Bit Type Position 15:0 RW See register 8B4h. Type 0 ROL Only used for tests. RO Only used for tests. RO Reserved. Always read as "0000" Table 255 - TX SRTS Debug Register 191 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 192

... Only used for tests. 15:12 RO Reserved. Always read as "0000" Type ROL Only used for tests. ROL Only used for tests. ROL Only used for tests. ROL Only used for tests. ROL Reserved. Always read as "0000_0000_0000" 192 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 193

... ROL Reserved. Always read as "0000_0000_00" M iscellaneous Error Register Bit Type 15:0 RW Size of the silent tone buffers, in bytes minus 1. 0 means 1 byte; FFFFh means 10000h bytes. Table 261 - Silent Tone 2 Register 193 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...

Page 194

... Size of the adaptive point/SRTS value buffer minus one. 0 means 1; FFFFh means 10000h. Bit Type RW The base address of the adaptive point/SRTS value buffer (in points or SRTS values). Note that since adaptive points are 8 words, bits 18:16 of the base address are ignored. 194 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 195

... Type 15:0 RO The chip's write pointer to the adaptive point/SRTS value buffer. Bit Type 15:0 RW The CPU's read pointer to the adaptive point/SRTS value buffer. Type RO The chip's write pointer to the local SRTS value buffer. 195 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 196

... Bit Type 2:0 RW The base address of the adaptive point/SRTS value buffer (in points or SRTS values). Note that since adaptive points are 8 words, bits 18:16 of the base address are ignored. 15:3 RW Reserved. Must always be "0000_0000_0000_0" 196 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 197

... Bit Type 15:0 RW The CPU's read pointer to the adaptive point/SRTS value buffer. Type RO The chip's write pointer to the local SRTS value buffer. Type RW The CPU's read pointer to the local SRTS value buffer. 197 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 198

... Size of the CAS change buffer minus 1. 0 means 1; FFFFh means 10000h. Type RW Base address of the CAS change buffer. Type RW Base address of the CAS change buffer. RW Reserved. Must always be "0000_0000_0000_0" Type RO The chip's write pointer to the CAS change buffer. 198 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 199

... Written to '1' to indicate that CAS change FIFO has been treated. Another alarm will not be generated until the above timeout has elapsed. PUL Reserved. Always read as "0000_0000_0000_000" Table 285 - Treated Pulses Register 199 Zarlink Semiconductor Inc. Data Sheet Description Description Description Description ...

Page 200

... RW clk to tdmint if selected clk is bad: '0' = always sync on selected clk (h100_tdming_clk_sel). ' selected clk fails, switch over to backup clk. TS When '1', all the status bits in the register will be set. Table 286 - H.100 Control 0 Register 200 Zarlink Semiconductor Inc. Data Sheet Description ...