DSPB56362PV100 Freescale Semiconductor, Inc, DSPB56362PV100 Datasheet
DSPB56362PV100
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DSPB56362PV100 Summary of contents
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... The DSP56362 offers 100 million instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V. This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. Document Number: DSP56362 Rev. 4, 08/2006 Contents 1 Overview ...
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Overview This data sheet uses the following conventions: OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) “asserted” Means that a high true (active high) signal is high ...
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Features • Multimode, multichannel decoder software functionality — Dolby Digital and Pro Logic — MPEG2 5.1 — DTS — Bass management • Digital audio post-processing capabilities — 3D Virtual surround sound — Lucasfilm THX5.1 — Soundfield processing — Equalization ...
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Overview – On-Chip Emulation (OnCE‘) module – Joint Action Test Group (JTAG) test access port (TAP) – Address trace mode reflects internal program RAM accesses at the external port • On-Chip Memories — Modified Harvard architecture allows simultaneous access to ...
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Triple timer module with single external interface or GPIO line — On-chip peripheral registers are memory mapped in data memory space • Reduced Power Dissipation — Very low-power (3.3 V) CMOS design — Wait and stop low-power standby modes ...
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Overview 1-6 NOTES DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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Signal/Connection Descriptions 2.1 Signal Groupings The input and output signals of the DSP56362 are organized into functional groups, which are listed in Table 2-1 and illustrated in Figure The DSP56362 is operated from a 3.3 V supply; however, some ...
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Signal Groupings Power Inputs: V PLL CCP 3 V External I/O CCQH 4 V Internal Logic CCQL 3 V Address Bus CCA 4 V Data Bus CCD 2 V Bus Control CCC V HDI08 CCH 2 V SHI/ESAI/DAX/Timer CCS Grounds: ...
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Power Power Name V PLL Power—V CCP input should be provided with an extremely low impedance path to the V V input. CCP V (4) Quiet Core (Low) Power—V CCQL be tied externally to all other chip power inputs. ...
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Ground 2.3 Ground Ground Name GND PLL Ground—GND P extremely low-impedance path to ground. V located as close as possible to the chip package. There is one GND GND PLL Ground 1—GND P1 extremely low-impedance path to ground. There is ...
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Table 2-4 Clock and PLL Signals (continued) Signal Name Type State during Reset PCAP Input Input PINIT/NMI Input Input 2.5 External Memory Expansion Port (Port A) When the DSP56362 enters a low-power standby mode (stop or wait), it releases bus ...
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External Memory Expansion Port (Port A) 2.5.3 External Bus Control Signal Name Type State during Reset AA0–AA3/RA Output Tri-Stated S0–RAS3 CAS Output Tri-Stated RD Output Tri-Stated WR Output Tri-Stated TA Input Ignored Input 2-6 Table 2-7 External Bus Control Signals ...
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Table 2-7 External Bus Control Signals (continued) Signal Name Type State during Reset BR Output Output (deasserted) BG Input Ignored Input BB Input/ Input Output Freescale Semiconductor External Memory Expansion Port (Port A) Signal Description Bus Request— active-low ...
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Interrupt and Mode Control 2.6 Interrupt and Mode Control The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. Signal Name ...
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Table 2-8 Interrupt and Mode Control (continued) Signal Name Type State during Reset MODD/IRQD Input RESET Input 2.7 Host Interface (HDI08) The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The ...
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Host Interface (HDI08) Signal Name Type H0–H7 Input/Output HAD0–HAD7 Input/Output PB0–PB7 Input, Output, or Disconnected HA0 Input HAS/HAS Input PB8 Input, output, or disconnected HA1 Input HA8 Input PB9 Input, Output, or Disconnected 2-10 Table 2-9 Host Interface State during ...
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Signal Name Type HA2 Input HA9 Input PB10 Input, Output, or Disconnected HRW Input HRD/HRD Input PB11 Input, Output, or Disconnected HDS/HDS Input HWR/HWR Input PB12 Input, Output, or Disconnected Freescale Semiconductor Table 2-9 Host Interface (continued) State during Reset ...
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Host Interface (HDI08) Signal Name Type HCS Input HA10 Input PB13 Input, Output, or Disconnected 2-12 Table 2-9 Host Interface (continued) State during Reset GPIO Disconnected Host Chip Select—When HDI08 is programmed to interface a nonmultiplexed host bus and the ...
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Signal Name Type HOREQ/HORE Output HTRQ/HTRQ Output PB14 Input, Output, or Disconnected HACK/HACK Input HRRQ/HRRQ Output PB15 Input, Output, or Disconnected Freescale Semiconductor Table 2-9 Host Interface (continued) State during Reset GPIO Disconnected Host Request—When HDI08 is programmed to interface ...
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Serial Host Interface 2.8 Serial Host Interface The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I Signal Name Signal Type SCK Input or Output SCL Input or Output ...
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Table 2-10 Serial Host Interface Signals (continued) Signal Name Signal Type MOSI Input or Output HA0 Input SS Input HA2 Input HREQ Input or Output Freescale Semiconductor State during Reset Tri-Stated SPI Master-Out-Slave-In—When the SPI is configured as a master, ...
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Enhanced Serial Audio Interface 2.9 Enhanced Serial Audio Interface Table 2-11 Enhanced Serial Audio Interface Signals Signal Signal Type State during Reset Name HCKR Input or Output GPIO Disconnected High Frequency Clock for Receiver—When programmed as an PC2 Input, Output, ...
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Table 2-11 Enhanced Serial Audio Interface Signals (continued) Signal Signal Type State during Reset Name FST Input or Output GPIO Disconnected Frame Sync for Transmitter—This is the transmitter frame sync PC4 Input, Output, or Disconnected SCKR Input or Output GPIO ...
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Enhanced Serial Audio Interface Table 2-11 Enhanced Serial Audio Interface Signals (continued) Signal Signal Type State during Reset Name SDO4 Output GPIO Disconnected Serial Data Output 4—When programmed as a transmitter, SDO4 is SDI1 Input PC7 Input, Output, or Disconnected ...
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Digital Audio Interface (DAX) Table 2-12 Digital Audio Interface (DAX) Signals Signal Type State During Reset Name ACI Input PD0 Input, Output, or Disconnected ADO Output PD1 Input, Output, or Disconnected 2.11 Timer Signal Type State During Reset Name ...
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JTAG/OnCE Interface 2.12 JTAG/OnCE Interface Signal Type State During Reset Name TCK Input TDI Input TDO Output Tri-Stated TMS Input TRST Input DE Input/Output 2-20 Table 2-14 JTAG/OnCE™ Interface Input Test Clock—TCK is a test clock input signal used to ...
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Specifications 3.1 Introduction The DSP56362 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. The DSP56362 specifications are preliminary and are from design simulations, and may not be fully tested or guaranteed. Finalized specifications ...
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Thermal Characteristics 1 Rating Operating temperature range Storage temperature 1 GND = 3.3 V ± . Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not ...
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Table 3-3 DC Electrical Characteristics Characteristics Input leakage current High impedance (off-state) input current (@ 2 0.4 V) Output high voltage = –0.4 µ • TTL ( –10 µA) 4 • CMOS (I OH ...
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Internal Clocks 3.6 Internal Clocks Characteristics Internal operation frequency and CLKOUT with PLL enabled Internal operation frequency and CLKOUT with PLL disabled Internal clock and CLKOUT high period • With PLL disabled • With PLL enabled and MF ≤ 4 ...
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EXTERNAL CLOCK OPERATION The DSP56362 system clock is an externally supplied square wave voltage source connected to EXTAL (Figure 3-1) EXTAL ETH V ILC CLKOUT With PLL Disabled CLKOUT With PLL Enabled 6a Note: The midpoint is 0.5 (V ...
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Phase Lock Loop (PLL) Characteristics Table 3-5 Clock Operation (continued) 100 and 120 MHz Values No. Characteristics 6 CLKOUT rising edge from EXTAL rising edge with PLL enabled ( PDF = 1, Ef > 15 MHz) CLKOUT falling ...
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Reset, Stop, Mode Select, and Interrupt Timing Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values No Characteristics 8 Delay from RESET assertion to all pins at reset value 4 9 Required RESET duration ...
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Reset, Stop, Mode Select, and Interrupt Timing Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values No Characteristics 19 Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for ...
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Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values No Characteristics 27 Interrupt Requests Rate • HI08, ESAI, SHI, Timer • DMA • IRQ, NMI (edge trigger) • IRQ, NMI (level trigger) 28 DMA Requests ...
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Reset, Stop, Mode Select, and Interrupt Timing RESET 8 All Pins A0–A17 CLKOUT 11 RESET A0–A17 3-10 9 Reset Value Figure 3-2 Reset Timing 12 Figure 3-3 Synchronous Reset Timing DSP56362 Technical Data, Rev First Fetch ...
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A0–A17 RD WR IRQA, IRQB, IRQC, IRQD, NMI General Purpose I/O IRQA, IRQB, IRQC, IRQD, NMI IRQA, IRQB, IRQC, IRQD, NMI IRQA, IRQB, IRQC, IRQD, NMI Figure 3-5 External Interrupt Timing (Negative Edge-Triggered) Freescale Semiconductor First Interrupt Instruction Execution/Fetch 20 ...
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Reset, Stop, Mode Select, and Interrupt Timing CLKOUT IRQA, IRQB, IRQC, IRQD, NMI A0–A17 Figure 3-6 Synchronous Interrupt from Wait State Timing RESET MODA, MODB, MODC, MODD, PINIT IRQA A0–A17 Figure 3-8 Recovery from Stop State Using IRQA 3-12 22 ...
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IRQA A0–A17 Figure 3-9 Recovery from Stop State Using IRQA Interrupt Service A0–A17 RD WR IRQA, IRQB, IRQC, IRQD, NMI Figure 3-10 External Memory Access (DMA Source) Timing Freescale Semiconductor 26 25 DMA Source Address 29 First Interrupt Instruction Execution ...
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External Memory Expansion Port (Port A) 3.10 External Memory Expansion Port (Port A) 3.10.1 SRAM Timing Table 3-8 SRAM Read and Write Accesses 100 and 120 MHz No. Characteristics 100 Address valid and AA assertion pulse width 101 Address and ...
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Table 3-8 SRAM Read and Write Accesses 100 and 120 MHz No. Characteristics 104 Address and AA valid to input data valid 105 RD assertion to input data valid 106 RD deassertion to data not valid (data hold time) 107 ...
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External Memory Expansion Port (Port A) Table 3-8 SRAM Read and Write Accesses 100 and 120 MHz No. Characteristics 112 Previous RD deassertion to data active 4 (write) 113 RD deassertion time 114 WR deassertion time 115 Address valid to ...
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Table 3-8 SRAM Read and Write Accesses 100 and 120 MHz No. Characteristics 118 TA setup before deassertion 119 TA hold after deassertion 1 All timings for 100 MHz are measured from 0.5 Vcc ...
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External Memory Expansion Port (Port A) A0–A17 AA0–AA3 D0–D23 3.10.2 DRAM Timing The selection guides provided in Final selection should be based on the timing provided in the following tables example, the selection guide suggests ...
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DRAM Type (tRAC ns) 100 Wait States 2 Wait States Figure 3-13 DRAM Page Mode Wait States Selection Guide Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications) No. Characteristics 131 Page ...
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External Memory Expansion Port (Port A) Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications) No. Characteristics 137 CAS assertion pulse width 138 Last CAS deassertion to RAS deassertion • BRW[1: • BRW[1: • ...
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Table 3-10 DRAM Page Mode Timings, Two Wait States No. Characteristics 131 Page mode cycle time for two consecutive accesses of the 5 same direction Page mode cycle time for mixed (read and write) accesses. 132 CAS assertion to data ...
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External Memory Expansion Port (Port A) Table 3-10 DRAM Page Mode Timings, Two Wait States No. Characteristics 153 RD assertion to data valid 154 RD deassertion to data not valid 155 WR assertion to data active 156 WR deassertion to ...
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Table 3-11 DRAM Page Mode Timings, Three Wait States No. Characteristics 139 CAS deassertion pulse width 140 Column address valid to CAS assertion 141 CAS assertion to column address not valid 142 Last column address valid to RAS deassertion 143 ...
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External Memory Expansion Port (Port A) Table 3-12 DRAM Page Mode Timings, Four Wait States 100 and 120MHz No. Characteristics 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read ...
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Table 3-12 DRAM Page Mode Timings, Four Wait States 100 and 120MHz No. Characteristics 149 Data valid to CAS assertion (write) 150 CAS assertion to data not valid (write) 151 WR assertion to CAS assertion 152 Last RD assertion to ...
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External Memory Expansion Port (Port A) RAS CAS Row A0–A17 Add WR RD D0–D23 Figure 3-14 DRAM Page Mode Write Accesses 3-26 131 137 139 140 141 Column Column Address Address 151 144 145 146 155 150 149 Data Out ...
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RAS CAS Row A0–A17 Add WR RD D0–D23 Figure 3-15 DRAM Page Mode Read Accesses Freescale Semiconductor 131 137 139 140 141 Column Column Address Address 143 133 153 Data In Data In DSP56362 Technical Data, Rev. 4 External Memory ...
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External Memory Expansion Port (Port A) DRAM Type (tRAC ns) Note: This figure should be use for primary selection. For exact 100 Wait States 8 Wait States Figure 3-16 DRAM Out-of-Page Wait States Selection ...
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Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States No. Characteristics 165 RAS assertion to CAS deassertion 166 CAS assertion pulse width 167 RAS assertion to CAS assertion 168 RAS assertion to column address valid 169 CAS deassertion to ...
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External Memory Expansion Port (Port A) Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States No. Characteristics 191 RD assertion to RAS deassertion 192 RD assertion to data valid 193 RD deassertion to data not valid 194 WR assertion ...
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Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States No. Characteristics 172 RAS assertion to row address not valid 173 Column address valid to CAS assertion 174 CAS assertion to column address not valid 175 RAS assertion to column ...
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External Memory Expansion Port (Port A) Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States No. Characteristics 157 Random read or write cycle time 158 RAS assertion to data valid (read) 159 CAS assertion to data valid (read) 160 ...
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Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States No. Characteristics 182 WR assertion pulse width 183 WR assertion to RAS deassertion 184 WR assertion to CAS deassertion 185 Data valid to CAS assertion (write) 186 CAS assertion to ...
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External Memory Expansion Port (Port A) Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States 100 and 120MHz No. Characteristics 161 CAS deassertion to data not valid (read hold time) 162 RAS deassertion to RAS assertion 163 RAS assertion ...
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Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States 100 and 120MHz No. Characteristics 186 CAS assertion to data not valid (write) 187 RAS assertion to data not valid (write) 188 WR assertion to CAS assertion 189 CAS assertion ...
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External Memory Expansion Port (Port A) 162 RAS 169 CAS A0–A17 WR RD D0–D23 Figure 3-17 DRAM Out-of-Page Read Access 3-36 157 163 165 167 164 168 170 166 171 173 175 Row Address Column Address 172 176 177 191 ...
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RAS 169 CAS A0–A17 WR RD D0–D23 Figure 3-18 DRAM Out-of-Page Write Access Freescale Semiconductor 157 163 165 167 164 168 170 166 171 173 172 176 Row Address Column Address 181 175 188 180 182 184 183 187 ...
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External Memory Expansion Port (Port A) RAS 190 170 CAS 177 WR 3.10.3 Synchronous Timings (SRAM) Table 3-17 External Bus Synchronous Timings (SRAM Access) No. Characteristics 198 CLKOUT high to address, and AA valid 199 CLKOUT high to address, and ...
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Table 3-17 External Bus Synchronous Timings (SRAM Access) No. Characteristics 209 CLKOUT high to RD deassertion 210 CLKOUT high to WR assertion 211 CLKOUT high to WR deassertion 1 External bus synchronous timings should be used only for reference to ...
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External Memory Expansion Port (Port A) CLKOUT A0–A17 AA0–AA3 TA WR D0–D23 RD D0–D23 Figure 3-20 Synchronous Bus Timings SRAM 1 WS (BCR Controlled) 3-40 198 210 203 Data Out 202 208 206 DSP56362 Technical Data, Rev. 4 199 201 ...
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CLKOUT 198 A0–A17 AA0–AA3 TA WR 210 D0–D23 208 RD D0–D23 Figure 3-21 Synchronous Bus Timings SRAM 2 WS (TA Controlled) 3.10.4 Arbitration Timings No. Characteristics 212 CLKOUT high to BR assertion/deassertion 213 BG asserted/deasserted to CLKOUT high (setup) 214 ...
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External Memory Expansion Port (Port A) Table 3-18 Arbitration Bus Timings No. Characteristics 218 CLKOUT high to BB deassertion (output) 219 BB high to BB high impedance (output) 220 CLKOUT high to address and controls active 221 CLKOUT high to ...
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CLKOUT 212 A0–A17 RD, WR AA0–AA3 Figure 3-23 Bus Release Timings Case 1 (BRT Bit in OMR Cleared) Freescale Semiconductor External Memory Expansion Port (Port A) 214 213 219 218 221 224 223 DSP56362 Technical Data, Rev. ...
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External Memory Expansion Port (Port A) CLKOUT 212 A0–A17 RD, WR AA0–AA3 Figure 3-24 Bus Release Timings Case 2 (BRT Bit in OMR Set) Table 3-19 Asynchronous Bus Arbitration timing No. Characteristics 250 BB assertion window from ...
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BG1 BB BG2 Figure 3-25 Asynchronous Bus Arbitration Timing BG1 BG2 Figure 3-26 Asynchronous Bus Arbitration Timing Background explanation for Asynchronous Bus Arbitration: The asynchronous bus arbitration is enabled by internal synchronization circuits on BG, and BB inputs. These synchronization ...
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Parallel Host Interface (HDI08) Timing 3.11 Parallel Host Interface (HDI08) Timing Table 3-20 Host Interface (HDI08) Timing No. Characteristics 317 Read data strobe assertion width HACK read assertion width 318 Read data strobe deassertion width HACK read deassertion width 319 ...
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Table 3-20 Host Interface (HDI08) Timing No. Characteristics 333 HCS hold time after data strobe deassertion 334 Address (AD7–AD0) setup time before HAS deassertion (HMUX=1) 335 Address (AD7–AD0) hold time after HAS deassertion (HMUX=1) 336 A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W ...
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Parallel Host Interface (HDI08) Timing 8 The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode. 9 The data strobe is host read (HRD) or host write (HWR) in the ...
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HA0–HA2 HCS HWR, HDS HD0–HD7 HOREQ, HRRQ, HTRQ Figure 3-29 Write Timing Diagram, Non-Multiplexed Bus Freescale Semiconductor 336 331 320 321 324 340 341 DSP56362 Technical Data, Rev. 4 Parallel Host Interface (HDI08) Timing 337 333 325 339 AA0485 3-49 ...
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Parallel Host Interface (HDI08) Timing HA8–HA10 322 HAS HRD, HDS HAD0–HAD7 HOREQ, HRRQ, HTRQ Figure 3-30 Read Timing Diagram, Multiplexed Bus 3-50 336 337 323 317 334 335 327 328 329 Address Data 326 340 341 DSP56362 Technical Data, Rev. ...
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HA8–HA10 322 HAS HWR, HDS HAD0–HAD7 HOREQ, HRRQ, HTRQ Figure 3-31 Write Timing Diagram, Multiplexed Bus HOREQ (Output) HACK (Input) H0–H7 (Input) Figure 3-32 Host DMA Write Timing Diagram Freescale Semiconductor 336 323 320 334 324 335 Data Address 340 ...
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Serial Host Interface SPI Protocol Timing Figure 3-33 Host DMA Read Timing Diagram 3.12 Serial Host Interface SPI Protocol Timing Table 3-21 Serial Host Interface SPI Protocol Timing No. Characteristics 140 Tolerable spike width on clock or data in 141 ...
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Table 3-21 Serial Host Interface SPI Protocol Timing (continued) No. Characteristics 144 Serial clock rise/fall time 146 SS assertion to first SCK edge CPHA = 0 CPHA = 1 147 Last SCK edge to SS not asserted 148 Data input ...
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Serial Host Interface SPI Protocol Timing Table 3-21 Serial Host Interface SPI Protocol Timing (continued) No. Characteristics 159 SS deassertion to HREQ output not deasserted (CPHA = 0) 160 SS deassertion pulse width (CPHA = 0) 161 HREQ in assertion ...
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SS (Input) SCK (CPOL = 0 (Output) SCK (CPOL = 1 (Output) MISO (Input) MOSI (Output) 161 HREQ (Input) Freescale Semiconductor 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 162 163 Figure 3-35 SPI Slave Timing ...
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Serial Host Interface SPI Protocol Timing SS (Input) SCK (CPOL = 0 (Output) SCK (CPOL = 1 (Output) MISO (Input) MOSI (Output) 161 HREQ (Input) 3-56 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 162 163 ...
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SS (Input) 142 SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 154 150 MISO (Output) 148 MOSI (Input) HREQ (Output) Freescale Semiconductor 143 144 142 144 143 152 153 153 MSB 148 149 MSB Valid 157 Figure ...
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Serial Host Interface SPI Protocol Timing SS (Input) 142 SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 152 150 MISO (Output) MOSI (Input) HREQ (Output) 3-58 143 144 142 144 143 152 MSB 148 149 MSB Valid ...
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Serial Host Interface (SHI) I No. Characteristics Tolerable spike width on SCL or SDA Filters bypassed Narrow filters enabled Wide filters enabled 171 SCL clock frequency 172 Bus free time 173 Start condition set-up time 174 Start condition hold ...
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Serial Host Interface (SHI Protocol Timing Table 3-22 SHI I No. Characteristics 187 Last SCL edge to HREQ output not deasserted Filters bypassed Narrow filters enabled Wide filters enabled 188 HREQ in assertion to first SCL edge ...
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Table 3-23 SCL Serial Clock Cycle generated as Master Filters bypassed Narrow filters enabled Wide filters enabled EXAMPLE: For DSP clock frequency of 100 MHz (i. 100 KHz (i. 10µs), T SCL SCL T ...
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Enhanced Serial Audio Interface Timing 3.14 Enhanced Serial Audio Interface Timing Table 3-24 Enhanced Serial Audio Interface Timing , 1 No. Characteristics 5 430 Clock cycle 431 Clock high period • For internal clock • For external clock 432 Clock ...
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Table 3-24 Enhanced Serial Audio Interface Timing (continued No. Characteristics 443 FSR input hold time after RXC falling edge 444 Flags input setup before RXC falling edge 445 Flags input hold time after RXC falling edge 446 TXC ...
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Enhanced Serial Audio Interface Timing Table 3-24 Enhanced Serial Audio Interface Timing (continued No. Characteristics 458 FST input (wl) to data out enable from high impedance 459 FST input (wl) to transmitter drive enable assertion 460 FST input ...
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TXC (Input/Output) FST (Bit) Out FST (Word) Out Data Out Transmitter Drive Enable 457 FST (Bit) In FST (Word) In Flags Out Note: In network mode, output flag transitions can occur at the start of each time slot within ...
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Enhanced Serial Audio Interface Timing RXC (Input/Output) FSR (Bit) Out FSR (Word) Out Data In FSR (Bit) In FSR (Word) In Flags In HCKT SCKT(output) 3-66 430 431 432 433 434 437 439 First Bit 441 443 442 444 Figure ...
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HCKR SCKR (output) 3.15 Digital Audio Transmitter Timing Table 3-25 Digital Audio Transmitter Timing No. Characteristic 1 ACI frequency 220 ACI period 221 ACI high duration 222 ACI low duration 223 ACI rising edge to ADO valid 1 In order ...
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Timer Timing 3.16 Timer Timing No. Characteristics 480 TIO Low 481 TIO High 482 Timer setup time from TIO (Input) assertion to CLKOUT rising edge 483 Synchronous timer delay time from CLKOUT rising edge to the external memory access address ...
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CLKOUT TIO (Output) 3.17 GPIO Timing No. Characteristics 490 CLKOUT edge to GPIO out valid (GPIO out delay time) 491 CLKOUT edge to GPIO out not valid (GPIO out hold time) 492 GPIO In valid to CLKOUT edge (GPIO in ...
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JTAG Timing CLKOUT (Output) GPIO (Output) GPIO (Input) A0–A17 Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register. GPIO (Output) 3.18 JTAG Timing No. 500 TCK frequency of ...
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No. 508 TMS, TDI data setup time 509 TMS, TDI data hold time 510 TCK low to TDO data valid 511 TCK low to TDO high impedance 512 TRST assert time 513 TRST setup time to TCK low 1 V ...
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JTAG Timing TCK VIL (Input) Data Inputs Data Outputs Data Outputs Data Outputs Figure 3-50 Boundary Scan (JTAG) Timing Diagram TCK VIL (Input) TDI TMS (Input) TDO (Output) TDO (Output) TDO (Output) Figure 3-51 Test Access Port Timing Diagram 3-72 ...
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TCK (Input) TRST (Input) 512 3. Module TimIng n No. Characteristics 500 TCK frequency of operation 514 DE assertion time in order to enter Debug mode 515 Response time when DSP56362 is executing NOP instructions from internal memory ...
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OnCE Module TimIng 3-74 NOTES DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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Packaging 4.1 Pin-out and Package Information This section provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Descriptions” are allocated for the package. The DSP56362 ...
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LQFP Package Description 109 CCD GND D D9 D10 D11 D12 D13 D14 V CCD GND D D15 D16 D17 D18 D19 V CCQL GND Q D20 V CCD GND D D21 D22 D23 MODD MODC MODB ...
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Table 4-1 DSP56362 LQFP Signal Identification by Pin Number 1 Pin No. Signal Name 1 SCK/SCL 2 SS/HA2 3 HREQ 4 SDO0 or PC11 5 SDO1 or PC10 6 SDO2/SDI3 or PC9 7 SDO3/SDI2 or PC8 8 V CCS 9 ...
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LQFP Package Description Table 4-1 DSP56362 LQFP Signal Identification by Pin Number (continued) 1 Pin No. Signal Name CCA 81 GND ...
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Table 4-2 DSP56362 LQFP Signal Identification by Name Signal Name Pin No. not connected A10 88 A11 89 A12 92 A13 93 A14 94 A15 97 A16 98 A17 ...
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LQFP Package Description Table 4-2 DSP56362 LQFP Signal Identification by Name (continued) Signal Name Pin No CAS 52 CLKOUT 59 D0 100 D1 101 D10 114 D11 115 D12 116 HOREQ/HOREQ 24 HRD/HRD 22 HREQ 3 HRRQ/HRRQ 23 ...
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Table 4-2 DSP56362 LQFP Signal Identification by Name (continued) Signal Name Pin No. NMI 61 PB0 43 PB1 42 PB10 31 PB11 22 PB12 21 PB13 30 PB14 24 PB15 23 PB2 41 PB3 40 PB4 37 PB5 36 PB6 ...
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LQFP Package Mechanical Drawing 4.3 LQFP PACKAGE MECHANICAL DRAWING Figure 4-2 DSP56362 144-pin LQFP Package 4-8 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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Design Considerations 5.1 Thermal Design Considerations An estimation of the chip junction temperature, T Where ambient temperature ° package junction-to-ambient thermal resistance °C/W θ power dissipation in package W D Historically, thermal ...
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Electrical Design Considerations • To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat ...
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Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the V • All inputs must ...
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PLL Performance Issues • Disable unused peripherals. • Disable unused pin activity (e.g., CLKOUT, XTAL). One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (i.e., to compensate for measured ...
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Frequency Jitter Performance The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF < 10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) ...
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Host Port Considerations significance, the host could read the wrong combination. Therefore, read the bits twice and check for consensus. • Overwriting the Host Vector—The host interface programmer should change the host vector (HV) register only when the host command ...
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... Ordering Information Consult a Freescale Semiconductor, Inc. sales office or authorized distributor to determine product availability and to place an order. For information on ordering this and all DSP Audio products, review the SG1004 selector guide at http://www.freescale.com. Freescale Semiconductor DSP56362 Technical Data, Rev. 4 6-1 ...
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NOTES DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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Appendix A Power Consumption Benchmark The following benchmark program permits evaluation of DSP power usage in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate instructions with a set of synthetic DSP application data ...
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XLOAD_LOOP ; ; Load the Y-data ; move move do move move YLOAD_LOOP ; jmp PROG_START move move move move ; clr clr move move move move bset ; sbr dor mac mac add mac mac move ...
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...
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XDAT_END YDAT_START ; org ...
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YDAT_END Freescale Semiconductor $4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF $6162BC $E4A245 DSP56362 ...
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A-6 NOTES DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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Appendix B IBIS Model [IBIS ver] [File name] 56362.ibs [File Rev] 0.0 [Date] 29/6/2000 [Component] 56362 [Manufacturer] Freescale [Package] |variable typ R_pkg L_pkg C_pkg [Pin]signal_name model_name 1 sck 2 ss_ 3 hreq_ 4 sdo0 5 sdo1 6 sdoi23 7 sdoi32 ...
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33 hp8 34 hp7 35 hp6 36 hp5 37 hp4 38 svcc 39 sgnd 40 hp3 41 hp2 42 hp1 43 hp0 44 ires_ 45 pvcc 46 pcap 47 pgnd 48 pgnd1 49 qvcch 50 aa3 51 aa2 52 cas_ ...
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89 eab11 90 qgnd 91 qvcc 92 eab12 93 eab13 94 eab14 95 qvcch 96 agnd 97 eab15 98 eab16 99 eab17 100 edb0 101 edb1 102 edb2 103 dvcc 104 dgnd 105 edb3 106 edb4 107 edb5 108 edb6 ...
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Model_type Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF | | [Voltage Range] [GND_clamp] |voltage I(typ) | -3.30e+00 -5.21e+02 -3.10e+00 -4.69e+02 -2.90e+00 -4.18e+02 -2.70e+00 -3.67e+02 -2.50e+00 -3.16e+02 -2.30e+00 -2.65e+02 -2.10e+00 -2.14e+02 -1.90e+00 -1.63e+02 -1.70e+00 -1.13e+02 ...
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-1.50e+00 -7.83e+01 -1.30e+00 -4.43e+01 -1.10e+00 -1.02e+01 -9.00e-01 -5.10e-02 -7.00e-01 -3.65e-02 -5.00e-01 -2.65e-02 -3.00e-01 -1.62e-02 -1.00e-01 -5.49e-03 1.000e-01 5.377e-03 3.000e-01 1.516e-02 5.000e-01 2.370e-02 7.000e-01 3.098e-02 9.000e-01 3.700e-02 1.100e+00 4.175e-02 1.300e+00 4.531e-02 1.500e+00 4.779e-02 1.700e+00 4.935e-02 1.900e+00 5.013e-02 2.100e+00 5.046e-02 2.300e+00 5.063e-02 ...
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-1.50e+00 2.811e-04 -1.30e+00 2.810e-04 -1.10e+00 2.809e-04 -9.00e-01 2.808e-04 -7.00e-01 2.997e-04 -5.00e-01 1.750e-02 -3.00e-01 1.048e-02 -1.00e-01 3.487e-03 1.000e-01 -3.40e-03 3.000e-01 -9.69e-03 5.000e-01 -1.52e-02 7.000e-01 -2.02e-02 9.000e-01 -2.46e-02 1.100e+00 -2.84e-02 1.300e+00 -3.14e-02 1.500e+00 -3.37e-02 1.700e+00 -3.55e-02 1.900e+00 -3.68e-02 2.100e+00 -3.78e-02 2.300e+00 -3.85e-02 ...
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R_load = 50.00 |voltage I(typ dV/dt_r 1.030/0.465 | | dV/dt_f 1.290/0.671 | | [Model] ip5b_o Model_type Polarity Non-Inverting ...
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1.500e+00 4.779e-02 1.700e+00 4.935e-02 1.900e+00 5.013e-02 2.100e+00 5.046e-02 2.300e+00 5.063e-02 2.500e+00 5.075e-02 2.700e+00 5.085e-02 2.900e+00 5.090e-02 3.100e+00 4.771e-02 3.300e+00 4.525e-02 3.500e+00 4.657e-02 3.700e+00 4.904e-02 3.900e+00 5.221e-02 4.100e+00 5.524e-02 4.300e+00 5.634e-02 4.500e+00 5.751e-02 4.700e+00 5.634e-02 4.900e+00 5.648e-02 5.100e+00 5.664e-02 5.300e+00 5.679e-02 ...
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1.500e+00 -3.37e-02 1.700e+00 -3.55e-02 1.900e+00 -3.68e-02 2.100e+00 -3.78e-02 2.300e+00 -3.85e-02 2.500e+00 -3.91e-02 2.700e+00 -3.96e-02 2.900e+00 -4.01e-02 3.100e+00 -4.04e-02 3.300e+00 -4.08e-02 3.500e+00 -4.11e-02 3.700e+00 -4.14e-02 3.900e+00 -4.17e-02 4.100e+00 -4.32e-02 4.300e+00 -4.08e-01 4.500e+00 -2.73e+01 4.700e+00 -6.13e+01 4.900e+00 -9.54e+01 5.100e+00 -1.38e+02 5.300e+00 -1.89e+02 ...
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Model_type Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF | | [Voltage Range] [Pulldown] |voltage I(typ) | -3.30e+00 -5.20e+02 -3.10e+00 -4.69e+02 -2.90e+00 -4.18e+02 -2.70e+00 -3.67e+02 -2.50e+00 -3.16e+02 -2.30e+00 -2.65e+02 -2.10e+00 ...
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I(typ) | -3.30e+00 2.686e+02 -3.10e+00 2.428e+02 -2.90e+00 2.170e+02 -2.70e+00 ...
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I(typ) | -3.30e+00 -5.20e+02 -3.10e+00 -4.69e+02 -2.90e+00 -4.18e+02 -2.70e+00 ...
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R_load = 50.00 |voltage I(typ dV/dt_r 1.680/0.164 | | dV/dt_f 1.690/0.219 | | [Model] icba_o Model_type Polarity Non-Inverting C_comp 5.00pF | | [Voltage Range] [Pulldown] |voltage I(typ) | -3.30e+00 -5.20e+02 ...
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2.700e+00 1.445e-01 2.900e+00 1.450e-01 3.100e+00 1.454e-01 3.300e+00 1.458e-01 3.500e+00 1.461e-01 3.700e+00 1.464e-01 3.900e+00 1.469e-01 4.100e+00 1.490e-01 4.300e+00 1.501e+00 4.500e+00 1.813e+01 4.700e+00 3.540e+01 4.900e+00 5.269e+01 5.100e+00 7.541e+01 5.300e+00 1.012e+02 5.500e+00 1.270e+02 5.700e+00 1.527e+02 5.900e+00 1.785e+02 6.100e+00 2.043e+02 6.300e+00 2.301e+02 6.500e+00 2.559e+02 ...
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2.700e+00 -1.46e-01 2.900e+00 -1.48e-01 3.100e+00 -1.49e-01 3.300e+00 -1.50e-01 3.500e+00 -1.52e-01 3.700e+00 -1.53e-01 3.900e+00 -1.54e-01 4.100e+00 -1.57e-01 4.300e+00 -5.25e-01 4.500e+00 -2.74e+01 4.700e+00 -6.14e+01 4.900e+00 -9.55e+01 5.100e+00 -1.38e+02 5.300e+00 -1.89e+02 5.500e+00 -2.40e+02 5.700e+00 -2.91e+02 5.900e+00 -3.42e+02 6.100e+00 -3.93e+02 6.300e+00 -4.44e+02 6.500e+00 -4.95e+02 ...
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R_load = 50.00 |voltage I(typ dV/dt_r 1.680/0.164 | | dV/dt_f 1.690/0.219 | | [Model] icbc_o Model_type ...
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1.300e+00 1.688e-02 1.500e+00 9.632e-02 1.700e+00 1.012e-01 1.900e+00 1.039e-01 2.100e+00 1.053e-01 2.300e+00 1.060e-01 2.500e+00 1.065e-01 2.700e+00 1.069e-01 2.900e+00 1.073e-01 3.100e+00 1.076e-01 3.300e+00 1.078e-01 3.500e+00 1.081e-01 3.700e+00 1.083e-01 3.900e+00 1.086e-01 4.100e+00 1.103e-01 4.300e+00 1.437e+00 4.500e+00 1.800e+01 4.700e+00 3.519e+01 4.900e+00 5.241e+01 5.100e+00 7.505e+01 ...
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1.300e+00 -1.03e-02 1.500e+00 -9.03e-02 1.700e+00 -9.49e-02 1.900e+00 -9.84e-02 2.100e+00 -1.01e-01 2.300e+00 -1.03e-01 2.500e+00 -1.05e-01 2.700e+00 -1.06e-01 2.900e+00 -1.07e-01 3.100e+00 -1.08e-01 3.300e+00 -1.09e-01 3.500e+00 -1.10e-01 3.700e+00 -1.11e-01 3.900e+00 -1.11e-01 4.100e+00 -1.14e-01 4.300e+00 -4.76e-01 4.500e+00 -2.73e+01 4.700e+00 -6.14e+01 4.900e+00 -9.54e+01 5.100e+00 -1.38e+02 ...
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R_load = 50.00 |voltage ...
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I(typ) | -3.30e+00 2.667e+02 -3.10e+00 2.411e+02 -2.90e+00 2.155e+02 -2.70e+00 1.898e+02 -2.50e+00 1.642e+02 -2.30e+00 1.386e+02 -2.10e+00 1.130e+02 -1.90e+00 8.739e+01 -1.70e+00 6.178e+01 -1.50e+00 4.346e+01 -1.30e+00 2.634e+01 -1.10e+00 9.237e+00 -9.00e-01 2.454e-02 -7.00e-01 ...
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-3.00e-01 -1.11e-02 -1.00e-01 -3.77e-03 1.000e-01 3.729e-03 3.000e-01 1.076e-02 5.000e-01 1.723e-02 7.000e-01 2.311e-02 9.000e-01 2.836e-02 1.100e+00 3.292e-02 1.300e+00 3.675e-02 1.500e+00 3.979e-02 1.700e+00 4.205e-02 1.900e+00 4.347e-02 2.100e+00 4.413e-02 2.300e+00 4.445e-02 2.500e+00 4.465e-02 2.700e+00 4.479e-02 2.900e+00 4.492e-02 3.100e+00 4.502e-02 3.300e+00 4.511e-02 3.500e+00 4.519e-02 ...
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-3.00e-01 1.208e-02 -1.00e-01 3.994e-03 1.000e-01 -3.88e-03 3.000e-01 -1.11e-02 5.000e-01 -1.76e-02 7.000e-01 -2.35e-02 9.000e-01 -2.86e-02 1.100e+00 -3.30e-02 1.300e+00 -3.65e-02 1.500e+00 -3.92e-02 1.700e+00 -4.12e-02 1.900e+00 -4.26e-02 2.100e+00 -4.36e-02 2.300e+00 -4.43e-02 2.500e+00 -4.49e-02 2.700e+00 -4.54e-02 2.900e+00 -4.58e-02 3.100e+00 -4.61e-02 3.300e+00 -4.65e-02 3.500e+00 -4.68e-02 ...
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I(typ) | -3.30e+00 2.667e+02 -3.10e+00 2.411e+02 -2.90e+00 2.155e+02 -2.70e+00 1.898e+02 -2.50e+00 1.642e+02 -2.30e+00 1.386e+02 -2.10e+00 1.130e+02 -1.90e+00 8.739e+01 -1.70e+00 6.178e+01 -1.50e+00 4.346e+01 -1.30e+00 2.634e+01 -1.10e+00 9.237e+00 -9.00e-01 2.454e-02 -7.00e-01 8.741e-05 -5.00e-01 ...
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I(typ) | -3.30e+00 2.653e+02 -3.10e+00 2.398e+02 -2.90e+00 2.143e+02 -2.70e+00 1.888e+02 -2.50e+00 1.633e+02 -2.30e+00 ...
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Index A ac electrical characteristics 3 Address Trace mode 3, 38, 41 applications 5 arbitration bus timings 41 B bootstrap ROM 3 Boundary Scan (JTAG Port) timing diagram 72 bus address 2 data 2 multiplexed 2 non-multiplexed 2 bus acquisition ...
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Source) timing 13 External Memory Expansion Port 14 F functional groups 2 functional signal groups 1 G General Purpose ...
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O off-chip memory 3 OnCE module timing 73 OnCE module 3, 20 Debug request 73 on-chip DRAM controller 4 On-Chip Emulation module 3 on-chip memory 3 operating mode select timing 12 P package 144-pin TQFP 1 TQFP description 1, 3 ...
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General Purpose I/O (GPIO) Timing 62 OnCE™ (On Chip Emulator) Timing 62 Serial Host Interface (SHI) SPI Protocol Tim- ing 52 Serial Host Interface (SHI) Timing 52 timing interrupt 7 mode select 7 Reset 7 Stop 7 TQFP 1 pin ...
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Freescale Semiconductor DSP56362 Technical Data, Rev. 4 Index-5 ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. All rights reserved. ...