AD1991ASV Analog Devices Inc, AD1991ASV Datasheet - Page 7

• Manufacturer Part Number: AD1991ASV
• Description: IC AMP AUDIO PWR 40W STER 52TQFP
• Manufacturer: Analog Devices Inc
• Type: Class Dr

Specifications of AD1991ASV

• Rohs Status: RoHS non-compliant
• Output Type: 2-Channel (Stereo) or 4-Channel (Quad)
• Max Output Power X Channels @ Load: 40W x 1 @ 4 Ohm; 20W x 2 @ 8 Ohm
• Voltage - Supply: 6.5 V ~ 22.5 V
• Features: Depop, Mute, Short-Circuit and Thermal Protection
• Mounting Type: Surface Mount
• Package / Case: 52-TQFP, 52-VQFP

EDGE SPEED AND NONOVERLAP SETTINGS
The AD1991 allows the user to select from one of eight different
edge speeds and from one of eight different nonoverlap times.
This allows the user to make a trade-off between distortion,
efficiency, overshooting at the outputs, and EMI. The following
sections describe the method used to program the settings.
Edge Speed
The edge speed is set by using the three pins, ERR3, ERR2, and
INB, when RST/PDN is low. The levels on the three pins are
latched by the rising edge of RST/PDN. The latched value deter-
mines the edge speed thereafter, until RST/PDN is brought low.
Table VI shows the appropriate logic levels for the corresponding
edge speeds. Note that INB is internally inverted, resulting in
the nonmonotonic sequence in Table VI.
REV. 0
Figure 4. Functional Block Diagram (1-Channel Mode)
RST/PDN
INPUT
MUTE
CLK
INA
INB
INC
IND
AGND DGND
AV
SWITCH CONTROL
4
DD
LEVEL SHIFTER
n
THERMAL PROTECTION
SHORT-CIRCUIT PROTECTION
MUTE CONTROL
DV
AND
DD
CONTROL
TEST
H-BRIDGE
2
A1
A2
B1
B2
C1
C2
D1
D2
PGND
PV
14
DD
6
OUTA
OUTB
OUTC
OUTD
3
3
3
3
CURRENT OVERLOAD
THERMAL SHUTDOWN
THERMAL WARNING
DATA LOSS
–7–
Nonoverlap Time
The nonoverlap time is set by using the three pins, ERR1, ERR0,
and IND, when RST/PDN is low. The levels on the three pins
are latched by the rising edge of RST/PDN. The latched value
determines the nonoverlap time thereafter, until RST/PDN is
brought low. Table VII shows the appropriate logic levels for
the corresponding nonoverlap times. Note that IND is internally
inverted, resulting in the nonmonotonic sequence in Table VII.
Note that ERR3, ERR2, ERR1, and ERR0 are driven outputs
under normal operation and, therefore, should never be tied to a
dc voltage. The part contains internal 300 kΩ pull-up resistors
to pull these pins high during reset. If it is desired to set them
low to achieve a particular edge speed or nonoverlap time, this
should be done by pulling them low through resistors between
10 kΩ and 50 kΩ.
ERR1
0
0
0
0
1
1
1
1
ERR3
0
0
0
0
1
1
1
1
ERR0
0
0
1
1
0
0
1
1
Table VII. Nonoverlap Time Settings
Table VI. Edge Speed Settings
ERR2
0
0
1
1
0
0
1
1
IND
1
0
1
0
1
0
1
0
INB
1
0
1
0
1
0
1
0
Nonoverlap Time
1 (Shortest Nonoverlap Time)
2
3
4
5
6
7
8 (Longest Nonoverlap Time)
Edge Speed
1 (Slowest Edge Speed)
2
3
4
5
6
7
8 (Fastest Edge Speed)
AD1991