CXD2931R Sony, CXD2931R Datasheet

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CXD2931R

Manufacturer Part Number
CXD2931R
Description
1 chip GPS LSI
Manufacturer
Sony
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
CXD2931R-8
Manufacturer:
SONY/索尼
Quantity:
20 000
Description
(Global Positioning System) satellite-based position
measurement system.
ROM, RAM, UART, timer, and others.
enables the configuration of a 2-chip system capable of
measuring its position anywhere on the globe.
Features
• 16-channel GPS receiver capable of simultaneously
• Supports differential GPS
• All-in-view measurement
• 2-satellite measurement
• Timer supporting GPS time
• High performance 32-bit RISC CPU
• 256K-byte program ROM
• 36K-byte RAM
• 3-channel UART
• 23-bit general-purpose I/O port capable of defining
Structure
The CXD2931R is a dedicated LSI for the GPS
This LSI contains a 32-bit RISC CPU, 2M-bit MASK
This LSI, used together with the RF LSI (CXA1951AQ),
receiving 16 satellites
— Comforms to RTCM SC-104 Ver. 2.1
— Supports DARC
— Baud rate generator
— Supports 1.2K, 2.4K, 4.8K, 9.6K, 19.2K and
— Supports 1/2/4-byte buffer mode
input/output independently for each bit
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
1 chip GPS LSI
38.4K baud
– 1 –
Absolute Maximum Ratings
• Supply voltage
• Input voltage
• Output voltage
• Operating temperature Topr
• Storage temperature
Recommended Operating Conditions
• Supply voltage
• Operating temperature Topr
Input/Output Pin Capacitance
• Input capacitance
• Output capacitance
• I/O capacitance
CXD2931R
144 pin LQFP (Plastic)
V
V
V
V
C
C
C
Tstg
DD
I
O
DD
IN
OUT
I/O
V
V
SS
SS
V
– 0.5 to V
– 0.5 to V
SS
–50 to +150
–40 to +85
–40 to +85
11 (Max.)
11 (Max.)
3.0 to 3.6
9 (Max.)
– 0.5 to 4.6
DD
DD
E99702-PS
+ 0.5 V
+ 0.5 V
pF
pF
pF
°C
°C
°C
V
V

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CXD2931R Summary of contents

Page 1

... GPS LSI Description The CXD2931R is a dedicated LSI for the GPS (Global Positioning System) satellite-based position measurement system. This LSI contains a 32-bit RISC CPU, 2M-bit MASK ROM, RAM, UART, timer, and others. This LSI, used together with the RF LSI (CXA1951AQ), enables the configuration of a 2-chip system capable of measuring its position anywhere on the globe ...

Page 2

... All-in-view measurement • 2-satellite measurement • High performance 32-bit RISC CPU The noted values may be exceeded depending on the operating environment and other conditions. GPS receiver system diagram using the CXD2931R 1575.42MHz (L1 band, CA code) –130dBm or less 35 to 60s 6 to 20s Less than 5 minutes: < ...

Page 3

... PMI IODBK HOLDA SINT/PORT (22) TXD0 to 2 RXD0 to 2 BIU 32bit RISC 256K Byte ROM 36K Byte SRAM UART (Baud Rate Generator) 3 TIMER 3 16ch GPS DSP – 3 – CXD2931R TEST0, 1 ICST0, 1 XROMW CLKS CLKI CLKO CLKOUT TCXOS EXRS PWRST ...

Page 4

... – 4 – CXD2931R ...

Page 5

... Connect to main power supply. Leave open during backup — GND SS 30 CLKI I CPU clock oscillation circuit. 31 CLKO O 32 CLKS I CPU clock select signal. (Low: TCXO, High: CLKI) 33 CLKOUT O CPU clock output — Power supply RUN O Signal indicating CPU operating status. Description – 5 – CXD2931R ...

Page 6

... Address signal for external expansion memory. 59 IADR16 I/O 60 IADR17 I/O 61 IADR18 I/O (MSB) 62 IB0 I/O (LSB) Data bus I/O for external expansion memory — Power supply IB1 I/O 65 IB2 I/O 66 IB3 I/O Data bus I/O for external expansion memory. 67 IB4 I/O 68 IB5 I/O 69 IB6 I — GND SS Description – 6 – CXD2931R ...

Page 7

... DADR9 I — Power supply DADR10 I/O 97 DADR11 I/O 98 DADR12 I/O Address signal for external expansion data memory. 99 DADR13 I/O 100 DADR14 I/O 101 DADR15 I/O (MSB) 102 DB0 I/O (LSB) Data bus I/O for external expansion data memory. 103 DB1 I/O 104 V — GND SS Description – 7 – CXD2931R ...

Page 8

... General-purpose I/O port. 126 PORT9 I/O 127 PORT8 I/O 128 PORT7 I/O 129 V — Power supply. DD 130 PORT6 I/O 131 PORT5 I/O 132 PORT4 I/O 133 PORT3 I/O General-purpose I/O port. 134 PORT2 I/O 135 PORT1 I/O 136 PORT0 I/O 137 V — GND SS 138 TXD2 O UART transmission data output (channel 2) Description – 8 – CXD2931R ...

Page 9

... UART reception data input (channel 2) 140 TXD1 O UART transmission data output (channel 1) 141 RXD1 I UART reception data input (channel 1) 142 TXD0 O UART transmission data output (channel 0) 143 RXD0 I UART reception data input (channel 0) 144 V — Power supply. DD Description – 9 – CXD2931R ...

Page 10

... 8.0mA V ( –12.0mA V (3) V – 0 12.0mA V ( 3.0V DD ISTB 18.414MHz I DD – 10 – CXD2931R = 3.0 to 3.6V, Topr = –40 to +85°C) DD Applicable Typ. Max. Unit pins µ ...

Page 11

... Typ. Typ. – 3ppm 18.414 0. 220pF 13 10M 220pF 14 32.768kHz 100ppm 0. 15pF 30 1M 15pF 31 X'tal – 11 – CXD2931R Max. Unit Typ. + 3ppm MHz 3.0 to 3.6V, Topr = –40 to +85° 3.0 to 3.6V, Topr = –40 to +85°C) ...

Page 12

... Tri-state outputs ICS0, ICS1, IADR[18:1], IRD, IWR, DRD, DWR, XCS0 Bidirectional (Input) SINT, IB[15:0], DCS0 to 5, DADR[15:0], DB[7:0], PORT[15:0] (Outut) Inputs RXD0 to 2, ITCXO, IF0 to 2, HOLD, NMI, PMI 10 clocks 100ms or more Fixed low Fixed low Hi-Z Fixed low Hi-Z Fixed low – 12 – CXD2931R ...

Page 13

... CXD2931R Initialization CXD2931R initialization is started by setting the reset input signal EXRS (Pin 27) to low level. The timing should satisfy the conditions noted below. 1. During power-on (power-on reset Power supply, PWRST V [V] (Pin 28) DD GND The PWRST (Pin 28) signal should rise simultaneously with the power supply. The EXRS (Pin 27) signal should rise 100ms or more after the power supply and the PWRST signal have risen ...

Page 14

... Read data setup time (h) Read data hold time • External Command Fetch Timing (XROMW = 1) CLKOUT IADR ICS0, ICS1 IRD IB (a) (b) (e) Min. — — (16) – 14 – CXD2931R (d) (f) (g) (h) (16) Typ. Max. Unit 100 — ns — — — — — ...

Page 15

... Min. Typ. — 100 — — 2 — 2 — 1 — 1 — 23 — 0 — 0 — 0 — — — 5 — The load capacitance = 30pF. – 15 – CXD2931R Max. Unit — — ns — — ns ...

Page 16

... Read (word access/XROMW = 0) CLKOUT IADR ICS0, ICS1 IRD IB (4) Write (word access/XROMW = 0) CLKOUT IADR ICS0, ICS1 IWR IB H (16) L (16) L (16) H (16) – 16 – CXD2931R ...

Page 17

... Read (half-word access/XROMW = 1) CLKOUT IADR ICS0, ICS1 IRD IB (2) Write (half-word access/XROMW = 1) CLKOUT IADR ICS0, ICS1 IWR IB (3) Read (word access/XROMW = 1) CLKOUT IADR ICS0, ICS1 IRD IB (4) Write (word access/XROMW = 1) CLKOUT IADR ICS0, ICS1 IWR IB (16) (16) H (16) L (16) L (16) H (16) – 17 – CXD2931R ...

Page 18

... Write data established time (l) Write data hold time (a) (b) (c) (e) (g) (a) (b) (c) (i) (k) Min. — — — 5 – 18 – CXD2931R (d) (f) (h) (8) (d) (j) (l) (8) Typ. Max. Unit 100 — ns — — — — — ...

Page 19

... XCS0, DCS0 to 5 DWR DB (5) Read (word access/no data wait) CLKOUT DADR XCS0, DCS0 to 5 DRD DB (6) Write (word access/no data wait) CLKOUT DADR XCS0, DCS0 to 5 DWR DB H (8) H (8) L (8) HH (8) HL (8) LH (8) LL (8) LH (8) HL (8) – 19 – CXD2931R H (8) LL (8) HH (8) ...

Page 20

... DB (2) Write (byte access/data wait = 1) CLKOUT DADR XCS0, DCS0 to 5 DWR DB (3) Read (half-word access/data wait = 1) CLKOUT DADR XCS0, DCS0 to 5 DRD DB (4) Write (half-word access/data wait = 1) CLKOUT DADR XCS0, DCS0 to 5 DWR DB (8) (8) H (8) L (8) L (8) H (8) – 20 – CXD2931R ...

Page 21

... External Data Access Timing (XCS0, DCS0 to 5/data wait = 2) (1) Read (byte access/data wait = 2) CLKOUT DADR XCS0, DCS0 to 5 DRD DB (2) Write (byte access/data wait = 2) CLKOUT DADR XCS0, DCS0 to 5 DWR DB HH (8) HL (8) LH (8) LL (8) LH (8) HL (8) (8) (8) – 21 – CXD2931R LL (8) HH (8) ...

Page 22

... XCS0, DCS0 to 5 DWR DB (5) Read (word access/data wait = 2) CLKOUT DADR XCS0, DCS0 to 5 DRD HH (16) DB (6) Write (word access/data wait = 2) CLKOUT DADR XCS0, DCS0 to 5 DWR DB LL (16) H (8) L (8) L (8) H (8) HL (16) LH (16) LH (16) HL (16) HH (16) – 22 – CXD2931R LL (16) ...

Page 23

... LQFP (PLASTIC) 22.0 ± 0.2 20.0 ± 0.22 ± 0. 0.20 ± 0.03 (0.2) DETAIL B : SOLDER DETAIL B : PALLADIUM PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LQFP-144P-L01 LEAD MATERIAL LQFP144-P-2020 PACKAGE MASS – 23 – CXD2931R 1.7 MAX 1.4 ± EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 1.3 g ...

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