MT90221AL Mitel, MT90221AL Datasheet
MT90221AL
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MT90221AL Summary of contents
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... Processor I/F Figure 1 - MT90221 Block Diagram with Built-in IMA functions for 4 IMA Groups over links Quad IMA/UNI PHY Device DS5065 Ordering Information MT90221AL - +85 C • Provides Header Error Control (HEC) verification and generation, error detection, Filler cell filtering (IMA mode) and Idle/ Unassigned cell fi ...
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MT90221 Applications • Cost effective single chip solution to implement IMA and UNI links over all public or private UNI, NNI and B-ICI applications • ATM Edge switch IMA and UNI Line Card Design • Can ...
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Device Architecture ....................................................................................................................................... 8 1.1 Software Functions..................................................................................................................................... 8 1.1.1 Link State Machines........................................................................................................................... 8 1.1.2 IMA Group State Machines ................................................................................................................ 8 1.1.3 Link Addition, Removal or Restoration............................................................................................... 8 1.1.4 Interrupt.............................................................................................................................................. 8 1.1.5 Signaling and Rate Adjustment.......................................................................................................... 8 1.1.6 Performance Monitoring..................................................................................................................... ...
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MT90221 3.3.7 Rate Recovery ................................................................................................................................. 19 3.3.8 Cell Buffer/RAM Controller............................................................................................................... 19 3.3.9 Cell Sequence Recovery ................................................................................................................. 19 3.3.10 Delay Between Links ....................................................................................................................... 20 3.3.10.1 RX Recombiner Delay Value .................................................................................................... 20 3.3.10.2 RX Maximum Operational Delay Value..................................................................................... 20 3.3.10.3 Link Out ...
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Support Blocks............................................................................................................................................. 33 6.1 Counter Block........................................................................................................................................... 33 6.1.1 UTOPIA Input I/F counters............................................................................................................... 33 6.1.2 Transmit PCM I/F Counters ............................................................................................................. 33 6.1.3 Receive PCM I/F Counters .............................................................................................................. 33 6.1.4 Access to the Counters .................................................................................................................... 33 6.2 Interrupt Block .......................................................................................................................................... 34 ...
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MT90221 Packaging Information........................................................................................................................................ 98 List of Changes.................................................................................................................................................. 100 List of Abbreviations and Acronyms............................................................................................................... 102 ATM Glossary .................................................................................................................................................... 102 iv Table of Contents ...
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Figure 2 - Pin Connections ..................................................................................................................................... 3 Figure 3 - Functional Block Diagram -Transmitter in IMA Mode........................................................................... 10 Figure 4 - Functional Block Diagram of the Transmitter in UNI Mode ................................................................... 15 Figure 5 - Cell Delineation State Diagram ............................................................................................................ ...
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MT90221 Pin Description ....................................................................................................................................................... 4 Pinout Summary ..................................................................................................................................................... 7 Table 1 - IDCR Integration Register Value ........................................................................................................... 12 Table 2 - ICP Cell Description .............................................................................................................................. 13 Table 3 - Cell Acquisition Time............................................................................................................................. 16 Table 4 - Differential Delay for Various ...
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Table OIF Status Register...................................................................................................................... 53 Table OIF Counter Clear Command Register ........................................................................................ 54 Table Load Values/Link Select Register ................................................................................................ 54 Table Link IMA ID Registers................................................................................................................... 54 Table 50 ...
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MT90221 Table 93 - Select Counter Register ..................................................................................................................... 71 Table 94 - Counter Transfer Command Register ................................................................................................. 72 Table 95 - IRQ Master Status Register ................................................................................................................ 72 Table 96 - IRQ Master Enable Register .............................................................................................................. 73 Table 97 - IRQ ...
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VSS 158 REFCK_3 REFCK_2 REFCK_1 160 REFCK_0 162 SR_A_18 SR_A_17 SR_A_16 164 SR_A_15 SR_A_14 166 VDD 168 VSS SR_A_13 SR_A_12 170 SR_A_11 SR_A_10 172 VDD 174 VSS SR_A_9 SR_A_8 176 SR_A_7 178 SR_A_6 ...
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MT90221 Pin Description (continued) Pin # Name I/O 32 TxClk I UTOPIA Transmit Clock. Transfer clock from the ATM Layer device to the MT90221 which synchronizes data transfers on TxData[1:0]. This signal is the clock of the incoming data. Data ...
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Pin Description (continued) Pin # Name I/O 162, 163, sr_a O Static Memory Address Bus. The signal is used to select an entry in the external 164, 165, [18:0] static memory. 166, 169, 170, 171, 172, 175, 176, 177, 178, ...
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MT90221 Pin Description (continued) Pin # Name I/O 101, 103, TXCKi/o I/O PCM Interface Transmit Clock 3-0. This pin is an input for PCM Modes and 111, 113 [3: output for Interface Modes ...
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Pin Description (continued) Pin # Name I/O 81, 88, 90 Connect. Can be left unconnected. 97, 120, 122, 129, 131 74 Clk I System Clock (25 MHz nominal). In the MT90221, this clock is used for all internal ...
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MT90221 1.0 Device Architecture The MT90221, supported by software, implements the ATM Forum Inverse Asynchronous Transfer Mode (IMA) Specification. This approach minimizes the impact of any changes that might occur in the specification. Actions are implemented by the MT90221 and ...
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It also provides the content for received ICP cells that contain some changes. The external framers provide the low level status of the link. The software integrates and responds to the various events. 1.2 Hardware Functions The ...
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MT90221 ATM In UTOPIA L2 Interface Cell_In_Control from IDCR Generator Micro I/F Figure 3 - Functional Block Diagram -Transmitter in IMA Mode Section 5 describes the UTOPIA Interface in more detail. 2.2 The ATM Transmission Convergence The Transmit Convergence (TC) ...
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Filler Cell used in IMA mode • one Idle Cell used in UNI mode The remaining 58 cells can be assigned to any of the 12 TX FIFOs. The TX FIFOs are divided UTOPIA ...
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MT90221 The clocking mode and reference link are fixed once an IMA Group is setup and should remain unchanged so long as that group is operational. The reference link should not change unless problems are reported with the link. 2.4.4 ...
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Byte Description 1-5 ICP Cell Header 6 OAM label 7 Cell ID, Link ID 8 IMA Frame Sequence 9 ICP Cell Offset 10 Link Stuff Indication 11 Status Change Indic. 12 IMA ID 13 Group Status and Control 14 Sync. ...
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MT90221 The SCCI field is incremented by one for each transfer command performed change in at least one byte of the ICP cell. 2.4.8 IMA Frame Programmable Interrupt An optional interrupt is provided at the end of an IMA frame ...
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ATM In Cell_In_Control Output Controller and Cell Distribution Figure 4 - Functional Block Diagram of the Transmitter in UNI Mode ATM cells received from the ATM port are placed UTOPIA FIFO, waiting to be transmitted. If the ...
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MT90221 Cell Accepted DELTA Consecutive Correct HCS’s (PRESYNC State) Correction Only one set of values is defined for the four Cell Delineation state machines. The status of the CD state machine for each link is available in bits 0 and ...
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RXCK Cell RXSYNC S/P Delineation DSTi [0] RXCK Cell RXSYNC S/P Delineation DSTi [3] Figure 7 - The MT90221 Receiver Circuit in IMA Mode 3.3.1 ICP Cell Processor In IMA mode, the transmitter inserts special ICP cells in the various ...
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MT90221 3.3.1.2 Link Information All required verification and information is extracted from the ICP received cells. The IMA ID, Link ID (LID), Reference Link Number, ICP Cell Offset and Frame Length can be read and validated before enabling an IMA ...
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The RX ICP Cell Level FIFO register is used to read the level of any of the 4 RX ICP Cell buffers. A ’0’ in this register ...
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MT90221 corresponding to the lowest link ID (LID) of the IMA Group and placed in the RX UTOPIA FIFO. After a complete cell read, a read pointer is set to the buffer corresponding to the next LID. At the following ...
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A delay is negative when the two most significant bits are set to "1". The value reported is with respect to the read pointer and represents the minimum number of cells that has to be added to the ...
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MT90221 3.3.11 RX IMA Group Start-Up A quick initialization sequence for the RX IMA Group could be as follows (default values can be used for some registers) (Note: The startup procedure below is given indicating the most important steps. A ...
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RXCK RXSYNC S/P Delineation DSTi RXCK RXSYNC S/P Delineation DSTi RXCK RXSYNC S/P Delineation DSTi RXCK RXSYNC S/P Delineation DSTi 4.0 Description of the PCM Interface To provide support for the IMA Asymmetrical mode, the Transmit PCM blocks are independent ...
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MT90221 PCM Major Modes TX PCM Control Registers 1 & 2 Reg 1 bit 6 Mode 1 0 Mode 2 0 Mode 3 1 Mode 4 1 Mode 5 0 Mode 6 0 Mode 7 1 Mode 8 1 PCM ...
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... The MITEL ST-BUS clock value is 4.096 MHz. The frame pulse is 8 kHz and should be as defined in Figure 9 or Figure 10 (see MITEL Application Note MSAN-126). In the PCM Mode 6, the TXCK and TXSYNC pins are defined as outputs. The source for the TXCK is ...
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... ST-BUS timeslots. Channels 0 and 16 are used for framing and signaling information. See Figure 11 and Table 10 PCM Modes 4 and 8, the MITEL ST-BUS clock value is 4.096 MHz. The frame pulse is 8 kHz and should be as defined in Figure 11. In PCM Mode 4, the TXCK and TXSYNC pins are defi ...
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ST-BUS Bit Cells Channel 31 bit 0 (DSTx0-3) Serial Bit Bit Cell Stream TXSYNC RXSYNC TXCK RXCK ST-BUS Channel 15 bit 0 Bit Cells (DSTx0-3) Serial Bit Bit Cell Stream TXSYNC RXSYNC TXCK RXCK Figure 11 - PCM Mode 4 ...
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MT90221 T1 Frame Bit Cells at DSTx0-3 Serial Bit Stream TXSYNC TXCK RXSYNC RXCK Figure 12 - Mode 1 and 5: Generic PCM Interface for T1 or spaced) are supported. The TXCLK and RXCLK are 2.048 MHz signal and the ...
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ST-BUS Channel 31 bit 0 Channel 0 bit 7 Bit Cells (DSTx0-3) Serial Bit Bit Cell High Impedance Stream TXSYNC TXCK RXSYNC RXCK ST-BUS Channel 15 bit 0 Channel 16 bit 7 Bit Cells at DSTx0-3 Serial Bit Bit Cell ...
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MT90221 period and position of the TXSYNC is verified for each transmit block independently. A status bit (1 per link) in the TX Sync Status register is set if the synchronization pulse occurs at an unexpected time in the frame. ...
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PHY port is not to be used). The size of the TX Link FIFO is defined on a per group using the TX IMA Control registers. The device will ...
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MT90221 5.5 UTOPIA Operation in UNI Mode In UNI Mode, each Utopia port inside an MT90221 corresponds to a physical line eight PHY ports can be supported by one MT90221 eight MT90221 can ...
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ATM Layer Device Figure 17 - ATM Mixed-Mode Interface to One MT90221 6.0 Support Blocks 6.1 Counter Block The MT90221 includes 64 24-bit counters to provide statistical information on the device’s operation. All the counters are cleared by a hardware ...
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MT90221 bit of the Counter Transfer Command register. The value ’0x001010’ enables the counter IRQ and ’xxx00010’ disables (masks) it. 6.2 Interrupt Block The MT90221 can generate interrupts from many sources. All interrupt sources can be enabled or disabled. Write ...
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IRQ Link Status registers) for each link: • Bit 5 latched: reports that an ICP Cell with changes was received PCM link. • ...
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MT90221 6.2.3 IRQ Link UNI Overflow and IRQ UTOPIA Input UNI Overflow Status Registers The IRQ Link UNI Overflow and the IRQ UTOPIA Input UNI Overflow Status registers report the overflow condition from any of the counters associated with the ...
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Direct Access Direct access registers can be written or read directly by the microprocessor, without having to use otherregisters. Upon a write access to the MT90221 internal registers, the data is stored in an internal latch and transferred to ...
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MT90221 7.0 Register Descriptions Reset Address Access Value (Hex) Type (Hex) 000 - 003 D 00 008 - 00B D 00 00C D 00 00D D 00 00E D 00 040 - 043 D 00 048 - 04B D 00 ...
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Reset Address Access Value (Hex) Type (Hex) 119 D 00 11A D 00 11B D 00 11C D 00 11D D 20 11E D 00 1C0 D 00 1C6 D 00 1C7 D 00 1C3 S 00 292 D 08 ...
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MT90221 Reset Address Access Value (Hex) Type (Hex) 09C D 00 09D D 10 214 S 00 215 S 00 216 S 00 217 S 00 207 S 00 232 D 00 218 D 00 222 - 225 D 00 ...
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Utopia Register Description Tables describe the UTOPIA registers. Address (Hex): 000 - 003 Direct access 1 register per link in UNI mode. The TxClk signal must be active for correct register operation. Reset Value (Hex): 00 ...
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MT90221 Address (Hex): 00D Direct access 1 register to enable the IMA Groups. The TxClk signal must be active for correct register operation Reset Value (Hex): 00 Bit # Type 7-4 R/W Reserved. Write all 0’ R/W Enable ...
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Address (Hex): 048 - 04B Direct access 1 reg. per IMA Group.link. The RxClk signal must be active for correct register operation Reset Value (Hex): 00 Bit # Type 7:5 R Unused. Read all 0’s. 4:0 R/W UTOPIA PHY Address ...
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MT90221 Address (Hex): 205 Direct access 1 register to enable interrupts from IMA Groups. The RxClk signal must be active for correct register operation Reset Value (Hex): 00 Bit # Type 7-4 R Unused. Read all 0’s. 3 R/W When ...
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TX Registers Description Tables describe the Transmit registers. Address (Hex): 140 Direct access Used for initialization of the TX Cell RAM (Filler, Idle Cells etc.) Reset Value (Bin): 1X000000 Bit # Type 7 R Goes to ...
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MT90221 Address (Hex): 14C Direct access Reset Value (Hex): 33 Bit # Type 7:0 R/W Reserved. Write 0 for normal operation. Table FIFO Length Definition Register 3 Address (Hex): 14D Direct access Reset Value (Hex): 33 Bit ...
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Address (Hex): 0C0 - 0C3 Direct access 1 register per TX IMA Group Reset Value (Hex): 58 Bit # Type 7 R/W Reserved, write 0 for normal operation. 6-5 R/W Value of M. These 2 bits specifies the value of ...
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MT90221 Address (Hex): 200 - 203 Direct access 1 register per TX IMA Group Reset Value (Hex): 05 Bit # Type 7:4 R Unused. Read all 0’s. 3-0 R/W Defines the integration period for an IMA Group: 1111: Reserved. Do ...
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Address (Hex): 0D4- 0D7 Direct access 1 register per IMA Group Reset Value (Hex): 29 Bit # Type 7 R/W 0 for Stuff Indication 1 frame before Stuff event. 1 for Stuff Indication 4 frames before stuff event. 6:3 R/W ...
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MT90221 7.3 TX ICP Register Description Tables describe the TX ICP registers. Address (Hex): 148 Direct access Controls the transfer of TX ICP cells and frame pulse indication Reset Value (Hex): 0F Bit # Type 7 R/W ...
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Address (Hex): 300, 340, 380, 3C0 for IMA Group and 3 respectively Direct access Access these locations directly then use transfer command to copy to internal memory Reset Value (Hex): These registers need to be initialized for ...
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MT90221 7.4 RX Registers Description Tables describe the Receive registers. Address (Hex): 100 -103 Direct access 1 register per link Reset Value (Hex): 0C Bit # Type 7 R/W A Value of 0 select to count the ...
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Address (Hex): 10A Direct access 1 reg. for all 4 IMA Frame state machines Reset Value (Hex): 91 Bit # Type 7:6 R/W ALPHA parameter value for the IMA Frame Delineation.state machine. The number of consecutive invalid ICP cells to ...
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MT90221 Address (Hex): 116 Direct access 1 register for the 4 RX links Reset Value (Hex): 00 Bit # Type 7-4 R/W Reserved. Write 0 for normal operation. 3 R/W Write clear the OIF counter for physical ...
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Address (Hex): 119 Direct access The value is updated on completion of the write action in the RX Load Values register Reset Value (Hex): 00 Bit # Type 7:0 R Defines the ICP cell offset of the link selected in ...
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MT90221 Address (Hex): 11D Direct access The value is updated on completion of the write action in the RX Load Values register Reset Value (Hex): 20 Bit # Type 7 R LIF state of the link selected in the RX ...
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RX ICP Cell Registers Description Tables describe the RX ICP registers Address (Hex): 1C0 Direct access Access for RX link 3-0 Reset Value (Hex): 00 Bit # Type 7:6 R/W These 2 bits select the type ...
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MT90221 Address (Hex): 1C6 Direct access 1 reg. for all 4 RX link FIFO Reset Value (Hex): 00 Bit # Type 7-4 R/W Reserved. Write 0 for normal operation value of 1 will increment the position of ...
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External SRAM Register Description Tables describe the External SRAM registers. Address (Hex): 292 Direct access Defines the external SRAM configuration Reset Value (Hex): 08 Bit # Type 7 R/W Write reset the receiver. ...
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MT90221 Address (Hex): 290 Synchronized access Set address before the transfer is initiated with the RX External SRAM Control register Reset Value (Hex): 00 Bit # Type 7:0 R/W RX External SRAM Read/Write Address bit 15:8. Table ...
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RX Delay Registers Description Tables describe the RX Delay registers. Address (Hex): 280 Synchronized access Reset Value (Bin): 1X000000 Bit # Type 7 R Upon a write to this register, the bit will ...
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MT90221 Address (Hex): 29D Direct access Used to initiate an update of the RX Delay registers based on the link and delay value to read Reset Value (Hex): 00 Bit # Type 7:6 R/W 00: normal delay, 01: read pointer, ...
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Address (Hex): 286 Direct access This register contains the link number associated with the RX Delay value Register. Reset Value (Hex): 00 Bit # Type 7:2 R/W Reserved, write 000100 to these bits for normal operation. 1:0 R/W Number of ...
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MT90221 7.8 RX Recombiner Registers Description Tables describe the RX Recombiner registers. Address (Hex): 180 - 183 Direct access 1 register per RX link Reset Value (Hex): 00 Bit # Type 7:3 R Unused. Read all 0’s. ...
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Address (Hex): 188 - 18B Direct access 1 register per IMA Group Reset Value (Hex): 00 Bit # Type 7 R Unused. Read 0. 6:4 R Reserved. 3 R/W When set enables the automatic selection of the ...
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MT90221 7.9 TX/RX and PLL Control Registers Description Tables describe the TX/RX and PLL Control registers. Address (Hex): 080 - 083 Direct access 1 reg. per TX link Reset Value (Hex): 00 Bit # Type 7:5 R ...
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Address (Hex): 088 - 08B Direct access 1 reg. per TX link Reset Value (Hex): 00 Bit # Type 2 R/W T1 Signaling channel. A value of 1 disables the use of the channel 24 and reserves it for signaling. ...
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MT90221 Address (Hex): 098 Direct access Reset Value (Hex): 00 Bit # Type 7 R/W Writing a 1 forces the deselecting of the selected clock when it failed. 6:5 R/W Reserved. Set to 0 for normal operation. 4:3 R/W These ...
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Address (Hex): 09A Direct access 1 reg. for all 4 RX links Reset Value (Hex): 00 Bit # Type 7:4 R/W Reserved. Write 0 for normal operation. 3 R/W PCM RX Sync signal faulty on link 3. Cleared by writing ...
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MT90221 7.10 Counter Registers Description Tables describe the Counter registers Address (Hex): 214 Synchronized access The value in this register is used for internal access to the counter when the transfer command is issued Reset Value (Hex): ...
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Address (Hex): 217 Synchronized access The value in this register is used for internal access to the counter when the transfer command is issued Reset Value (Hex): 00 Bit # Type 7:4 R/W The valid bit combinations are: 1011: UTOPIA ...
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MT90221 7.11 Interrupt Registers Description Tables 94 to 102 describe the Interrupt registers. Address (Hex): 232 Direct access Reset Value (Hex): 00 Bit # Type 7:4 R Reserved. 3:0 R Each bit represents a link. A ’1’ means that the ...
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Address (Hex): 222 - 225 Direct access 1 Status register per link Reset Value (Hex): 00 Bit # Type ’1’ in this bit means that at least one of the IRQ sources from the IMA Group ...
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MT90221 Address (Hex): 204 Direct access Reset Value (Hex): 00 Bit # Type 7:4 R Unused. Should read 0’s. 3:0 R/W Each bit set to ’1’ will enable the generation of the interrupt when the corresponding bit in the IRQ ...
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Address (Hex): 22A - 22D Direct access 1 register per link. The RxClk and TxClk signals must be active for correct register operation Reset Value (Hex): 00 Bit # Type 7 R/W This bit is set when the TX PCM ...
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MT90221 7.12 Miscellaneous Registers Description Tables 103 to 105 describe the General Status and Test Register. Address (Hex): 206 Direct access Reset Value (Hex): 10 Bit # Type 7:4 R Device Revision Number: reads 0001. 3 R/W Set when the ...
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... MHz (T1) or 2.048 MHz (E1) transmit clock. Figure 20 provides an example of PCM Modes 2 and IMA implementation based on the MITEL MT90221 and the MITEL MT9074 framers. This configuration supports CTC mode. Although the MT9074 use the ST-Bus format but it is not configured as a common backplane. ...
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... ST-BUS I/FCLOCKS Dejittered TX CLK to Framers (1.544 or 2.048 MHz) MT9042 Functions Existing Mitel T1/E1 Legacy Trunks Framers at 1 Mbps Existing Mitel T1/E1 Legacy Trunks Framers at 1 Mbps Existing Mitel T1/E1 Legacy Trunks Framers at 1 Mbps Receive Clock (1.544 or 2.048 MHz kHz References External Source ...
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DSTi[0] RXCK[0] RXSYNC[0] TXSYNC[0] TXCK[0] DSTo[0] MT90221 DEVICE UTOPIA LEVEL 2 BUS DSTi[3] RXCK[3] RXSYNC[3] TXSYNC[3] TXCK[3] DSTo[3] Note: The MT9074 #1 is configured in Line Sync. mode and all other MT9074s are configured in Bus Master mode. Figure 20 ...
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... UTOPIA MT90221 LEVEL 2 DEVICE BUS DSTi[3] RXCK[3] RXSYNC[3] TXSYNC[3] TXCK[3] DSTo[3] Note: All MT9074 are configured in Line Sync. mode (Using Mitel MT9074 T1/E1 Single Chip Transceivers) 80 MT9074 DSTo C4b F0b DSTi MT9074 DSTo C4b F0b DSTi Figure 21 - PCM MODE 2 AND 4: ITC Mode ...
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DSTo[0] MT90221 DSTi[0] TXCKi[0] TXSYNCo[0] RXCKi[0] UTOPIA RXSYNC[0] BUS ATM LAYER BUS PLLREF0-1 DSTo[3] DSTi[3] TXCKi[3] TXSYNCo[3] RXCKi[3] REFCK0-3 RXSYNCi[3] Dejittered TX CLK (1.544 or 2.048 MHz) MT9042 Transmit Clock Dejittering Function Figure 22 - PCM MODE 1 and 3: ...
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MT90221 8.2 Optimum Usage of 1 Bank of Memory with a 4 Port Device Due to the addressing mode of the MT90221, only half of the memory locations are utilized when operating in IMA mode. This is mainly due to ...
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AC/DC Characteristics Absolute Maximum Conditions* Parameter 1 Supply Voltage 2 Voltage at Digital Inputs 3 Current at Digital Inputs 4 Storage Temperature * Exceeding these values may cause permanent damage. Functional Operation under these conditions is not implied. Note: ...
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MT90221 DC Electrical Characteristics* - Characteristics Sym 13 Output Low Current I 14 Output Pin C Capacitance 15 High Impedance I Leakage * DC Electrical Characteristics are over recommended temperature and supply voltage ‡ Typical figures are ...
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PCM Bit Bit Cell Stream TXSYNC 0-3/ RXSYNC 0-3 t TXCK 0-3/ RXCK 0-3 DSTi0-3 t SOD DSTo0 Figure 25 - ST-BUS Timing Diagram Bit Cell Bit Cell t FPH FPS SIH t ...
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MT90221 AC Electrical Characteristics Characteristic 1 TXCK/RXCK Clock period for T1, 1.544 MHz mode for E1, 2.048 MHz mode 2 TXCK/RXCK Clock Width High or Low for T1, 1.544 MHz mode for E1, 2.048 MHz mode 3 Frame Pulse Setup ...
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T1 PCM Channel 24 Stream xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x LSB Bit 1.544MHz T1/E1 PCM Stream Channel 31 LSB Bit 2.048MHz RXSYNC0-3 RXCK0-3 xxxxxxxx xxxxxxxx DSTi 0-3 xxxxxxxx xxxxxxxx TXSYNC0-3 INPUT t TXSYNC0-3 FPD TXCK0-3 t SOD DSTo 0-3 ...
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MT90221 AC Electrical Characteristics - Utopia Interface Transmit Timing Signal name TxClk TxData[7:0], TxSOC, TxEnb*, TxAddr[4:0] TxClav[0] AC Electrical Characteristics - Receive Timing Signal name RxClk RxEnb*, RxAddr[4:0] RxData[7:0], RxSOC, RxClav[0] Note 1 - The RXCLK signal needs to be ...
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Clock xxxx xxxx xxxx Signal tT5, tT7 Input Setup To Clock Figure 28 - Setup and Hold Time Definition Clock Signal Valid xxxxx t 1 xxxxx T9 Signal xxxxx tT11 Signal Going Low Impedance From Clock Figure 29 - Tri-State ...
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MT90221 AC Electrical Characteristics - External Memory Interface Timing - Read Access Item Description t MT90220 System Clock Period CLK t Read Cycle Time RC t Address Setup Time AVRS t Address Hold Time AVRH t Chip Select Setup Time ...
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AC Electrical Characteristics - External Memory Interface Timing - Write Access Item Description t System Clock Period CLK t Write Cycle Time WC t Address Setup Time AVWS t Address Hold Time AVWH t Chip Select Setup Time CSWS t ...
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MT90221 9.1 CPU Interface Timing The CPU Interface of the MT90221 supports both the Motorola and Intel timing modes. No Mode Select pin is required. With Motorola devices, the Motorola R/W-signal is connected to the UP_R/W* pin and the UP_OE* ...
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AC Electrical Characteristics - CPU Interface Timing - Read Cycle Characteristics 1 R/W set-up time to UP_CS* falling edge 2 Data valid after UP_OE*, UP_CS* or UP_AD 3 UP_AD or UP_R/W* hold time after UP_CS rising edge 4 Data hold ...
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MT90221 AC Electrical Characteristics - CPU Interface Motorola Timing - Write Cycle Characteristics 1 UP_R/W* set-up time to UP_CS* falling edge 2 Address and Data set up before rising edge of UP_CS* 3 UP_AD and Data hold time after UP_CS ...
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AC Electrical Characteristics - CPU Interface Intel Timing - Write Cycle Characteristics 1 UP_CS* set-up time to UP_R/W* falling edge 2 Address and Data set up before rising edge of UP_R/W 3 UP_AD, UP_CS and Data hold time after UP_R/W* ...
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MT90221 AC Electrical Characteristics - JTAG Port and RESET Pin Timing Parameter TCK period width TCK period width LOW TCK period width HIGH TDI setup time to TCK rising TDI hold time after TCK rising TMS setup time to TCK ...
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AC Electrical Characteristics - System Clock and Reset Parameter CLK period width CLK period width LOW CLK period width HIGH CLK rising CLK falling RESET pulse width CLK RESET Symbol Min Typ TCLK t 20 TCLKL t ...
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MT90221 Pin # Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) JEDEC Standard 2.6mm Footprint MS-29 5) MQFP-208 Package complies to JEDEC Standard MS-29 Figure 37 - Metric ...
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Dimensions Metric Quad Flat Package Dimensions 208-Pin Min 0.01 (0.25) .126 (3.20) .007 (0.18) .007 (0.18) .003 (0.076) .003 (0.076) 1.197 (30.40) 1.098 ...
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MT90221 List of Changes Page Numbers Newer Older ...
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Replaced Replaced Inserted Replaced Inserted Replaced Replaced Replaced Replaced Replaced Replaced Replaced Inserted: 60 ...
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MT90221 List of Abbreviations and Acronyms AAL ATM Adaptation Layer ATM Asynchronous Transfer Mode CBR Constant Bit Rate CDV Cell Delay Variation CPE Customer Premises Equipment CRC Cyclic Redundancy Check CTC Common Transmit Clock DSU Data Service Unit FE Far ...
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Note: Although ATM cells are transmitted synchronously to main- tain the clock between sender and receiver, the sender transmits ...
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... ATM devices; provides sequential, unidirectional trans- port of ATM cells. Also Virtual Circuit . Glossary References: The ATM Glossary - ATM Year 97 - Version 2.1, March 1997 The ATM Forum Glossary - May 1997 ATM and Networking Glossary (http://www.techguide.com/comm/index.html) Mitel Semiconductor Glossary of Telecommunications Terms - May 1995. ...
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Notes: MT90221 105 ...
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... Mitel. This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specifi ...