K7D803671B-HC25 Samsung, K7D803671B-HC25 Datasheet
K7D803671B-HC25
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K7D803671B-HC25 Summary of contents
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... K7D803671B K7D801871B Document Title 8M DDR SYNCHRONOUS SRAM Revision History Rev No. History Rev. 0.0 -Initial document. Rev. 0.1 -ZQ tolerance changed from 10% to 15% Rev. 0.2 -Stop Clock Standby Current condition changed from V =V -0.2V or 0.2V fixed Rev. 0.3 -V Max. changed to 2.0V DDQ SA0, SA1 defined for Boundary Scan Order Rev ...
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... Single/Double Data Selection 3 G Asynchronous Output Enable LBO Linear Burst Order 256Kx36 & 512Kx18 SRAM Organization Part Number K7D803671B-HC37 K7D803671B-HC35 256Kx36 K7D803671B-HC33 K7D803671B-HC30 K7D803671B-HC25 K7D801871B-HC37 K7D801871B-HC35 512Kx18 K7D801871B-HC33 K7D801871B-HC30 K7D801871B-HC25 NOTE : *Access time equals 16(or 17) 2:1 Dec. MUX (Burst Address) Data Out Burst ...
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... K7D803671B K7D801871B PACKAGE PIN CONFIGURATIONS K7D803671B(256Kx36 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ T DQ ...
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... FUNCTION DESCRIPTION The K7D803671B and K7D801871B are 9,437,184 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as 262,144 words by 36 bits for K7D803671B and 524,288 words by 18 bits for K7D801871B, fabricated using Samsung's advanced CMOS technology. Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of K clock, all addresses and burst control inputs are registered internally ...
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... K7D803671B K7D801871B TRUTH TABLE NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care" & K are complementary. BURST SEQUENCE TABLE 4 Burst Operation for Interleaved Burst (LBO = V ...
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... K7D803671B K7D801871B BUS CYCLE STATE DIAGRAM READ SDR INCREMENT ADDRESS POWER UP NOTE : 1. State transitions ; B =(Load Address), B =(Increment Address, Continue =(Read), B =(Write =(Single Data Rate), B =(Double Data Rate 256Kx36 & 512Kx18 SRAM LOAD NEW ADDRESS WRITE READ SDR DDR ...
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... K7D803671B K7D801871B ABSOLUTE MAXIMUM RATINGS Parameter Core Supply Voltage Relative Output Supply Voltage Relative Voltage on any pin Relative Output Short-Circuit Current(per I/O) Storage Temperature NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data. ...
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... K7D803671B K7D801871B DC CHARACTERISTICS Parameter Average Power Supply Operating Current(x36) (Cycle time = t min) KHKH Average Power Supply Operating Current(x18) (Cycle time = t min) KHKH Stop Clock Standby Current ( K=Low, K=Low Input Leakage Current ( DDQ Output Leakage Current ...
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... K7D803671B K7D801871B AC TEST CONDITIONS Parameter Input High/Low Level Input Reference Level Input Rise/Fall Time Output Timing Reference Level Clock Input Timing Reference Level Output Load AC TEST OUTPUT LOAD TEST CONDITIONS Parameter ...
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... K7D803671B K7D801871B AC CHARACTERISTICS (For both AC test condition 1 and 2) Parameter Symbol Clock Cycle Time t KHKH Clock High Pulse Width t KHKL Clock Low Pulse Width t KLKH CQ High Pulse Width t CHCL CQ Low Pulse Width t CLCH Clock to Echo Clock(CQ) High t KXCH Clock to Echo Clock(CQ) Low ...
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... K7D803671B K7D801871B TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES READ CONTINUE READ NOP READ (burst of 4) (burst KHKH BVKH KHBX AVKH KHAX CHQV KXCH t t CHQZ ...
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... K7D803671B K7D801871B TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES READ READ CONTINUE CONTINUE NOP READ (burst KHKL KLKH KHKH BVKH KHBX AVKH KHAX KXCH t CHQV t CHQX t t CHLZ ...
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... K7D803671B K7D801871B IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform- ance with IEEE 1149 ...
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... K7D803671B K7D801871B SCAN REGISTER DEFINITION Part Instruction Register 256Kx36 3 bits 512Kx18 3 bits ID REGISTER DEFINITION Revision Number Part Configuration Part (31:28) 256Kx36 0000 512Kx18 0000 BOUNDARY SCAN EXIT ORDER(x36 ...
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... K7D803671B K7D801871B JTAG DC OPERATING CONDITIONS Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage(I =-2mA) OH Output Low Voltage(I =2mA) OL NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification. JTAG AC TEST CONDITIONS Parameter Input High/Low Level ...
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... K7D803671B K7D801871B 153 BGA PACKAGE DIMENSIONS 12.50 0.10 0.492 0.004 14.00 0.10 0.551 0.004 TOP VIEW 153 BGA PACKAGE THERMAL CHARACTERISTICS Parameter Junction to Ambient(at still air) Junction to Case Junction to Board NOTE : 1. Junction temperature can be calculated 256Kx36 & 512Kx18 SRAM 0.60 0.10 0.024 0.004 9 8 0.56 0.04 0.022 0.002 ...