MC68331MFC16 Freescale Semiconductor, Inc, MC68331MFC16 Datasheet
MC68331MFC16
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MC68331MFC16 Summary of contents
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... Freescale Semiconductor © MOTOROLA, INC. 1996 © Freescale Semiconductor, Inc., 2004. All rights reserved. MC68331 User’s Manual ...
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... Freescale Semiconductor, Inc. How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center ...
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... Freescale Semiconductor, Inc. Paragraph SECTION 2NOMENCLATURE 2.1 Symbols and Operators .................................................................................. 2-1 2.2 CPU32 Registers ............................................................................................ 2-2 2.3 Pin and Signal Mnemonics ............................................................................. 2-3 2.4 Register Mnemonics ....................................................................................... 2-5 2.5 Conventions ................................................................................................... 2-6 3.1 MCU Features ................................................................................................ 3-1 3.1.1 System Integration Module (SIM) ........................................................... 3-1 3.1.2 Central Processing Unit (CPU32) ........................................................... 3-1 3.1.3 Queued Serial Module (QSM) ................................................................ 3-1 3.1.4 General-Purpose Timer (GPT) ............................................................... 3-2 3.2 System Block Diagram and Pin Assignment Diagrams .................................. 3-2 3 ...
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... Freescale Semiconductor, Inc. Paragraph 4.2.11 Periodic Interrupt Timer .......................................................................... 4-7 4.2.12 Low-Power STOP Operation .................................................................. 4-8 4.2.13 Freeze Operation ................................................................................... 4-9 4.3 System Clock ................................................................................................. 4-9 4.3.1 Clock Sources ...................................................................................... 4-10 4.3.2 Clock Synthesizer Operation ................................................................ 4-10 4.3.3 External Bus Clock ............................................................................... 4-15 4.3.4 Low-Power Operation ........................................................................... 4-15 4.3.5 Loss of Reference Signal ..................................................................... 4-16 4.4 External Bus Interface .................................................................................. 4-17 4.4.1 Bus Signals .......................................................................................... 4-18 4.4.1.1 Address Bus ................................................................................. 4-18 4.4.1.2 Address Strobe ............................................................................ 4-18 4.4.1.3 Data Bus ...................................................................................... 4-18 4.4.1.4 Data Strobe .................................................................................. 4-18 4 ...
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... Freescale Semiconductor, Inc. Paragraph 4.5.6.1 Slave (Factory Test) Mode Arbitration ......................................... 4-35 4.5.6.2 Show Cycles ................................................................................ 4-35 4.6 Reset ............................................................................................................ 4-36 4.6.1 Reset Exception Processing ................................................................ 4-36 4.6.2 Reset Control Logic .............................................................................. 4-37 4.6.3 Reset Mode Selection .......................................................................... 4-37 4.6.3.1 Data Bus Mode Selection ............................................................. 4-38 4.6.3.2 Clock Mode Selection .................................................................. 4-40 4.6.3.3 Breakpoint Mode Selection .......................................................... 4-40 4.6.4 MCU Module Pin Function During Reset ............................................. 4-40 4.6.5 Pin State During Reset ......................................................................... 4-41 4 ...
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... Freescale Semiconductor, Inc. Paragraph 5.2.1 Data Registers ........................................................................................ 5-4 5.2.2 Address Registers .................................................................................. 5-5 5.2.3 Program Counter .................................................................................... 5-6 5.2.4 Control Registers .................................................................................... 5-6 5.2.4.1 Status Register ............................................................................... 5-6 5.2.4.2 Alternate Function Code Registers ................................................ 5-6 5.2.5 Vector Base Register (VBR) ................................................................... 5-7 5.3 Memory Organization ..................................................................................... 5-7 5.4 Virtual Memory ............................................................................................... 5-9 5.5 Addressing Modes .......................................................................................... 5-9 5.6 Processing States .......................................................................................... 5-9 5.7 Privilege Levels ............................................................................................ 5-10 5.8 Instructions ................................................................................................... 5-10 5.8.1 M68000 Family Compatibility ............................................................... 5-14 5.8.2 Special Control Instructions .................................................................. 5-14 5.8.2.1 Low Power Stop (LPSTOP) ......................................................... 5-14 5 ...
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... Freescale Semiconductor, Inc. Paragraph 6.2.1.2 Freeze Operation ........................................................................... 6-3 6.2.1.3 QSM Interrupts ............................................................................... 6-3 6.2.2 QSM Pin Control Registers .................................................................... 6-4 6.3 Queued Serial Peripheral Interface ................................................................ 6-5 6.3.1 QSPI Registers ....................................................................................... 6-6 6.3.1.1 Control Registers ........................................................................... 6-7 6.3.1.2 Status Register ............................................................................... 6-7 6.3.2 QSPI RAM .............................................................................................. 6-7 6.3.2.1 Receive RAM ................................................................................. 6-8 6.3.2.2 Transmit RAM ................................................................................ 6-8 6.3.2.3 Command RAM .............................................................................. 6-8 6.3.3 QSPI Pins ............................................................................................... 6-8 6.3.4 QSPI Operation ...................................................................................... 6-9 6.3.5 QSPI Operating Modes ........................................................................ 6-10 6.3.5.1 Master Mode ................................................................................ 6-17 6.3.5.2 Master Wraparound Mode ........................................................... 6-19 6 ...
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... Freescale Semiconductor, Inc. Paragraph 7.3.1 Low-Power Stop Mode ........................................................................... 7-3 7.3.2 Freeze Mode .......................................................................................... 7-3 7.3.3 Single-Step Mode ................................................................................... 7-3 7.3.4 Test Mode .............................................................................................. 7-4 7.4 Polled and Interrupt-Driven Operation ............................................................ 7-4 7.4.1 Polled Operation ..................................................................................... 7-4 7.4.2 GPT Interrupts ........................................................................................ 7-5 7.5 Pin Descriptions ............................................................................................. 7-6 7.5.1 Input Capture Pins (IC[1:3]) .................................................................... 7-6 7.5.2 Input Capture/Output Compare Pin (IC4/OC5) ...................................... 7-6 7.5.3 Output Compare Pins (OC[1:4]) ............................................................. 7-6 7.5.4 Pulse Accumulator Input Pin (PAI) ......................................................... 7-7 7.5.5 Pulse-Width Modulation (PWMA, PWMB) .............................................. 7-7 7 ...
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... Freescale Semiconductor, Inc. Paragraph D.2 General-Purpose Timer ............................................................................ D-4 D.2.1 GPTMCR — GPT Module Configuration Register ............................ D-4 D.2.2 GPTMTR — GPT Module Test Register (Reserved) ........................ D-5 D.2.3 ICR — GPT Interrupt Configuration Register .................................... D-5 D.2.4 DDRGP — Port GP Data Direction Register..................................... D-6 D.2.5 OC1M— OC1 Action Mask Register ................................................. D-6 D.2.6 TCNT — Timer Counter Register ..................................................... D-6 D.2.7 PACTL — ...
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... Freescale Semiconductor, Inc. Paragraph D.3.22 PORTC — Port C Data Register ..................................................... D-21 D.3.23 CSPAR0 — Chip Select Pin Assignment Register 0....................... D-21 D.3.24 CSPAR1 — Chip Select Pin Assignment Register 1....................... D-22 D.3.25 CSBARBT — Chip Select Base Address Register Boot ROM ....... D-23 D.3.26 CSORBT — Chip Select Option Register Boot ROM...................... D-23 D.4 Queued Serial Module ............................................................................ D-25 D.4.1 QSMCR — ...
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... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure 3-1 MCU Block Diagram........................................................................................ 3-3 3-2 Pin Assignments for 132-Pin Package ............................................................ 3-4 3-3 Pin Assignments for 144-Pin Package ............................................................ 3-5 3-4 Internal Register Memory Map ...................................................................... 3-11 3-5 Overall Memory Map ..................................................................................... 3-12 3-6 Separate Supervisor and User Space Map................................................... 3-13 3-7 Supervisor Space (Separate Program/Data Space) Map ............................. 3-14 3-8 User Space (Separate Program/Data Space) Map ....................................... 3-15 4-1 System Integration Module Block Diagram ...
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... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure 6-3 QSPI RAM....................................................................................................... 6-7 6-4 Flowchart of QSPI Initialization Operation..................................................... 6-11 6-5 Flowchart of QSPI Master Operation (Part 1) ............................................... 6-12 6-5 Flowchart of QSPI Master Operation (Part 2) ............................................... 6-13 6-5 Flowchart of QSPI Master Operation (Part 3) ............................................... 6-14 6-6 Flowchart of QSPI Slave Operation (Part 1) ................................................. 6-15 6-6 Flowchart of QSPI Slave Operation (Part 2) ................................................. 6-16 6-7 SCI Transmitter Block Diagram..................................................................... 6-23 6-8 SCI Receiver Block Diagram ...
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... Freescale Semiconductor, Inc. Table 3-1 MCU Driver Types .......................................................................................... 3-6 3-2 MCU Pin Characteristics ................................................................................ 3-6 3-3 MCU Power Connections ............................................................................... 3-7 3-4 Signal Characteristics ..................................................................................... 3-7 3-5 Signal Function ............................................................................................... 3-8 3-6 SIM Reset Mode Selection ........................................................................... 3-16 3-7 Module Pin Functions ................................................................................... 3-17 4-1 Show Cycle Enable Bits ................................................................................. 4-4 4-2 Bus Monitor Period ......................................................................................... 4-5 4-3 MODCLK Pin and SWP Bit During Reset ...................................................... 4-6 4-4 Software Watchdog Ratio ............................................................................... 4-6 4-5 MODCLK Pin and PTP Bit at Reset ...
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... Freescale Semiconductor, Inc. Table 6-5 Serial Frame Formats ...................................................................................6-26 6-6 Effect of Parity Checking on Data Size .........................................................6-27 7-1 GPT Status Flags ............................................................................................7-4 7-2 GPT Interrupt Sources ....................................................................................7-5 7-3 PWM Frequency Ranges Using 16.78-MHz/20.97-MHz System Clocks ......7-17 A-1 Maximum Ratings .......................................................................................... A-1 A-2 Typical Ratings, 16.78 MHz Operation .......................................................... A-2 A-2 Typical Ratings, 20.97 MHz Operation ......................................................... A-2 A-3 Thermal Characteristics ................................................................................. A-3 A-4 16.78 MHz Clock Control Timing ................................................................... A-3 A-4 20 ...
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... Freescale Semiconductor, Inc. SECTION 1INTRODUCTION The MC68331, a highly-integrated 32-bit microcontroller, combines high-performance data manipulation capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that interface through a common intermodule bus (IMB). Standardization facilitates rapid development of devices tailored for specific applica- tions ...
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... Freescale Semiconductor, Inc. INTRODUCTION For More Information On This Product, Go to: www.freescale.com MC68331 USER’S MANUAL ...
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... Freescale Semiconductor, Inc. SECTION 2NOMENCLATURE The following nomenclature is used throughout the manual. Nomenclature used only in certain sections, such as register bit mnemonics, is defined in those sections. 2.1 Symbols and Operators — Addition — Subtraction or negation (two's complement) — Multiplication — Division — Greater — Less — ...
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... SR — Status register VBR — Vector base register X — Extend indicator N — Negative indicator Z — Zero indicator 2 V — Two's complement overflow indicator C — Carry/borrow indicator 2-2 Freescale Semiconductor, Inc. NOMENCLATURE For More Information On This Product, Go to: www.freescale.com MC68331 USER’S MANUAL ...
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... Freescale Semiconductor, Inc. 2.3 Pin and Signal Mnemonics ADDR[23:0] — Address Bus AS — Address Strobe AVEC — Autovector BERR — Bus Error BG — Bus Grant BGACK — Bus Grant Acknowledge BKPT — Breakpoint BR — Bus Request CLKOUT — System Clock CS[10:0] — Chip Selects CSBOOT — ...
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... SIZ[1:0] — Size SS — Slave Select TSC — Three-State Control TXD — SCI Transmit Data XFC — External Filter Capacitor XTAL — External Crystal Oscillator Connection 2 2-4 Freescale Semiconductor, Inc. NOMENCLATURE For More Information On This Product, Go to: www.freescale.com MC68331 USER’S MANUAL ...
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... Freescale Semiconductor, Inc. 2.4 Register Mnemonics CFORC — GPT Compare Force Register CREG — Test Control Register C CR[0:F] — QSM Command RAM CSBARBT — Chip-Select Base Address Register Boot ROM CSBAR[0:10] — Chip-Select Base Address Registers [0:10] CSORBT — Chip-Select Option Register Boot ROM CSOR[0:10] — ...
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... Negated means that an asserted signal changes logic state. An active low signal changes from logic level zero to logic level one when negated, and an active high sig- nal changes from logic level one to logic level zero. 2-6 Freescale Semiconductor, Inc. RSR — Reset Status Register NOMENCLATURE For More Information On This Product, Go to: www ...
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... Freescale Semiconductor, Inc. A specific mnemonic within a range is referred to by mnemonic and number. A15 is bit 15 of accumulator A; ADDR7 is line 7 of the address bus; CSOR0 is chip-select op- tion register 0. A range of mnemonics is referred to by mnemonic and the numbers that define the range. AM[35:30] are bits accumulator M; CSOR[0:5] are the first six option registers ...
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... Freescale Semiconductor, Inc. NOMENCLATURE For More Information On This Product, Go to: www.freescale.com MC68331 USER’S MANUAL ...
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... Freescale Semiconductor, Inc. This section contains information about the entire modular microcontroller. It lists the features of each module, shows device functional divisions and pin assignments, sum- marizes signal and pin functions, discusses the intermodule bus, and provides system memory maps. Timing and electrical specifications for the entire microcontroller and for individual modules are provided in APPENDIX A ELECTRICAL CHARACTERIS- TICS ...
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... Refer to APPENDIX B MECHANICAL DATA AND ORDERING IN- 3 FORMATION for package dimensions. All pin functions and signal names are shown in this drawing. Refer to subsequent paragraphs in this section for pin and signal de- scriptions. 3-2 Freescale Semiconductor, Inc. OVERVIEW For More Information On This Product, Go to: www.freescale.com MC68331 USER’S MANUAL ...
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... Freescale Semiconductor, Inc. PWMA PWMA PWMB PWMB PCLK PCLK PAI PAI PGP7/IC4/OC5/OC1 PGP7/IC4/OC5/OC1 PGP6/OC4/OC1 PGP6/OC4/OC1 PGP5/OC3/OC1 PGP5/OC3/OC1 PGP4/OC2/OC1 PGP4/OC2/OC1 PGP3/OC1 PGP3/OC1 PGP2/IC3 PGP2/IC3 PGP1/IC2 PGP1/IC2 PGP0/IC1 PGP0/IC1 RXD PQS7/TXD TXD PQS6/PCS3 PCS3 PQS5/PCS2 PCS2 PQS4/PCS1 PCS1 PQS3/PCS0/SS PCS0/SS PQS2/SCK SCK PQS1/MOSI ...
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... PQS0/MISO 43 PQS1/MOSI 44 PQS2/SCK 45 PQS3/PCS0/SS 46 PQS4/PCS1 47 PQS5/PCS2 48 PQS6/PCS3 Figure 3-2 Pin Assignments for 132-Pin Package 3-4 Freescale Semiconductor, Inc. MC68331 OVERVIEW For More Information On This Product, Go to: www.freescale.com V 116 DD 115 BGACK/CS2 114 BG/CS1 BR/CS0 113 112 CSBOOT 111 DATA0 110 DATA1 109 ...
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... Freescale Semiconductor, Inc FC0/CS3 3 4 FC1/CS4 FC2/CS5 5 6 ADDR19/CS6 7 ADDR20/CS7 8 ADDR21/CS8 9 ADDR22/CS9 10 ADDR23/CS10 PCLK PWMB 14 15 PWMA PAI GP7/IC4/OC5/OC1 23 24 PGP6/OC4 PGP5/OC3/OC1 29 PGP4/OC2/OC1 30 PGP3/OC1 31 PGP2/IC3 ...
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... DSO/IPIPE EXTAL2 FC[2:0]/CS[5:3] FREEZE/QUOT IC4/OC5 IC[3:1] HALT IRQ[7:1] MISO 1 MODCLK MOSI OC[4:1] 2 PAI 2 PCLK PCSO/SS PCS[3:1] PWMA, PWMB R/W RESET RMC 3-6 Freescale Semiconductor, Inc. Table 3-1 MCU Driver Types Description Table 3-2 MCU Pin Characteristics Output Input Driver Synchronized — — ...
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... Freescale Semiconductor, Inc. Table 3-2 MCU Pin Characteristics (Continued) Pin Mnemonic RXD SCK SIZ[1:0] TSC TXD 3 XFC 3 XTAL 1. DATA[15:0] are synchronized during reset only. MODCLK is synchronized only when used as an input port pin. 2. EXTAL, XFC, and XTAL are clock reference connections. 3. PAI and PCLK can be used for discrete input, but are not part of an I/O port. ...
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... Address Bus Address Strobe Autovector Bus Error Bus Grant Bus Grant Acknowledge Breakpoint Bus Request System Clockout Chip Selects Boot Chip Select Data Bus 3-8 Freescale Semiconductor, Inc. Table 3-4 Signal Characteristics (Continued) MCU Module SIM SIM SIM GPT CPU32 CPU32 SIM QSM SIM ...
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... Freescale Semiconductor, Inc. Table 3-5 Signal Function (Continued) Signal Name Mnemonic Data Strobe Data and Size Acknowledge DSACK[1:0] Development Serial In, Out, Clock DSI, DSO, Crystal Oscillator EXTAL, XTAL Connections for clock synthesizer circuit reference; a crystal or an Function Codes Freeze FREEZE Halt Input Capture ...
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... CENTRAL PROCESSING UNIT for more information concerning memory manage- ment, extended addressing, and exception processing. Refer to SECTION 4 SYSTEM INTEGRATION MODULE for more information concerning function codes and ad- dress space types. 3-10 Freescale Semiconductor, Inc. OVERVIEW For More Information On This Product, Go to: www.freescale.com MC68331 ...
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... Freescale Semiconductor, Inc M111, where M is the state of the module mapping (MM) bit in the SIM configuration register. Figure 3-4 Internal Register Memory Map MC68331 USER’S MANUAL For More Information On This Product, $YFF000 $YFF900 GPT $YFF93F $YFFA00 SIM $YFFA7F $YFFA80 RESERVED $YFFAFF $YFFC00 ...
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... Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configuration register M111, where M is the state of the MM bit. 3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally. 3-12 Freescale Semiconductor, Inc. VECTOR VECTOR NUMBER ...
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... Freescale Semiconductor, Inc. $000000 VECTOR OFFSET 0000 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 002C 0030 0034 0038 003C 0040–005C 006C 0064 SUPERVISOR 0068 SPACE 006C 0070 0074 0078 007C 0080–00BC 00C0–00EB 00EC–00FC 0100–03FC ...
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... Y = M111, where M is the state of the MM bit. 3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally. 4. Some internal registers are not available in user space. Figure 3-7 Supervisor Space (Separate Program/Data Space) Map 3-14 Freescale Semiconductor, Inc. VECTOR VECTOR EXCEPTION VECTORS LOCATED OFFSET ...
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... Freescale Semiconductor, Inc. $000000 USER PROGRAM SPACE $FFFFFF NOTES: 1. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configuration register M111, where M is the state of the MM bit. 2. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally. ...
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... Table 3 summary of reset mode selection options. Mode Select Pin 3 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA11 MODCLK BKPT 3-16 Freescale Semiconductor, Inc. Table 3-6 SIM Reset Mode Selection Default Function (Pin Left High) CSBOOT 16-Bit CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS[7:6] CS[8:6] CS[9:6] CS[10:6] DSACK0, DSACK1, ...
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... Freescale Semiconductor, Inc. 3.7.2 MCU Module Pin Function During Reset Generally, pins associated with modules other than the SIM default to port functions, and input/output ports are set to input state. This is accomplished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port data direction registers ...
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... Freescale Semiconductor, Inc. OVERVIEW For More Information On This Product, Go to: www.freescale.com MC68331 USER’S MANUAL ...
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... Freescale Semiconductor, Inc. SECTION 4 SYSTEM INTEGRATION MODULE This section is an overview of SIM function. Refer to the SIM Reference Manual (SIM- RM/AD) for a comprehensive discussion of SIM capabilities. Refer to APPENDIX D REGISTER SUMMARY for information concerning the SIM address map and register structure. 4.1 General The system integration module (SIM) consists of five functional blocks. Figure 4 block diagram of the SIM ...
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... System Configuration and Protection The system configuration and protection functional block controls module configura- tion, preserves reset status, monitors internal activity, and provides periodic interrupt generation. Figure 4 block diagram of the submodule. 4-2 Freescale Semiconductor, Inc. SYSTEM CONFIGURATION AND PROTECTION CLOCK SYNTHESIZER CHIP SELECTS ...
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... Freescale Semiconductor, Inc. SPURIOUS INTERRUPT MONITOR CLOCK 9 2 PRESCALER Figure 4-2 System Configuration and Protection 4.2.1 Module Mapping Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte block. The state of the module mapping bit (MM) in the SIM module configuration reg- ister (SIMCR) determines where the control register block is located in the system memory map. When register addresses range from $7FF000 to $7FFFFF ...
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... The internal bus monitor checks data and size acknowledge (DSACK) or autovector (AVEC) signal response times during normal bus cycles. The monitor asserts the in- ternal bus error (BERR) signal when the response time is excessively long. 4-4 Freescale Semiconductor, Inc. Table 4-1 Show Cycle Enable Bits SHEN 00 ...
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... Freescale Semiconductor, Inc. DSACK and AVEC response times are measured in clock cycles. Maximum allowable response time can be selected by setting the bus monitor timing (BMT) field in the sys- tem protection control register (SYPCR). Table 4-2 shows the periods allowed. Table 4-2 Bus Monitor Period ...
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... Figure 4 block diagram of the watchdog timer and the clock control for the pe- riodic interrupt timer. 4-6 Freescale Semiconductor, Inc. MODCLK 0 (External Clock) 1 (Internal Clock) Time-out Period ...
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... Freescale Semiconductor, Inc. SWP PTP FREEZE CLOCK EXTAL PRESCALER (2 DISABLE LPSTOP SWT1 SWT0 SWE Figure 4-3 Periodic Interrupt Timer and Software Watchdog Timer 4.2.11 Periodic Interrupt Timer The periodic interrupt timer allows the generation of interrupts of specific priority at pre- determined intervals. This capability is often used to schedule control system tasks that must be performed within time constraints ...
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... MCU out of the low-power stop condition if it has a higher priority than the interrupt mask value stored in the clock control logic when low- power stop is initiated. LPSTOP can be terminated by a reset. 4-8 Freescale Semiconductor, Inc. PIT Modulus Prescaler Value 4 PIT Period = ...
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... Freescale Semiconductor, Inc. 4.2.13 Freeze Operation The FREEZE signal halts MCU operations during debugging. FREEZE is asserted in- ternally by the CPU32 if a breakpoint occurs while background mode is enabled. When FREEZE is asserted, only the bus monitor, software watchdog, and periodic interrupt timer are affected. The halt monitor and spurious interrupt monitor continue to operate normally ...
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... DDSYN erence frequency is applied. A separate power source increases MCU noise immunity and can be used to run the clock when the MCU is powered down. A quiet power sup- ply must be used as the V be placed as close as possible to the V 4-10 Freescale Semiconductor, Inc 330k R2 ...
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... Freescale Semiconductor, Inc. cy. When an external system clock signal is applied and the PLL is disabled, V should be connected to the V AD) for more information regarding system clock power supply conditioning. A voltage controlled oscillator (VCO) generates the system clock signal. To maintain a 50% clock duty cycle, VCO frequency is either two or four times system clock fre- quency, depending on the state of the X bit in SYNCR ...
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... Modulus Y 000000 000001 000010 011111 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 4-12 Freescale Semiconductor, Inc SYSTEM REFERENCE Table 4-7 Clock Control Multipliers Prescalers [W: [W: ...
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... Freescale Semiconductor, Inc. Table 4-7 Clock Control Multipliers (Continued) To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value in appropriate prescaler cell. Modulus Y [W: 010100 88 010101 92 010110 96 010111 100 011000 104 011001 108 011010 112 011011 116 ...
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... Freescale Semiconductor, Inc. Prescaler [W: [W: 131 262 262 524 393 786 524 1049 655 1311 786 1573 918 1835 1049 2097 1180 ...
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... Freescale Semiconductor, Inc. Table 4-8 System Frequencies from 32.768-kHz Reference (Continued) To obtain clock frequency in kilohertz, find counter modulus in the left column, then look in appropriate prescaler cell. Shaded cells contain values that exceed specified maximum system frequency. Modulus Y [W: 101101 6029 101110 6160 ...
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... maximum system clock frequency when When RSTEN is set, the SIM resets the MCU. The limp status bit (SLIMP) in SYNCR indicates whether the synthesizer has a refer- ence signal set when a reference failure is detected. 4-16 Freescale Semiconductor, Inc. Table 4-9 Clock Control Pins SYNCR Bits EXTAL ...
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... Freescale Semiconductor, Inc. 4.4 External Bus Interface The external bus interface (EBI) transfers information between the internal MCU bus and external devices. Figure 4-7 shows a basic system with external memory and pe- ripherals. FC SIZ CLKOUT AS DSACK DS CS3 CS5 IRQ ADDR[23:0] DATA[15:0] MCU CSBOOT R/W 1. Can be decoded to provide additional address space. ...
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... Size signals (SIZ[1:0]) indicate the number of bytes remaining to be transferred during an operand cycle. They are valid while the address strobe (AS) is asserted. Table 4- 10 shows SIZ0 and SIZ1 encoding. 4-18 Freescale Semiconductor, Inc. SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
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... Freescale Semiconductor, Inc. Table 4-10 Size Signal Encoding SIZ1 4.4.1.7 Function Codes The CPU generates function code output signals FC[2:0] to indicate the type of activity occurring on the data or address bus. These signals can be considered address ex- tensions that can be externally decoded to determine which of eight external address spaces is accessed during a bus cycle ...
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... If the CPU is executing an instruction that reads a long-word operand from a 16-bit port, the MCU latches the 16 bits of valid data and then runs another bus cycle to ob- 4-20 Freescale Semiconductor, Inc. Table 4-12 Effect of DSACK Signals DSACK0 1 Insert Wait States in Current Bus Cycle 0 Complete Cycle — ...
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... Freescale Semiconductor, Inc. tain the other 16 bits. The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the DSACK signals to indicate the port width. For instance, a 16-bit device always returns DSACK for a 16-bit port (regardless of wheth- er the bus cycle is a byte or word operation) ...
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... RM/AD) for more information about each type of bus cycle. The MCU is responsible for de-skewing signals it issues at both the start and the end of a cycle. In addition, the MCU is responsible for de-skewing acknowledge and data signals from peripheral devices. 4-22 Freescale Semiconductor, Inc. Table 4-13 Operand Transfer Cases SIZ ADDR0 DSACK [1:0] ...
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... Freescale Semiconductor, Inc. 4.5.1 Synchronization to CLKOUT External devices connected to the MCU bus can operate at a clock frequency different from the frequencies of the MCU as long as the external devices satisfy the interface signal timing constraints. Although bus cycles are classified as asynchronous, they are interpreted relative to the MCU system clock output (CLKOUT). ...
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... DRIVE SIZ[1:0] FOR OPERAND SIZE ASSERT AS AND DS (S1) DECODE DSACK (S3) LATCH DATA (S4) NEGATE AS AND DS (S5) START NEXT CYCLE (S0) 4-24 Freescale Semiconductor, Inc. NOTE MCU 1) DECODE ADDR, R/W, SIZ[1:0 PLACE DATA ON DATA[15:0] OR DATA[15:8] IF 8-BIT DATA 3) DRIVE DSACK SIGNALS 1) REMOVE DATA FROM DATA BUS ...
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... Freescale Semiconductor, Inc. 4.5.2.2 Write Cycle During a write cycle, the MCU transfers data to an external memory or peripheral de- vice. If the instruction specifies a long-word or word operation, the MCU attempts to write two bytes at once. For a byte operation, the MCU writes one byte. The portion of the data bus upon which each byte is written depends on operand size, peripheral ad- dress, and peripheral port size ...
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... These encodings represent breakpoint acknowledge (Type $0) cycles low power stop broadcast (Type $3) cycles, and interrupt acknowledge (Type $F) cycles. Refer to 4.7 Interrupts for information about interrupt acknowledge bus cycles. 4-26 Freescale Semiconductor, Inc. SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
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... Freescale Semiconductor, Inc. FUNCTION CODE 2 BREAKPOINT ACKNOWLEDGE 2 LOW POWER STOP BROADCAST 2 INTERRUPT ACKNOWLEDGE Figure 4-11 CPU Space Address Encoding 4.5.4.1 Breakpoint Acknowledge Cycle Breakpoints stop program execution at a predefined point during system development. Breakpoints can be used alone or in conjunction with the background debugging mode ...
Page 70
... BKPT is latched. Refer to the CPU32 Reference Manual (CPU32RM/AD) and the SIM Reference Man- ual (SIMRM/AD) for additional information. 4-28 Freescale Semiconductor, Inc. SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’S MANUAL ...
Page 71
... Freescale Semiconductor, Inc. CPU32 ACKNOWLEDGE BREAKPOINT IF BREAKPOINT INSTRUCTION EXECUTED: 1) SET R/W TO READ 2) SET FUNCTION CODE TO CPU SPACE 3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16] 4) PLACE BREAKPOINT NUMBER ON ADDR[4:2] 5) CLEAR T-BIT (ADDR1) TO ZERO 6) SET SIZE TO WORD 7) ASSERT AS AND DS IF BKPT PIN ASSERTED: 1) SET R/W TO READ ...
Page 72
... HALT is asserted at the same time or before DSACK, and BERR remains negated (case 2). Bus Error Termination BERR is asserted in lieu of, at the same time as, or before DSACK (case 3), or after DSACK (case 4), and HALT remains negated; BERR is negated at the same time or after DSACK. 4-30 Freescale Semiconductor, Inc ...
Page 73
... Freescale Semiconductor, Inc. Retry Termination HALT and BERR are asserted in lieu of, at the same time as, or before DSACK (case 5) or after DSACK (case 6); BERR is negated at the same time or after DSACK; HALT may be negated at the same time or after BERR. Table 4-14 shows various combinations of control signal sequences and the resulting bus cycle terminations ...
Page 74
... Multiple bus errors within a single instruction that can generate multiple bus cycles cause a single bus error exception after the instruction has been executed. 4-32 Freescale Semiconductor, Inc. CAUTION SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www ...
Page 75
... Freescale Semiconductor, Inc. Immediately after assertion of a second BERR, the MCU halts and drives the HALT line low. Only a reset can restart a halted MCU. However, bus arbitration can still occur (refer to 4.5.6 External Bus Arbitration). A bus error or address error that occurs after exception processing has been completed (during the execution of the exception han- dler routine, or later) does not cause a double bus fault ...
Page 76
... Refer to Figure 4-14, which shows bus arbitration for a single device. The flowchart shows BR negated at the same time BGACK is asserted. 4-34 Freescale Semiconductor, Inc. SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com MC68331 ...
Page 77
... Freescale Semiconductor, Inc. MCU GRANT BUS ARBITRATION 1) ASSERT BUS GRANT (BG) TERMINATE ARBITRATION 1) NEGATE BG (AND WAIT FOR BGACK TO BE NEGATED) RE-ARBITRATE OR RESUME PROCESSOR OPERATION Figure 4-14 Bus Arbitration Flowchart for Single Request State changes occur on the next rising edge of CLKOUT after the internal signal is val- id ...
Page 78
... Only essential reset tasks are performed during excep- tion processing. Other initialization tasks must be accomplished by the exception handler routine. 4.6.8 Reset Processing Summary contains details of exception pro- cessing. 4-36 Freescale Semiconductor, Inc. SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com MC68331 ...
Page 79
... Freescale Semiconductor, Inc. 4.6.2 Reset Control Logic SIM reset control logic determines the cause of a reset, synchronizes reset assertion if necessary to the completion of the current bus cycle, and asserts the appropriate re- set lines. Reset control logic can drive four different internal signals. 1. EXTRST (external reset) drives the external reset pin. ...
Page 80
... The first bus cycle occurs ten CLKOUT cycles after RESET is re- leased. If external mode selection logic causes a conflict of this type, an isolation re- sistor on the driven lines may be required. Figure 4-15 shows a recommended method for conditioning the mode select signals. 4-38 Freescale Semiconductor, Inc. Table 4-16 Reset Mode Selection Default Function (Pin Left High) CSBOOT 16-Bit ...
Page 81
... Freescale Semiconductor, Inc. DATA15 • • • • MODE SELECT • • DATA1 LINES DATA0 RESET DS R/W * Optional, to prevent conflict on RESET negation. Figure 4-15 Data Bus Mode Select Conditioning Data bus mode select current is specified in APPENDIX A ELECTRICAL CHARAC- TERISTICS. Do not confuse pin function with pin electrical state. Refer to 4.6.5 Pin State During Reset for more information ...
Page 82
... Refer to individual module sections in this manual for more information. Table 4- summary of mod- ule pin function out of reset. Refer to APPENDIX D REGISTER SUMMARY for register function and reset state. 4-40 Freescale Semiconductor, Inc. NOTE SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
Page 83
... Freescale Semiconductor, Inc. Table 4-17 Module Pin Functions Module CPU32 GPT QSM 4.6.5 Pin State During Reset It is important to keep the distinction between pin function and pin electrical state clear. Although control register values and mode select inputs determine pin function, a pin driver can be active, inactive or in high-impedance state while reset occurs. During power-up reset, pin state is subject to the constraints discussed in 4 ...
Page 84
... The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer being externally driven, to guarantee this length of reset to the entire system. 4-42 Freescale Semiconductor, Inc. Table 4-18 SIM Pin Reset States State While Pin State After RESET Released ...
Page 85
... Freescale Semiconductor, Inc internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of 512 cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert RESET until the internal reset signal is negated. After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for ten cycles ...
Page 86
... The second long word of the vector is loaded into the program counter. Vectors can be fetched from internal RAM or from external ROM enabled by the CSBOOT signal. C. The CPU32 fetches and begins decoding the first instruction to be executed. 4-44 Freescale Semiconductor, Inc. 10 CLOCKS 512 CLOCKS ADDRESS AND CONTROL SIGNALS ...
Page 87
... Freescale Semiconductor, Inc. 4.6.9 Reset Status Register The reset status register (RSR) contains a bit for each reset source in the MCU. When a reset occurs, a bit corresponding to the reset type is set. When multiple causes of reset occur at the same time, more than one bit in RSR may be set. The reset status register is updated by the reset control logic when the RESET signal is released ...
Page 88
... IARB field value of %0000, a spu- rious interrupt exception is processed. Do not assign the same arbitration priority to more than one module. When two or more IARB fields have the same nonzero value, the 4-46 Freescale Semiconductor, Inc. WARNING SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
Page 89
... Freescale Semiconductor, Inc. CPU32 interprets multiple vector numbers at the same time, with un- predictable consequences. Because the EBI manages external interrupt requests, the SIM IARB value is used for arbitration between internal and external interrupt requests. The reset value of IARB for the SIM is %1111, and the reset IARB value for all other modules is %0000. ...
Page 90
... Address block sizes of two Kbytes to one Mbyte can be selected. Figure 4- diagram of a basic system that uses chip selects. 4-48 Freescale Semiconductor, Inc. SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
Page 91
... Freescale Semiconductor, Inc. FC SIZ CLKOUT AS DSACK DS CS3 CS5 IRQ ADDR[23:0] DATA[15:0] MCU CSBOOT R/W 1. Can be decoded to provide additional address space. 2. Varies depending upon peripheral memory size. Figure 4-17 Basic MCU System Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobe, or interrupt acknowledge signals. Chip select logic can also generate DSACK and AVEC signals internally ...
Page 92
... Initialization software usually resides in a peripheral memory device controlled by the chip-select circuits. A set of special chip-select functions and registers (CSORBT, CS- BARBT) is provided to support bootstrap operation. Comprehensive address maps and register diagrams are provided in APPENDIX D REGISTER SUMMARY. 4-50 Freescale Semiconductor, Inc. BASE ADDRESS REGISTER ADDRESS COMPARATOR OPTION COMPARE OPTION REGISTER PIN ...
Page 93
... Freescale Semiconductor, Inc. 4.8.1.1 Chip-Select Pin Assignment Registers The pin assignment registers contain twelve 2-bit fields (CS[10:0] and CSBOOT) that determine the functions of the chip-select pins. Each pin has two or three possible functions, as shown in Table 4-19. Table 4-19 Chip-Select Pin Functions 16-Bit Chip Select CSBOOT ...
Page 94
... To assert a chip-select signal, and to provide DSACK or autovector support, other constraints set by fields in the option register and in the base address register must also be satisfied. Table 4- summary of option register functions. 4-52 Freescale Semiconductor, Inc. Table 4-21 Block Size Encoding Block Size Address Lines Compared ...
Page 95
... Freescale Semiconductor, Inc. Table 4-22 Option Register Function Summary MODE BYTE R ASYNC Disable 00 = Rsvd 1 = SYNC 01 = Lower 01 = Read 10 = Upper 10 = Write *11 = Both 11 = Both *Use this value when function is not required for chip-select operation. The MODE bit determines whether chip-select assertion simulates an asynchronous bus cycle synchronized to the M6800-type bus clock signal (ECLK) available on ADDR23 (refer to 4 ...
Page 96
... CPU space access. Refer to 4.5.4 CPU Space Cycles for more informa- tion. There are no differences in flow for chip selects in each type of space, but base and option registers must be properly programmed for each type of external bus cycle. 4-54 Freescale Semiconductor, Inc. SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
Page 97
... Freescale Semiconductor, Inc. During a CPU space cycle, bits [15:3] of the appropriate base register must be config- ured to match ADDR[23:11], as the address is compared to an address generated by the CPU. Figure 4-19 shows CPU space encoding for an interrupt acknowledge cycle. FC[2:0] are set to %111, designating CPU space access. ADDR[3:1] indicate interrupt priority, and the space type field (ADDR[19:16]) is set to %1111, the interrupt acknowledge code ...
Page 98
... CSBOOT signal is asserted. The block size field in CSBARBT has a reset value of 1 Mbyte. Table 4-24 shows CSBOOT reset values. 4-56 Freescale Semiconductor, Inc. Fields Reset Values Base Address ...
Page 99
... Freescale Semiconductor, Inc. Table 4-24 CSBOOT Base and Option Register Reset Values Base Address Block Size Async/Sync Mode Upper/Lower Byte Read/Write AS/DS DSACK Address Space Autovector 4.9 Parallel Input/Output Ports Fifteen SIM pins can be configured for general-purpose discrete input and output. Al- though these pins are organized into two ports, port E and port F, function assignment is by individual pin ...
Page 100
... Freescale Semiconductor, Inc. SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’S MANUAL ...
Page 101
... Freescale Semiconductor, Inc. SECTION 5 CENTRAL PROCESSING UNIT The CPU32, the instruction processing module of the M68300 family, is based on the industry-standard MC68000 processor. It has many features of the MC68010 and MC68020, as well as unique features suited for high-performance controller applica- tions. This section is an overview of the CPU32. For detailed information concerning CPU operation, refer to the CPU32 Reference Manual (CPU32RM/AD) ...
Page 102
... The CPU32 has eight 32-bit data registers, seven 32-bit address registers, a 32-bit program counter, separate 32-bit supervisor and user stack pointers, a 16-bit status register, two alternate function code registers, and a 32-bit vector base register (see Figure 5-2 and Figure 5-3). 5-2 Freescale Semiconductor, Inc. DECODE STAGE STAGE C ...
Page 103
... Freescale Semiconductor, Inc Figure 5-2 User Programming Model Figure 5-3 Supervisor Programming Model Supplement MC68331 USER’S MANUAL For More Information On This Product DATA REGISTERS ADDRESS REGISTERS (USP) USER STACK POINTER ...
Page 104
... MSB contain the most significant digit. The ABCD, SBCD, and NBCD instructions operate on two BCD digits packed into a single byte. 5-4 Freescale Semiconductor, Inc. CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
Page 105
... Freescale Semiconductor, Inc MSB BYTE HIGH-ORDER BYTE MIDDLE HIGH BYTE 16-BIT WORD 31 HIGH-ORDER WORD LONG WORD 31 QUAD-WORD 63 62 MSB 31 Figure 5-4 Data Organization in Data Registers 5.2.2 Address Registers Each address register and stack pointer is 32 bits wide and holds a 32-bit address. Ad- dress registers cannot be used for byte-sized operands ...
Page 106
... The MOVEC instruction is used to transfer val- ues to and from the alternate function code registers. This is a long-word transfer; the upper 29 bits are read as zeros and are ignored when written. 5-6 Freescale Semiconductor, Inc. CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
Page 107
... Freescale Semiconductor, Inc. 5.2.5 Vector Base Register (VBR) The VBR contains the base address of the 1024-byte exception vector table, consist- ing of 256 exception vectors. Exception vectors contain the memory addresses of rou- tines that begin execution at the completion of exception processing. Refer to 5.9 Exception Processing for more information on the VBR and exception processing. ...
Page 108
... MSB ADDRESS 0 ADDRESS 1 ADDRESS 2 MSB = Most Significant Bit LSB = Least Significant Bit 15 BCD 0 MSD BCD 4 MSD = Most Significant Digit LSD = Least Significant Digit 5-8 Freescale Semiconductor, Inc. BIT DATA 1 BYTE = 8 BITS INTEGER DATA 1 BYTE = 8 BITS 8 7 BYTE 0 LSB BYTE 2 ...
Page 109
... Freescale Semiconductor, Inc. 5.4 Virtual Memory The full addressing range of the CPU32 on the MC68331 is 16 Mbytes in each of eight address spaces. Even though most systems implement a smaller physical memory, the system can be made to appear to have a full 16 Mbytes of memory available to each user program by using virtual memory techniques. ...
Page 110
... However, Freescale reserves the right to use all current- ly unimplemented instruction operation codes for future M68000 core enhancements. 5-10 Freescale Semiconductor, Inc. — Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST) — Call Module, Return Module — ...
Page 111
... Freescale Semiconductor, Inc. Table 5-1 Instruction Set Summary Instruction Syntax ABCD Dn, Dn– (An), – (An) ADD Dn, <ea> <ea>, Dn ADDA <ea>, An ADDI #<data>, <ea> ADDQ #<data>, <ea> ADDX Dn, Dn– (An), – (An) AND <ea>, Dn Dn, <ea> ANDI #<data>, <ea> ANDI to CCR #<data>, CCR 1 #<data>, SR ANDI to SR ASL Dn, Dn #<data>, Dn <ea> ASR Dn, Dn #<data>, Dn < ...
Page 112
... MOVE USP, An MOVE USP An, USP 1 MOVEC MOVEM list, <ea> <ea>, list MOVEP Dn MOVEQ #<data> Rn, <ea> MOVES <ea>, Rn MULS/MULU <ea>, Dn <ea>, Dl <ea> NBCD 5-12 Freescale Semiconductor, Inc. Operand Size 64/ 32/32 32 32 none ...
Page 113
... Freescale Semiconductor, Inc. Table 5-1 Instruction Set Summary (Continued) Instruction Syntax NEG <ea> NEGX <ea> NOP none NOT <ea> OR <ea>, Dn Dn, <ea> ORI #<data>, <ea> ORI to CCR #<data>, CCR 1 #<data>, SR ORI to SR PEA <ea> 1 none RESET ROL Dn, Dn #<data>, Dn <ea> ROR Dn, Dn #<data>, Dn <ea> ROXL Dn, Dn #<data>, Dn<ea> ROXR Dn, Dn #<data>, Dn <ea> ...
Page 114
... Results can be rounded with a round- to-nearest algorithm. 5.9 Exception Processing Exception processing is a special condition that preempts normal processing. Excep- tion processing is the transition from normal mode program execution to execution of a routine that deals with an exception. 5-14 Freescale Semiconductor, Inc. Operand Size none none 16, 32 none none < ...
Page 115
... Freescale Semiconductor, Inc. 5.9.1 Exception Vectors An exception vector is the address of a routine that handles an exception. The vector base register (VBR) contains the base address of a 1024-byte exception vector table, which consists of 256 exception vectors. Sixty-four vectors are defined by the proces- sor, and 192 vectors are reserved for user definition as interrupt vectors. Except for the reset vector, each vector in the table is one long word in length ...
Page 116
... TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause excep- tions during normal execution. Illegal instructions, instruction fetches from odd ad- dresses, word or long-word operand accesses from odd addresses, and privilege violations also cause internal exceptions. 5-16 Freescale Semiconductor, Inc. Table 5-2 Exception Vector Assignments Vector Offset Dec Hex ...
Page 117
... Freescale Semiconductor, Inc. Sources of external exception include interrupts, breakpoints, bus errors, and reset re- quests. Interrupts are peripheral device requests for processor action. Breakpoints are used to support development equipment. Bus error and reset are used for access con- trol and processor restart. ...
Page 118
... AC and DC parametric mismatches, and restrictions on cable length) are mini- mized. TARGET SYSTEM Figure 5-7 Common In-Circuit Emulator Diagram 5-18 Freescale Semiconductor, Inc. IN-CIRCUIT EMULATOR TARGET MCU CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www ...
Page 119
... Freescale Semiconductor, Inc. TARGET SYSTEM Figure 5-8 Bus State Analyzer Configuration 5.10.2.1 Enabling BDM Accidentally entering BDM in a non-development environment can lock up the CPU32 when the serial command interface is not available. For this reason, BDM is enabled during reset via the breakpoint (BKPT) signal. ...
Page 120
... A double bus fault during initial stack pointer/program counter (SP/PC) fetch sequence is distinguished by a value of $FFFFFFFF in the current instruction PC other time will the processor write an odd value into this register. 5-20 Freescale Semiconductor, Inc. Table 5-4 Polling the BDM Entry Source ATEMP[31:16] SSW* $0000 ...
Page 121
... Freescale Semiconductor, Inc. 5.10.2.4 BDM Commands Commands consist of one 16-bit operation word and can include one or more 16-bit extension words. Each incoming word is read assembled by the serial interface. The microcode routine corresponding to a command is executed as soon as the com- mand is complete. Result operands are loaded into the output shift register to be shift- ed out as the next command is read ...
Page 122
... Figure 5 block diagram of the interface. The BKPT signal becomes the serial clock (DSCLK); serial input data (DSI) is received on IFETCH, and serial output data (DSO) is transmitted on IPIPE. 5-22 Freescale Semiconductor, Inc. CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
Page 123
... Freescale Semiconductor, Inc. CPU STATUS EXECUTION UNIT SYNCHRONIZE MICROSEQUENCER Figure 5-9 Debug Serial I/O Block Diagram The serial interface uses a full-duplex synchronous protocol similar to the serial pe- ripheral interface (SPI) protocol. The development system serves as the master of the serial link since it is responsible for the generation of DSCLK. If DSCLK is derived from the CPU32 system clock, development system serial logic is unhindered by the oper- ating frequency of the target processor ...
Page 124
... CPU32 function code outputs are augmented by two supplementary signals to monitor the instruction pipeline. The instruction pipe (IPIPE) output indicates the start of each new instruction and each mid-instruction pipeline advance. The instruction fetch 5-24 Freescale Semiconductor, Inc. DATA FIELD Figure 5-10 BDM Serial Data Word Table 5-6 CPU Generated Message Encoding ...
Page 125
... Freescale Semiconductor, Inc. (IFETCH) output identifies the bus cycles in which the operand is loaded into the in- struction pipeline. Pipeline flushes are also signaled with IFETCH. Monitoring these two signals allows a bus analyzer to synchronize itself to the instruction stream and monitor its activity. 5.10.4 On-Chip Breakpoint Hardware An external breakpoint input and on-chip breakpoint hardware allow a breakpoint trap on any memory access ...
Page 126
... Freescale Semiconductor, Inc. CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com MC68331 USER’S MANUAL ...
Page 127
... Freescale Semiconductor, Inc. SECTION 6QUEUED SERIAL MODULE This section is an overview of queued serial module (QSM) function. Refer to the QSM Reference Manual (QSMRM/AD) for complete information about the QSM. 6.1 General The QSM contains two serial interfaces, the queued serial peripheral interface (QSPI) and the serial communication interface (SCI) ...
Page 128
... System software must stop the QSPI and SCI before asserting STOP to prevent data corruption and simplify restart. Disable both SCI receiver and transmitter after trans- fers in progress are complete. Halt the QSPI by setting the HALT bit in SPCR3 and 6-2 Freescale Semiconductor, Inc. QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
Page 129
... Freescale Semiconductor, Inc. then setting STOP after the HALTA flag is set. Refer to SECTION 4 SYSTEM INTE- GRATION MODULE for more information about low-power operation. 6.2.1.2 Freeze Operation The freeze (FRZ[1:0]) bits in the QSMCR are used to determine what action is taken by the QSM when the IMB FREEZE signal is asserted. FREEZE is asserted when the CPU enters background debugging mode. At the present time, FRZ0 has no effect ...
Page 130
... PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes the SPI serial clock SCK. 2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 set), in which case it becomes SCI serial output TXD and DDRQS has no effect. 6-4 Freescale Semiconductor, Inc. Table 6-1 QSM Pin Function DDRQS Bit Bit State ...
Page 131
... Freescale Semiconductor, Inc. 6.3 Queued Serial Peripheral Interface The queued serial peripheral interface (QSPI) communicates with external devices through a synchronous serial bus. The QSPI is fully compatible with SPI systems found on other Freescale products, but has enhanced capabilities. The QSPI can per- form full duplex three-wire or half duplex two-wire transfers. A variety of transfer rate, clocking, and interrupt-driven communication options are available ...
Page 132
... The programmer's model for the QSPI consists of the QSM global and pin control reg- isters, four QSPI control registers (SPCR[0:3]), a status register (SPCR), and the 80- byte QSPI RAM. Registers and RAM can be read and written by the CPU. Refer to APPENDIX D REG- ISTER SUMMARY for register bit and field definitions. 6-6 Freescale Semiconductor, Inc. 4 DONE ADDRESS REGISTER 4 ...
Page 133
... Freescale Semiconductor, Inc. 6.3.1.1 Control Registers Control registers contain parameters for configuring the QSPI and enabling various modes of operation. The CPU has read and write access to all control registers, but the QSM has read-only access to all bits except the SPE bit in SPCR1. Control regis- ters must be initialized before the QSPI is enabled to ensure defined operation ...
Page 134
... QSPI application. When used for QSPI functions, the MOSI, MI- SO, and SS pins should have pull-up resistors. Table 6-2 shows QSPI input and output pins and their functions. 6-8 Freescale Semiconductor, Inc. QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
Page 135
... Freescale Semiconductor, Inc. Table 6-2 QSPI Pin Function Pin/Signal Name Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Slave Select Peripheral Chip Select 0 6.3.4 QSPI Operation The QSPI uses a dedicated 80-byte block of static RAM accessible by both the QSPI and the CPU to perform queued operations. The RAM is divided into three segments. ...
Page 136
... Any data to be transmitted should be written into transmit RAM before the QSPI is enabled. During wraparound operation, data for sub- sequent transmissions can be written at any time. 6-10 Freescale Semiconductor, Inc. QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
Page 137
... Freescale Semiconductor, Inc. CPU INITIALIZES QSM GLOBAL REGISTERS CPU INITIALIZES QSM PIN REGISTERS CPU INITIALIZES QSPI CONTROL REGISTERS CPU INITIALIZES CPU ENABLES QSPI Figure 6-4 Flowchart of QSPI Initialization Operation MC68331 USER’S MANUAL For More Information On This Product, BEGIN INITIALIZATION OF QSPI BY THE CPU ...
Page 138
... Figure 6-5 Flowchart of QSPI Master Operation (Part 1) 6-12 Freescale Semiconductor, Inc. QSPI CYCLE BEGINS (MASTER MODE QSPI YES DISABLED ? NO HAS NEWQP YES WORKING QUEUE POINTER CHANGED TO NEWQP BEEN WRITTEN ? NO READ COMMAND CONTROL AND TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS ASSERT PERIPHERAL ...
Page 139
... Freescale Semiconductor, Inc. QSPI CYCLE BEGINS (SLAVE MODE QSPI DISABLED HAS NEWQP BEEN WRITTEN READ TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS IS SLAVE SELECT PIN ASSERTED EXECUTE SERIAL TRANSFER WHEN SCK RECEIVED STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS ...
Page 140
... Figure 6-5 Flowchart of QSPI Master Operation (Part 3) 6-14 Freescale Semiconductor, Inc. B1 WRITE QUEUE POINTER TO CPTQP STATUS BITS IS CONTINUE YES BIT ASSERTED ? NO NEGATE PERIPHERAL CHIP-SELECT(S) IS DELAY YES AFTER TRANSFER EXECUTE PROGRAMMED DELAY ASSERTED ? NO EXECUTE STANDARD DELAY C QUEUED SERIAL MODULE For More Information On This Product, Go to: www ...
Page 141
... Freescale Semiconductor, Inc QSPI DISABLED HAS NEWQP BEEN WRITTEN READ TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS IS SLAVE SELECT PIN ASSERTED EXECUTE SERIAL TRANSFER WHEN SCK RECEIVED STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS WRITE QUEUE POINTER TO CPTQP STATUS BITS ...
Page 142
... IS THIS THE LAST COMMAND IN THE QUEUE ? NO INCREMENT WORKING QUEUE POINTER 6 IS HALT OR FREEZE ASSERTED ? NO A2 Figure 6-6 Flowchart of QSPI Slave Operation (Part 2) 6-16 Freescale Semiconductor, Inc. YES ASSERT SPIF STATUS FLAG IS INTERRUPT ENABLE BIT SPIFIE ASSERTED ? NO IS WRAP ENABLE BIT ASSERTED ? NO DISABLE QSPI A1 ...
Page 143
... Freescale Semiconductor, Inc. Normally, the SPI bus performs synchronous bidirectional transfers. The serial clock on the SPI bus master supplies the clock signal (SCK) to time the transfer of data. Four possible combinations of clock phase and polarity can be specified by the CPHA and CPOL bits in SPCR0. ...
Page 144
... Writing a value to the DTL field in SPCR1 specifies a delay period. The DT bit in command RAM determines whether the standard delay period ( the specified delay pe- 6-18 Freescale Semiconductor, Inc. System Clock Baud Rate Desired DSCKL ...
Page 145
... Freescale Semiconductor, Inc. riod ( used. The following expression is used to calculate the delay: Delay after Transfer = ----------------------------------------------------------------- - System Clock Frequency where DTL equals {1, 2, 3,..., 255}. A zero value for DTL causes a delay-after-transfer value of 8192/system clock. Standard Delay after Transfer Adequate delay between transfers must be specified for long data streams because the QSPI requires time to load a transmit RAM entry for transfer ...
Page 146
... Because the BITSE option is not available in slave mode, the BITS field specifies the number of bits to be transferred for all transfers in the queue. When the number of bits 6-20 Freescale Semiconductor, Inc. QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
Page 147
... Freescale Semiconductor, Inc. designated by BITS has been transferred, the QSPI stores the working queue pointer value in CPTQP, increments the working queue pointer, and loads new transmit data from transmit RAM into the data serializer. The working queue pointer address is used the next time PCS0/SS is asserted, unless the CPU writes to NEWQP first. ...
Page 148
... Changing the value of SCI control bits during a transfer operation may disrupt opera- tion. Before changing register values, allow the SCI to complete the current transfer, then disable the receiver and transmitter. 6-22 Freescale Semiconductor, Inc. QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
Page 149
... Freescale Semiconductor, Inc. TRANSMITTER BAUD RATE CLOCK H ( GENERATOR 15 SCCR1 (CONTROL REGISTER 1) TDRE TC SCI Rx SCI INTERRUPT REQUESTS REQUEST Figure 6-7 SCI Transmitter Block Diagram MC68331 USER’S MANUAL For More Information On This Product, (WRITE-ONLY) SCDR Tx BUFFER 10 (11) - BIT ...
Page 150
... RECEIVER BAUD RATE CLOCK RxD 6 15 SCCR1 (CONTROL REGISTER 1) SCI Tx SCI INTERRUPT REQUESTS 6-24 Freescale Semiconductor, Inc. 16 DATA PIN BUFFER RECOVERY PARITY DETECT WAKEUP LOGIC 0 15 SCSR (STATUS REGISTER) REQUEST Figure 6-8 SCI Receiver Block Diagram QUEUED SERIAL MODULE For More Information On This Product, Go to: www ...
Page 151
... Freescale Semiconductor, Inc. 6.4.1.2 Status Register The SCI status register (SCSR) contains flags that show SCI operating conditions. These flags are cleared either by SCI hardware read/write sequence. In gen- eral, flags are cleared by reading the SCSR, then reading (receiver status bits) or writ- ing (transmitter status bits) the SCDR ...
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... SCI control register zero (SCCR0). Baud clock is derived from the MCU system clock by a modulus counter. Writing a value of zero to SCBR disables the baud rate generator. Baud clock rate is calculated as follows: 6-26 Freescale Semiconductor, Inc. Table 6-5 Serial Frame Formats 10-Bit Frames Data ...
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... Freescale Semiconductor, Inc. System Clock SCI Baud Clock Rate = ----------------------------------- - where SCBR is in the range {1, 2, 3,..., 8191}. The SCI receiver operates asynchronously. An internal clock is necessary to synchro- nize with an incoming data stream. The SCI baud clock generator produces a receive time (RT) sampling clock with a frequency 16 times that of the SCI baud clock. The SCI determines the position of bit boundaries from transitions within the received waveform, and adjusts sampling points to the proper positions within the bit period ...
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... SCCR1. Service routines can load the last byte of data in a sequence into the TDR, then terminate the transmission when a TDRE interrupt occurs. 6-28 Freescale Semiconductor, Inc. QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
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... Freescale Semiconductor, Inc. 6.4.3.6 Receiver Operation The receiver enable (RE) bit in SCCR1 enables ( and disables ( the transmitter. The receiver contains a receive serial shifter and a parallel receive data register (RDR) located in the SCI data register (SCDR). The serial shifter cannot be directly accessed by the CPU. The receiver is double-buffered, allowing data to be held in RDR while other data is shifted in ...
Page 156
... RWU and wakes up. The byte is received normally, trans- ferred to register RDR, and the RDRF flag is set. If software does not recognize the address, it can set RWU and put the receiver back to sleep. Address-mark wakeup al- 6-30 Freescale Semiconductor, Inc. QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
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... Freescale Semiconductor, Inc. lows idle time between frames and eliminates idle time between transmissions. How- ever, there is a loss of efficiency because of an additional bit-time per frame. 6.4.3.9 Internal Loop The LOOPS bit in SCCR1 controls a feedback path on the data serial shifter. When LOOPS is set, SCI transmitter output is fed back into the receive serial shifter. TXD is asserted (idle line) ...
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... Clear the transmitter data register empty (TDRE) and transmit complete (TC) indicators by reading the serial communication interface status reg- ister (SCSR Write transmit data to the serial communication data register (SCDR). 6-32 Freescale Semiconductor, Inc. QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com MC68331 USER’S MANUAL ...
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... Freescale Semiconductor, Inc. SECTION 7GENERAL-PURPOSE TIMER This section is an overview of GPT function. Refer to the GPT Reference Manual (GP- TRM/AD) for complete information about the GPT module. 7.1 General The 11-channel general-purpose timer (GPT) is used in systems where a moderate level of CPU control is required. The GPT consists of a capture/compare unit, a pulse accumulator, and two pulse-width modulators ...
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... MCU. Refer to APPENDIX D REGISTER SUMMARY for a GPT address map and register bit/field descriptions. SECTION 4 SYSTEM INTEGRATION MODULE contains more information about how the state of MM affects the system. 7-2 Freescale Semiconductor, Inc. CAPTURE/COMPARE UNIT PULSE ACCUMULATOR PRESCALER PWM UNIT BUS INTERFACE ...
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... Freescale Semiconductor, Inc. 7.3 Special Modes of Operation The GPT module configuration register (GPTMCR) module configuration register (GPTMCR) is used to control special GPT operating modes. These include low-power stop mode, freeze mode, single-step mode, and test mode. Normal GPT operation can be polled or interrupt-driven. Refer to 7.4 Polled and Interrupt-Driven Operation for more information ...
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... If a new event occurs between the time that the register is read and the time that it is written, the as- sociated flag is not cleared. 7-4 Freescale Semiconductor, Inc. Table 7-1 GPT Status Flags Register Assignment ...
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... Freescale Semiconductor, Inc. 7.4.2 GPT Interrupts The GPT has 11 internal sources that can cause it to request interrupt service (refer to Table 7-2). Setting bits in TMSK1 and TMSK2 enables specific interrupt sources. TMSK1 and TMSK2 are 8-bit registers that can be addressed individually or as one 16-bit register. The registers are initialized to zero at reset. For each bit in TMSK1 and TMSK2 there is a corresponding bit in TFLG1 and TFLG2 in the same bit position ...
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... Pins OC2, OC3, and OC4 are asso- ciated with a specific output compare function. The OC1 function can affect the output of all compare pins. If the OC1 pin is not needed for an output compare function it can 7-6 Freescale Semiconductor, Inc. GENERAL-PURPOSE TIMER For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
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... Freescale Semiconductor, Inc. be used to output the clock selected for the timer counter register. Any of these pins can also be used for general-purpose I/O. Refer to 7.8.3 Output Compare Functions for more information. 7.5.4 Pulse Accumulator Input Pin (PAI) The PAI pin connects a discrete signal to the pulse accumulator for timed or gated pulse accumulation ...
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... The prescaler can be read at any time. In freeze mode the prescaler can also be writ- ten. Word accesses must be used to ensure coherency. If coherency is not needed byte accesses can be used. The prescaler value is contained in bits [8:0] while bits [15:9] are unimplemented and are read as zeros. 7-8 Freescale Semiconductor, Inc. GENERAL-PURPOSE TIMER For More Information On This Product, Go to: www.freescale.com MC68331 ...
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... Freescale Semiconductor, Inc. SYSTEM CLOCK DIVIDER PCLK SYNCHRONIZER AND PIN DIGITAL FILTER Figure 7-2 Prescaler Block Diagram Multiplexer outputs (including the PCLK signal) can be connected to external pins) can be connected to external pins. The CPROUT bit in the TMSK2 register configures the OC1 pin to output the TCNT clock and the PPROUT bit in the PWMC register config- ures the PWMA pin to output the PWMC clock ...
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... COMPARATOR = TOC2 (HI) TOC2 (LO) 16-BIT COMPARATOR = TOC3 (HI) TOC3 (LO) 16-BIT COMPARATOR = TOC4 (HI) TOC4 (LO) 16-BIT COMPARATOR = TI4/O5 (HI) TI4/O5 (LO) 16-BIT LATCH Figure 7-3 Capture/Compare Unit Block Diagram 7-10 Freescale Semiconductor, Inc. TCNT (HI) TCNT (LO) 16-BIT FREE-RUNNING COUNTER CPR0 TFLG1 CLK IC1F CLK IC2F CLK IC3F CFORC OC1F ...
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... Freescale Semiconductor, Inc. 7.8.1 Timer Counter The timer counter (TCNT) is the key timing component in the capture/compare unit. The timer counter is a 16-bit free-running counter that starts counting after the proces- sor comes out of reset. The counter cannot be stopped during normal operation. After reset, the GPT is configured to use the system clock divided by four as the input to the counter ...
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... Each GPT output compare pin has an associated 16-bit compare register and a 16-bit comparator. Each output compare function has an associated status flag, and can cause the GPT to make an interrupt service request. Output compare logic is designed to prevent false compares during data transition times. 7-12 Freescale Semiconductor, Inc. (PH1) $0101 TCNT Figure 7-4 Input Capture Timing Example ...
Page 171
... Freescale Semiconductor, Inc. When the programmed content of an output compare register matches the value in TCNT, an output compare status flag (OCxF) bit in TFLG1 is set. If the appropriate in- terrupt enable bit (OCxI) in TMSK1 is set, an interrupt request is made when a match occurs. Refer to 7.4.2 GPT Interrupts for more information. ...
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... PCLKS bits show the state of the PAI and PCLK pins. The PAI pin can also be used for general-purpose input. The logic state of the PAIS bit in PACTL shows the state of the pin. 7-14 Freescale Semiconductor, Inc. GENERAL-PURPOSE TIMER For More Information On This Product, Go to: www.freescale.com MC68331 USER’ ...
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... Freescale Semiconductor, Inc. SYNCHRONIZER PAI & DIGITAL FILTER PACTL PCLK TCNT OVERFLOW MUX CAPTURE/COMPARE CLK PRESCALER 512 Figure 7-5 Pulse Accumulator Block Diagram 7.11 Pulse-Width Modulation Unit The pulse-width modulation (PWM) unit has two output channels, PWMA and PWMB. A single clock output from the prescaler multiplexer drives a 16-bit counter that is used to control both channels ...
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... During reset, the GPT is configured to use the system clock divided by two to drive the counter. Initialization software can reconfigure the counter to use one of seven prescaler outputs or an external clock input from the PCLK pin. 7-16 Freescale Semiconductor, Inc. 16-BIT DATA BUS PWMA REGISTER PWMB REGISTER ...
Page 175
... Freescale Semiconductor, Inc. The PWM count register (PWMCNT) can be read at any time without affecting its val- ue. A read must be a word access to ensure coherence, but byte accesses can be made if coherence is not needed. The counter is cleared to $0000 during reset and is a read-only register except in freeze or test mode. ...
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... F1A and F1B bits in PWMC are driven out on the corresponding PWM pins when normal PWM operation is disabled. When read, the F1A and F1B bits reflect the states of the PWMA and PWMB pins. 7 7-18 Freescale Semiconductor, Inc. GENERAL-PURPOSE TIMER For More Information On This Product, Go to: www.freescale.com MC68331 ...
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... Freescale Semiconductor, Inc. APPENDIX A ELECTRICAL CHARACTERISTICS This appendix contains electrical specification tables and reference timing diagrams. Table A-1 Maximum Ratings Num 1 Supply Voltage Input Voltage 3 Instantaneous Maximum Current Single pin limit (applies to all pins) 4 Operating Maximum Current Digital Input Disruptive Current ...
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... LPSTOP, External clock, maxi f 4 Clock Synthesizer Operating Voltage 5 V DDSYN VCO on, maximum f External Clock, maximum f LPSTOP, VCO off V 6 Power Dissipation A-2 Freescale Semiconductor, Inc. Rating Supply Current sys Supply Current sys sys powered down DD Rating Supply Current sys Supply Current ...
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... Freescale Semiconductor, Inc. Table A-3 Thermal Characteristics Num 1 Thermal Resistance Plastic 132-Pin Surface Mount Plastic 144-Pin Surface Mount Thin Plastic 144-Pin Surface Mount NOTES: The average chip-junction temperature (T where T = Ambient Temperature Package Thermal Resistance, Junction-to-Ambient, C INT P = Power Dissipation on Input and Output Pins — User Determined ...
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... Noise injected into the PLL circuitry via V oscillator frequency increase the C straint on control system operation, this parameter should be measured during functional testing of the final system. A-4 Freescale Semiconductor, Inc. Table A-4a 20.97 MHz Clock Control Timing (V and V = 5.0 Vdc 5 ...
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... Freescale Semiconductor, Inc. Table A-5 16.78 MHz DC Characteristics (V and V DD Num Characteristic 1 Input High Voltage 2 Input Low Voltage 1 3 Input Hysteresis 2 4 Input Leakage Current High Impedance (Off-State) Leakage Current CMOS Output High Voltage I = – ...
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... LPSTOP, 32.768 kHz crystal, VCO off (STSIM = 0) 32.768 kHz crystal Power Dissipation Input Capacitance 2 17 Load Capacitance Group 1 I/O Pins and CLKOUT, FREEZE/QUOT, IPIPE A-6 Freescale Semiconductor, Inc. Table A-5a 20.97 MHz DC Characteristics (V and V = 5.0 Vdc 5 DDSYN SS Characteristic 2 Input-only pins 2 All input/output and output pins ...
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... Freescale Semiconductor, Inc. Notes for Tables A–5 and A–5a 1. Applies to: Port E [7:4] — SIZ[1:0], AS, DS Port F [7:0] — IRQ[7:1], MODCLK Port GP [7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1 Port QS [7:0] — TXD, PCS[3:1],ÊPCS0/SS, SCK, MOSI, MISO BKPT/DSCLK, IFETCH, RESET, RXD, TSTME/TSC EXTAL (when PLL enabled) 2. Input-Only Pins: EXTAL, TSTME/TSC, BKPT, RXD ...
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... CLKOUT Low to Data In Invalid (Fast Cycle Hold) 30A CLKOUT Low to Data In High Impedance 31 DSACK[1:0] Asserted to Data In Valid 33 Clock Low to BG Asserted/Negated 35 BR Asserted to BG Asserted (RMC Not Asserted) 37 BGACK Asserted to BG Negated A-8 Freescale Semiconductor, Inc. Table A-6 16.78 MHz AC Timing (V and V = 5.0 Vdc 10 DDSYN SS Characteristic 2 3 ...
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... Freescale Semiconductor, Inc. Table A-6 16.78 MHz AC Timing, (Continued) (V and V DD DDSYN Num Characteristic 39 BG Width Negated 39A BG Width Asserted 46 R/W Width Asserted (Write or Read) 46A R/W Width Asserted (Fast Write or Read Cycle) 47A Asynchronous Input Setup Time BR, BGACK, DSACK[1:0], BERR, AVEC, HALT 47B Asynchronous Input Hold Time ...
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... Data Hold from Clock Low (Show) 73 BKPT Input Setup Time 74 BKPT Input Hold Time 75 Mode Select Setup Time 76 Mode Select Hold Time 77 RESET Assertion Time 78 RESET Rise Time A-10 Freescale Semiconductor, Inc. Table A-6a 20.97 MHz AC Timing, (Continued) (V and V = 5.0 Vdc 5 DDSYN SS Characteristic ...
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... Freescale Semiconductor, Inc. Notes for Tables A–6 and A–6a: 1. All AC timing is shown with respect to 20 Minimum system clock frequency is four times the crystal frequency, subject to specified limits. 3. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum allowable t period is reduced when the duty cycle of the external clock signal varies ...
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... NOTE: Timing shown with respect to 20% and 70 EXTAL NOTE: Timing shown with respect to 20% and 70% V Figure A-2 External Clock Input Timing Diagram ECLK NOTE: Timing shown with respect to 20% and 70% V A-12 Freescale Semiconductor, Inc Figure A-1 CLKOUT Output Timing Diagram 4B ...
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... Freescale Semiconductor, Inc. S0 CLKOUT A20–A23 FC0–FC2 SIZ0, SIZ1 R/W DSACK0 DSACK1 D0–D15 BERR HALT BKPT Figure A-4 Read Cycle Timing Diagram MC68331 ELECTRICAL CHARACTERISTICS USER’S MANUAL For More Information On This Product 14A ...
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... CLKOUT A20–A23 FC0–FC2 SIZ0, SIZ1 A R/W DSACK0 DSACK1 D0–D15 BERR HALT BKPT A-14 Freescale Semiconductor, Inc 14A 46 47A Figure A-5 Write Cycle Timing Diagram ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com ...
Page 191
... Freescale Semiconductor, Inc. CLKOUT 6 A0–A23 FC0–FC2 SIZ0, SIZ1 R/W D0–D15 BKPT Figure A-6 Fast Termination Read Cycle Timing Diagram MC68331 ELECTRICAL CHARACTERISTICS USER’S MANUAL For More Information On This Product 14B 46A 27 30 30A 29A ...
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... A Figure A-7 Fast Termination Write Cycle Timing Diagram A-16 Freescale Semiconductor, Inc CLKOUT 6 8 A0–A23 FC0–FC2 SIZ0, SIZ1 14B 46A R/W 24 D0–D15 23 BKPT 73 ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com 68300 FAST WR CYC TIM MC68331 USER’ ...
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... Freescale Semiconductor, Inc CLKOUT A0–A23 D0–D15 AS DS R/W DSACK0 DSACK1 BR BG BGACK Figure A-8 Bus Arbitration Timing Diagram — Active Bus Case MC68331 ELECTRICAL CHARACTERISTICS USER’S MANUAL For More Information On This Product S98 47A to: www.freescale.com 39A ...
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... BGACK Figure A-9 Bus Arbitration Timing Diagram — Idle Bus Case CLKOUT A0–A23 D0–D15 BKPT NOTE: Show cycles can stretch during S42 when bus accesses take longer than two cycles due to wait-state insertion by IMB modules. A-18 Freescale Semiconductor, Inc 47A ...
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... Freescale Semiconductor, Inc CLKOUT 6 A0–A23 FC0–FC2 SIZ0, SIZ1 R/W D0–D15 NOTE: AS and DS timing shown for reference only. Figure A-11 Chip Select Timing Diagram 77 RESET D0–D15 Figure A-12 Reset and Mode Select Timing Diagram MC68331 ELECTRICAL CHARACTERISTICS USER’S MANUAL ...
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... B6 CLKOUT High to FREEZE Asserted/Negated B7 CLKOUT High to IFETCH High Impedance B8 CLKOUT High to IFETCH Valid B9 DSCLK Low Time B10 FREEZE Asserted to IFETCH Valid Notes: 1. All AC timing is shown with respect to 20 A-20 Freescale Semiconductor, Inc 5.0 Vdc 10 Vdc Characteristic Symbol t t DSCCYC t t and 70% V levels unless otherwise noted ...
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... Freescale Semiconductor, Inc. CLKOUT FREEZE BKPT/DSCLK IFETCH/DSI IPIPE/DSO Figure A-13 Background Debugging Mode Timing Diagram — CLKOUT FREEZE IFETCH/DSI Figure A-14 Background Debugging Mode Timing Diagram —Freeze Assertion MC68331 ELECTRICAL CHARACTERISTICS USER’S MANUAL For More Information On This Product Serial Communication ...
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... All AC timing is shown with respect to 20 When the previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low. 3. Address access time = t 4. Chip select access time = t A-22 Freescale Semiconductor, Inc. Table A-8 16.78 MHz ECLK Bus Timing (V = 5.0 Vdc 10 Vdc, T ...
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... Freescale Semiconductor, Inc. CLKOUT 2A ECLK R/W E1 A0–A23 E3 CS E15 D0–D15 E11 D0–D15 NOTE: Shown with ECLK = system clock/8 — EDIV bit in clock synthesizer control register (SYNCR Figure A-15 ECLK Timing Diagram MC68331 ELECTRICAL CHARACTERISTICS USER’S MANUAL For More Information On This Product, ...
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... V /V prior to SCK transitioning between valid point voltages of the data and clock signals can differ, which can corrupt data if slower transition times are used. A-24 Freescale Semiconductor, Inc. Table A-9 QSPI Timing 10 Vdc 200 pF load on all QSPI pins) ...