MPC9653A Integrated Device Technology, Inc., MPC9653A Datasheet

MPC9653A

Manufacturer Part Number

MPC9653A

Description

Manufacturer

Integrated Device Technology, Inc.

Datasheet

1.MPC9653A.pdf (10 pages)

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IDT™ 3.3 V 1:8 LVCMOS PLL Clock Generator

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

3.3 V 1:8 LVCMOS PLL Clock

Generator

Freescale Semiconductor, Inc.

TECHNICAL DATA

3.3 V 1:8 LVCMOS PLL Clock

Generator

zero-delay buffer targeted for high performance low-skew clock distribution in

mid-range to high-performance telecom, networking and computing

applications. With output frequencies up to 125 MHz and output skews less

than 150 ps the device meets the needs of the most demanding clock

applications.

Features

•

Functional Description

MPC9653A requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With

the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency

range of 25 to 62.5 MHz or 50 to 125 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8)

and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The

internal VCO of the MPC9653A is running at either 4x or 8x of the reference clock frequency. The MPC9653A is guaranteed to lock

in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or F

zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.

input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass config-

urations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can

be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock

due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, en-

abling the PLL to recover to normal operation.

MOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For

series terminated transmission lines, each of the MPC9653A outputs can drive one or two traces giving the devices an effective fanout

of 1:16. The device is packaged in a 7x7 mm

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

The MPC9653A is a 3.3 V compatible, 1:8 PLL based clock generator and

The MPC9653A utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

The MPC9653A has a differential LVPECL reference input along with an external feedback input. The device is ideal for use as a

The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected

The MPC9653A is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVC-

1:8 PLL based low-voltage clock generator

32-lead Pb-free Package Available

Supports zero-delay operation

3.3 V power supply

Generates clock signals up to 125 MHz

PLL guaranteed to lock down to 145 MHz, output frequency = 36.25 MHz

Maximum output skew of 150 ps

Differential LVPECL reference clock input

External PLL feedback

Drives up to 16 clock lines

32-lead LQFP packaging

Ambient temperature range 0°C to +70°C

Pin and function compatible to the MPC953 and MPC9653

32-lead LQFP package.

PLL CLOCK GENERATOR

32-LEAD LQFP PACKAGE

MPC9653A

3.3 V LVCMOS 1:8

LOW VOLTAGE

CASE 873A-03

ref

FA SUFFIX

AC SUFFIX

= 36.25 MHz.

Order number: MPC9653A

DATA SHEET

MPC9653A

Rev 3, 08/2004

MPC9653A

529

Related parts for MPC9653A

MPC9653A Summary of contents

Page 1

... VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9653A is running at either the reference clock frequency. The MPC9653A is guaranteed to lock in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or F The MPC9653A has a differential LVPECL reference input along with an external feedback input ...

Page 2

... Figure 1. MPC9653A Logic Diagram MPC9653A Figure 2. MPC9653A 32-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA ÷ QFB ...

Page 3

... Control Default PLL_EN 1 Test mode with PLL bypassed. The reference clock (PCLK) is substituted for the internal VCO output. MPC9653A is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. BYPASS 1 Test mode with PLL and output dividers bypassed. The reference clock (PCLK) is directly routed to the outputs ...

Page 4

... V (DC) specification The MPC9653A is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission . Alternatively, the device drives up to two 50 Ω series terminated transmission lines. The MPC9653A meets line to a termination voltage of V ...

Page 5

... PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/ ÷ 8 PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/ bypass mode, the MPC9653A divides the input reference clock. 5. The input frequency f must match the VCO frequency range divided by the feedback divider ratio FB: f REF 6 ...

Page 6

... CMOS fanout buffers. The external feedback option of the V CC_PLL MPC9653A clock driver allows for its use as a zero-delay buffer. The PLL aligns the feedback clock output edge with the clock MPC9653A input reference edge resulting a near zero delay through the ...

Page 7

... DC current draw, thus the outputs can drive multiple series terminated lines. driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9653A clock driver is effectively doubled due to its capability to drive multiple lines. 7 MPC9653A = [-17ps ...

Page 8

... Figure 7 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9653A output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. ...

Page 9

... MPC9653A CMR = V –1 ÷ GND t (PD) , static phase (PD) offset) Test Reference –T mean| JIT(∅ for a controlled edge with respect Figure 13. I/O Jitter –1/f | JIT(PER Figure 15. Period Jitter MPC9653A 537 ...

Page 10

... MPC9653A PART NUMBERS 3.3 V 1:8 LVCMOS PLL Clock Generator INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 ...

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