AD1819B Analog Devices, AD1819B Datasheet
AD1819B
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AD1819B Summary of contents
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... PHAT STEREO PHAT STEREO GAIN A = ATTENUATE M = MUTE MV = MASTER VOLUME One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 AC’97 SoundPort AD1819B Resolution CS1 CHAIN_IN CHAIN_CLK CS0 MASTER/SLAVE SYNCHRONIZER 16-BIT PGA A/D CONVERTER 16-BIT A/D PGA CONVERTER SAMPLE RATE G ...
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... Hz. The AD1819B also supports irrational V.34 sample rates. Sample Rates and D The AD1819B default mode sets the codec to operate at 48 kHz sample rates. The converter pairs may process left and right channel data at different sample rates. The AD1819B sample rate generator allows the codec to instantaneously change and process sample rates from 7 kHz to 48 kHz with a resolution ...
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... Line Input Selected Min Typ 1 2.83 0.1 0.283 1 2. Min Typ 1.5 22.5 Min Typ 90 90 1.5 46.5 3.0 45 Min Typ –74 –3– AD1819B Max Units V rms V p-p V rms V p-p V rms V p Max Units dB dB Max Units Max Units 0 0. ...
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... AD1819B–SPECIFICATIONS ANALOG-TO-DIGITAL CONVERTERS Parameter Resolution Total Harmonic Distortion (THD) Dynamic Range (–60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) Line to Other Gain Error (Full-Scale Span Relative to Nominal Input Voltage) ...
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... Set Bits PR0 PR1 On) PR1, PR2 REFOUT Off) PR0, PR1, PR3 REFOUT PR4 PR0, PR1, PR4, PR5 PR0, PR1 PR0, PR1, PR2, PR4, PR5 PR0, PR1, PR2, PR3, PR4, PR5 –5– AD1819B Min Typ Max –10 10 – ...
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... AD1819B TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE) Parameter RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Start-Up Delay SYNC Active High Pulsewidth SYNC Low Pulsewidth SYNC Inactive to BIT_CLK Start-Up Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter* BIT_CLK High Pulsewidth BIT_CLK Low Pulsewidth ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1819B features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... XTL_OUT 3 O SDATA_OUT 5 I BIT_CLK 6 O/I* SDATA_IN 8 O SYNC 10 I RESET 11 I *Input if the AD1819B is configured as Slave 1 or Slave 2. Daisy Chain Connections Pin Name LQFP I/O CS0 45 I CS1 46 I CHAIN_IN 47 I CHAIN_CLK 48 I/O* *Output when configured as Master. Input when configured as Slave 1 or Slave 2. ...
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... Analog I/O These signals connect the AD1819B component to analog sources and sinks, including microphones and speakers. Pin Name LQFP I/O PC_BEEP 12 I PHONE_IN 13 I AUX_L 14 I AUX_R 15 I VIDEO_L 16 I VIDEO_R 17 I CD_L 18 I CD_GND 19 I CD_R 20 I MIC1 21 I MIC2 22 I LINE_IN_L ...
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... 0x1C LS/RS (7) X 16-BIT RIM RIM ADC LS ( LS/RS (6) RESET RS (5) 0x1A SYNC LPBK SR0 0x78 0x20 BIT_CLK SR1 0x7A SDATA_OUT SDATA_IN GAM 0x18 LOV 16-BIT OM DAC 0x20 POP GAM 0x18 ROV 16-BIT OM DAC AD1819B OSCILLATORS XTL_OUT XTL_IN REV. 0 ...
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... –11– AD1819B ...
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... Note: Writing any value to this register performs a register reset, which cause all registers to revert to their default values (except 74h, which controls the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement. ID [9:0] Identify Capability. The ID field decodes the capabilities of AD1819B on the following: Bit Function ID0 ...
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... PC Beep Volume Control. The least significant bit represents 3 dB attenuation. This register controls the output from maximum attenuation of –45 dB. The PC Beep is routed to the Left and Right Line outputs even when AD1819B RESET State. This is so that Power-On Self Test (POST) codes can be heard by the user in case of a hardware problem with the PC. ...
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... AD1819B CD Volume (Index 12h RCV [4:0] Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is + –34.5 dB. The default value is 0 dB, mute enabled. ...
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... X dB gain. IM xIM3 . . . xIM0 0 1111 0 0000 1 xxxxx –15– AD1819B ...
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... Ready Bits: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indi- cate the status for the AD1819B subsections. If the bit is a one then that subsection is “ready.” Ready is defined as the subsection able to perform in its nominal state. ...
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... SLOT16 Enable 16-Bit Slots. If your system uses only a single AD1819B, you can ignore the register mask and the slave 1/slave 2 request bits. If you write to this register, write ones to all of the register mask bits. The request bits are read-only. The codec asserts each request bit when the corresponding DAC channel can accept data in the next frame. These bits are snapshots of the codec state taken when the current frame began (effectively, on the rising edge of SYNC), but they also take notice of DAC samples sent in the current frame ...
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... BIT_CLK maximum duration of 16 BIT_CLKs at the beginning of each audio frame. The first 16 bits of the audio frame is defined as the “Tag Phase.” The remainder of the audio frame is the “Data Phase.” The AD1819B uses SYNC to define the beginning of the audio frame. ...
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... If a slot is “tagged” invalid the responsibility of the source of the data, (AD1819B for the input stream, AC’97 controller for the output stream), to stuff all bit positions with 0s during that slot’ ...
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... The AD1819B ignores unused bits example, consider an 8-bit sample stream being played out to one of the AD1819B’s DACs. The first 8-bit positions are pre- sented to the DAC (MSB justified), followed by the next 12 bit positions, which are stuffed with 0s by the AC’97 controller. ...
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... Slot 0: Tag Phase SDATA_IN The AD1819B is capable of sampling data from 7 kHz to 48 kHz with a resolution of 1 kHz. To enable a sample rate other than the default 48 kHz, set the DRQEN bit (Register 74h Bit 11). This allows DAC request bits (these are low active output on the SDATA_IN stream ...
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... Audio input frame Slot 3 is the left channel output of the AD1819B’s input MUX, post-ADC. AD1819B transmits its ADC output data (MSB first), and stuffs the trailing nonvalid bit positions with 0s to fill out its 20-bit time slot. Slot 4: PCM Record Right Channel Audio input frame Slot 4 is the right channel output of the AD1819B’ ...
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... The AC’97 controller should also drive SYNC and SDATA_OUT low after programming AD1819B to this low power “halted” mode. Once AD1819B has been instructed to halt BIT_CLK, a special “wake-up” protocol must be used to bring the AC-Link to the active mode, since normal audio output and input frames can not be communicated in the absence of BIT_CLK. ...
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... AD1819B MULTIPLE CODE CONFIGURATION Setting Up Multiple Codecs The AD1819B may be used with up to two additional AD1819 or AD1819B codecs. In order to configure the codecs as Mas- ter, Slave 1 or Slave 2, refer to the following table. CS1 CS0 Ground The XTAL_IN pin on the Slave Codecs “must” be tied to ground and the CHAIN_IN pin “ ...
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... APPLICATIONS CIRCUITS The AD1819B has been designed to require a minimum amount of external circuitry. The recommended applications circuits are shown in Figures 15–18. Reference designs for the AD1819B are available and may be obtained by contacting your local Analog Devices’ sales representative or authorized distributor. Example shell programs for establishing a communications path between the AD1819B and an ADSP-21xx DSP are also available ...
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... NP0 NP0 RESET SDATA_OUT SDATA_IN SYNC AD1819B BIT_CLK SLAVE 1 CS0 CS1 CHAIN_IN CHAIN_CLK XTAL_OUT XTAL_IN RESET SDATA_OUT SDATA_IN SYNC AD1819B BIT_CLK SLAVE 2 CS0 CS1 CHAIN_IN CHAIN_CLK XTAL_OUT XTAL_IN RESET SDATA_OUT SDATA_IN SYNC BIT_CLK Figure 16. Three Codec System Example –26– ...
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... RESET SDATA_OUT SDATA_IN SYNC BIT_CLK DV DD Figure 17. Two Codec System Example 2.21k * FB 100 100pF 10nF* (mean) 200Hz < FREQUENCY RESPONSE < 5kHz @ –3dB Figure 18. Microphone Input –27– AD1819B FL0 DT0 DIGITAL DR0 CONTROLLER (ADSP-2181) RFS0 SCLK0 SPORT0 AD1819B V REFOUT 100nF MIC1** NC MIC2 ...
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... AD1819B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Terminal LQFP (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC 0.030 (0.75) 0.057 (1.45) 0.276 (7.0) BSC 0.030 (0.75) 0.018 (0.45) 0.053 (1.35) 0.018 (0.45 SEATING PLANE TOP VIEW (PINS DOWN) 0.006 (0.15 0.002 (0.05) 0° MIN 0° – 7° 0.007 (0.18) 0.011 (0.27) 0.0197 (0.5) 0.004 (0.09) BSC 0.006 (0.17) – ...