ADV7170 Analog Devices, ADV7170 Datasheet
ADV7170
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ADV7170 Summary of contents
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... Integrated subcarrier locking to external video source Color signal control/burst signal control Interlaced/noninterlaced operation Complete on-chip video timing generator Programmable multimode master/slave operation Macrovision® AntiTaping Rev. 7.1 (ADV7170 only) Closed captioning support Teletext insertion port (PAL-WST) On-board color bar generation On-board voltage reference 2-wire serial MPU interface (I Single supply ...
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... ADV7170/ADV7171 TABLE OF CONTENTS Specifications..................................................................................... 4 Dynamic Specifications ............................................................... 6 Timing Specifications .................................................................. 7 Timing Diagrams.......................................................................... 9 Absolute Maximum Ratings.......................................................... 10 Package Thermal Performance................................................. 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 General Description ....................................................................... 13 Data Path Description................................................................ 13 Internal Filter Response............................................................. 14 Typical Performance Characteristics ........................................... 15 Features ............................................................................................ 18 Color Bar Generation ................................................................ 18 Square Pixel Mode...................................................................... 18 Color Signal Control ...
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... Changes to Subcarrier Frequency Registers Section .......35 Changes to Figure 45 ......................................................................35 Changes to Figure 82 ......................................................................48 Changes to Ordering Guide...........................................................62 6/02—Starting Rev Rev. B Changes to SPECIFICATIONS .......................................................3 Changes to PACKAGE THERMAL PERFORMANCE section...9 Appendix 9—Recommended Register Values ........................49 Appendix 10—Output Waveforms ...........................................51 Outline Dimensions........................................................................61 Ordering Guide ...........................................................................62 Rev Page ADV7170/ADV7171 ...
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... ADV7170/ADV7171 SPECIFICATIONS ± 1.235 150 Ω. All specifications T AA REF SET Table 1. Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current, I ...
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... R = 37.5 Ω SET 1041 Ω 262.5 Ω SET L COMP = 0.1 µF , must always be kept below 110° 37.5 Ω); optimum performance obtained DAC current ( 110°C. J Rev Page ADV7170/ADV7171 2 , unless otherwise noted. Min Typ Max 10 ±0.6 ±1 2 0.8 ±1 10 2.4 0 ...
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... ADV7170/ADV7171 DYNAMIC SPECIFICATIONS ± 1.235 150 Ω. All specifications T AA REF SET Table 3. Parameter 3, 4 Differential Gain 3, 4 Differential Phase 3, 4 Differential Gain 3, 4 Differential Phase 3, 4 SNR (Pedestal SNR (Pedestal SNR (Ramp SNR ...
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... Teletext input: TTX = 150 Ω. All specifications SET MIN MAX Conditions After this period the first clock is generated Relevant for repeated start condition , must always be kept below 110°C. J Rev Page ADV7170/ADV7171 2 , unless otherwise noted. Min Typ Max 0 400 0.6 1.3 0.6 0.6 100 ...
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... ADV7170/ADV7171 3 3 1.235 REF SET Table 6. Parameter 3, 4 MPU PORT SCLOCK Frequency SCLOCK High Pulse Width SCLOCK Low Pulse Width Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK Rise Time, t ...
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... Figure 2. MPU Port Timing Diagram Figure 3. Pixel and Control Data Timing Diagram 4 CLOCK 4 CLOCK CYCLES CYCLES Figure 4. Teletext Timing Diagram Rev Page ADV7170/ADV7171 CLOCK 4 CLOCK CYCLES CYCLES ...
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... ADV7170/ADV7171 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Rating V to GND Voltage on Any Digital Input Pin GND − 0 Storage Temperature (T ) −65°C to +150°C S Junction Temperature (T ) 150°C J Lead Temperature (Soldering, 10 sec) 260°C 1 Analog Outputs to GND GND − 0 Analog output short circuit to any power supply or GND can indefinite duration ...
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... TTL Address Input. This signal sets up the LSB of the MPU address. The input resets the on-chip timing generator and sets the ADV7170/ADV7171 into default mode. This is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2 × composite and S-Video out, and DAC B powered on and DAC D powered off. ...
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... ADV7170/ADV7171 Input/ Pin No. Mnemonic Output 35 SCRESET/RTC I 36 TTXREQ O 37 TTX I 44 CLOCK I Description This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It can be configured as a subcarrier reset pin, in which case a low-to-high transition on this pin resets the subcarrier to Field 0. Alternatively, it may be configured as a real-time control (RTC) input ...
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... Y typically has a range 235; Cr and Cb typically have a range of 128 ± 112. However possible to input data from 1 to 254 on Y, Cb, and Cr. The ADV7170/ ADV7171 support PAL ( and NTSC (with and without pedestal) standards. The appropriate SYNC, BLANK , and burst levels are added to the YCrCb data ...
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... ADV7170/ADV7171 INTERNAL FILTER RESPONSE The Y filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended (SSAF) response, a CIF response, and a QCIF response. The UV filter supports several different frequency responses, including four low-pass responses, a CIF response, and a QCIF response that are shown in Table 10 and Table 11 and Figure 6 to Figure 18. ...
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... Rev Page ADV7170/ADV7171 FREQUENCY (MHz) Figure 9. PAL Notch Luma Filter FREQUENCY (MHz) Figure 10. Extended Mode (SSAF) Luma Filter ...
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... ADV7170/ADV7171 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 12. QCIF Luma Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 13. 1.3 MHz Low-Pass Chroma Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 14 ...
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... FREQUENCY (MHz) Figure 18. QCIF Chroma Filter 12 Rev Page ADV7170/ADV7171 ...
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... REAL-TIME CONTROL Together with the SCRESET/RTC pin and Bit MR22 and Bit MR21 of Mode Register 2, the ADV7170/ADV7171 can be used to lock to an external video source. The real-time control mode allows the ADV7170/ADV7171 to automatically alter the subcarrier frequency to compensate for line length variation. ...
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... RTC TIME SLOT: 01 NOT USED IN ADV7170/ADV7171 NOTES PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7170/ADV7171 FSC DDS REGISTER PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD SC BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7170/ADV7171. 2 SEQUENCE BIT ...
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... Register 0 TR0 = The ADV7170/ADV7171 generate H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin, and the F bit is output on the FIELD/ VSYNC pin ...
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... EVEN FIELD F ANALOG VIDEO Figure 23. Timing Mode 0 Data Transitions (Master Mode) VERTICAL BLANK VERTICAL BLANK 318 314 315 316 317 319 Figure 22. Timing Mode 0 (PAL Master Mode) Rev Page ADV7170/ADV7171 DISPLAY DISPLAY 335 336 320 334 ...
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... In this mode the ADV7170/ADV7171 accept horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL). ...
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... Register 0 TR0 = this mode the ADV7170/ADV7171 can generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624 ...
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... VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Mode 2 is shown in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 shows the HSYNC , BLANK , and VSYNC for an even-to-odd field transition relative to the pixel data ...
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... In this mode the ADV7170/ADV7171 accept or generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Mode 3 is shown in Figure 31 (NTSC) and Figure 32 (PAL). ...
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... Figure 33 and Figure 34. The LSB sets either a read or write operation. Logic Level 1 corresponds to a read operation, while Logic Level 0 corre- sponds to a write operation set by setting the ALSB pin of the ADV7170/ADV7171 to Logic Level 0 or Logic Level ...
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... The ADV7170/ADV7171 act as standard slave devices on the bus. The data on the SDATA pin is eight bits long, supporting the 7-bit addresses plus the R/ RW bit. The ADV7170 has 48 subaddresses, and the ADV7171 has 26 subaddresses to enable access to the internal registers. It therefore interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses’ ...
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... Mode Register 0. This register can be read from as well as written to. MR0 BIT DESCRIPTION Output Video Standard Selection (MR01 to MR00) These bits are used to set up the encode mode. The ADV7170/ ADV7171 can be set up to output NTSC, PAL B/D/G/H/I, and PAL M/N standard video. Luminance Filter Control (MR02 to MR04) These bits specify which luma filter selected ...
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... Figure 37. Subaddress Register Map Rev Page ADV7170/ADV7171 ADV7170 SUBADDRESS REGISTER POWER-UP/ SR1 SR0 RESET VALUE 0 0 MODE REGISTER MODE REGISTER MODE REGISTER MODE REGISTER MODE REGISTER ...
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... Closed captioning information can be displayed on an odd field, even field, or both odd and even fields. DAC Control (MR16 to MR13) These bits can be used to power down the DACs. This can be used to reduce the power consumption of the ADV7170/ ADV7171 if any of the DACs are not required in the application. MR06 ...
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... DISABLE 1 ENABLE Genlock Control (MR22 to MR21) These bits control the genlock feature of the ADV7170/ ADV7171. Setting MR21 to a Logic Level 1 configures the SCRESET/RTC pin as an input. Setting MR22 to Logic Level 0 configures the SCRESET/RTC pin as a subcarrier reset input. Therefore, the subcarrier resets to Field 0 following a low-to- high transition on the SCRESET/RTC pin ...
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... Burst Control (MR25) This bit enables the burst information to be switched on and off the video output. Low Power Mode (MR26) This bit enables the lower power mode of the ADV7170/ ADV7171, reducing the DAC current by 45%. Reserved (MR27) A Logic Level 0 must be written to this bit. ...
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... If MR46 is set when the device is in sleep mode, the ADV7170/ADV7171 come out of sleep mode and resume normal operation. Also, if the RESET signal is applied during sleep mode, the ADV7170/ADV7171 come out of sleep mode and resume normal operation. Reserved (MR47) A Logic Level 0 should be written to this bit. ...
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... These bits adjust the position of the HSYNC output relative to the FIELD/ VSYNC output. HSYNC to FIELD Rising Edge Delay (TR15 to TR14) When the ADV7170/ADV7171 are in Timing Mode 1, these bits adjust the position of the HSYNC output relative to the FIELD output rising edge. VSYNC Width (TR15 to TR14) When the ADV7170/ADV7171 are configured in Timing Mode 2, these bits adjust the VSYNC pulse width ...
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... FSC2 FSC1 FSC0 BYTE 1 FSC10 FSC9 FSC8 BYTE 0 FSC18 FSC17 FSC16 FSC26 FSC25 FSC24 Rev Page ADV7170/ADV7171 TR11 TR10 HSYNC WIDTH T TR11 TR10 × PCLK 4 × × ...
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... When this bit is enabled (1), the last six bits of the CGMS data TXO10 TXO9 TXO8 (that is, the CRC check sequence) are calculated internally by the ADV7170/ADV7171. If this bit is disabled (0), the CRC LINE 8 LINE 7 values in the register are output to the CGMS data stream. TXE2 ...
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... C/W15 C/W14 C/W13 C/W15 – C/W10 CGMS/WSS DATA BITS Figure 52. CGMS_WSS Register 1 C/W26 C/W25 C/W24 C/W23 C/W27 – C/W20 CGMS/WSS DATA BITS Figure 53. CGMS_ WSS Register 2 Rev Page ADV7170/ADV7171 TC02 TC01 TC00 PCLK PCLK " " ...
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... The ground plane should encompass all ADV7170/ADV7171 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7170/ADV7171, the analog output traces, and all the digital signal traces leading up to the ADV7170/ ADV7171. The ground plane is the board’s common ground plane. ...
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... The circuit in Figure 55 can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform is guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if a 13.5 MHz clock is required by the MPEG decoder. This guarantees that the Cr and Cb pixel information is input to the ADV7170/ADV7171 in the correct sequence. ...
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... FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Line 21 and Line 284. The ADV7170/ADV7171 use a single buffering method. This means that the closed captioning buffer is only one byte deep; therefore, there is no frame delay in outputting the closed captioning data, unlike other 2-byte deep buffering systems ...
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... If the Bit C/W04 is set to a Logic Level 1, the last six bits, C19 to C14, which comprise the 6-bit CRC check sequence, are calculated automatically on the ADV7170/ADV7171 based on the lower 14 bits (C0 to C13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial ...
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... APPENDIX 4—WIDE SCREEN SIGNALING The ADV7170/ADV7171 support wide screen signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7170/ADV7171 are configured in PAL mode. The WSS data is 14 bits long; the function of each of these bits is as shown below. ...
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... DEL (6.9375 × 10 Thus, 37 TTX bits correspond to 144 clocks (27 MHz), and each bit has a width of nearly four clock cycles. The ADV7170/ ADV7171 use an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal that can be output on the CVBS and Y outputs ...
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... ADV7170/ADV7171 APPENDIX 6—WAVEFORMS NTSC Waveforms (with Pedestal) +130.8 IRE +100 IRE +7.5 IRE 0 IRE –40 IRE +100 IRE +7.5 IRE 0 IRE –40 IRE 963.8mV 286mV p-p 650mV 335.2mV 0mV +100 IRE +7.5 IRE 0 IRE –40 IRE 714.2mV Figure 61. NTSC Composite Video Levels 714.2mV Figure 62. NTSC Luma Video Levels 629 ...
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... Figure 65. NTSC Composite Video Levels 714.2mV BLANK/BLACK LEVEL Figure 66. NTSC Luma Video Levels 694.9mV p-p Figure 67. NTSC Chroma Video Levels 715.7mV BLANK/BLACK LEVEL Figure 68. NTSC RGB Video Levels Rev Page ADV7170/ADV7171 1289.8mV PEAK COMPOSITE REF WHITE 1052.2mV 338mV 52.1mV SYNC LEVEL REF WHITE 1052.2mV ...
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... ADV7170/ADV7171 P AL Waveforms 1284.2mV 1047.1mV 350.7mV 50.8mV 1047mV 350.7mV 50.8mV 989.7mV 300mV p-p 650mV 317.7mV 0mV 1050.2mV 351.8mV 51mV 696.4mV Figure 69. PAL Composite Video Levels 696.4mV Figure 70. PAL Luma Video Levels 672mV p-p Figure 71. PAL Chroma Video Levels 698.4mV Figure 72. PAL RGB Video Levels Rev ...
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... Figure 75. PAL 100% Color Bars, U Levels +505mV BETACAM LEVEL 0mV +467mV BETACAM LEVEL 0mV +350mV SMPTE LEVEL 0mV Rev Page ADV7170/ADV7171 +505mV +423mV +82mV 0mV –82mV –423mV –505mV Figure 76. NTSC 100% Color Bars, No Pedestal V Levels +467mV +391mV +76mV 0mV – ...
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... APPEN DIX 7—OPTIONAL OUTPUT FILTER If an output filter is required for the CVBS, Y, UV, Chroma, and RGB outputs of the ADV7170/ADV7171, the filter shown in Figure 79 can be used. Plots of the filter characteristics are shown in Figure 80. An output filter is not required if the outputs of the ADV7170/ADV7171 are connected to most analog monitors or analog TVs ...
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... APPENDIX 9—RECOMM ENDED REGI The ADV7170/ADV7171 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. In each case, the output is set to composite o/p with all DACs powered up and with the BLANK input control disabled. ...
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... ADV7170/ADV7171 Table 15. PAL 4.43361875 MHz) SC Address 00Hex Mode Register 0 01Hex Mode Register 1 02Hex Mode Register 2 03Hex Mode Register 3 04Hex Mode Register 4 07Hex Timing Register 0 08Hex Timing Register 1 09Hex Subcarrier Frequency Register 0 0AHex Subcarrier Frequency Register 1 0BHex Subcarrier Frequency Register 2 0CHex ...
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... P AL Color B L575 10.0 20.0 30.0 40.0 MICROSECONDS RCE! PRECISION MODE OFF NO FILTERING SYNCHRONOUS Figure 8 4. 100/0/75/ 0 PAL Color Bars Luminance Rev Page ADV7170/ADV7171 40.0 50 SOUND-IN-SYNC O FF HRONO US SYNC = SOURCE FRAMES SELECTED ars 50.0 60.0 70.0 SOUND-IN-SYNC OFF SYNC = A FRAMES SELECTED: 1 ...
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... ADV7170/ADV7171 0.5 0.0 –0.5 L575 10.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL SLOW CLAMP TO 0.00V AT 6.72µs 100.0 0.5 50.0 0.0 0.0 –50.0 0.0 APL = 44.6% 525 LINE NTSC SLOW CLAMP TO 0.00V AT 6.72 µ s 20.0 30.0 40.0 MICROSECONDS PRECISION MODE OFF NO FILTERING SYNCHRONOUS Figure 85. 100/0/75/0 Pal Color Bars Chrominance F1 L76 10.0 20.0 30.0 40.0 MICROSECONDS PRECISION MODE OFF NO FILTERING Figure 86 ...
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... NOISE REDUCTION: 15.05dB APL NEEDS SYNC = SOURCE! 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00V AT 6.72µs Figure 88. 100/7.5/75/7.5 NTSC Color Bars Chrominance Rev Page 30.0 40.0 50.0 MICROSECONDS SYNCHRONOUS SYNC = SOURCE FRAMES SELECTED 30.0 40.0 50.0 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS SYNC = B FRAMES SELECTED ADV7170/ADV7171 60.0 60.0 ...
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... ADV7170/ADV7171 APL = 39.6% SOUND IN SYNC OFF APL = 45.1% –Q SETUP 7. 75% 100 Figure 89. PAL Vector Plot R– 100% 75 Figure 90. NTSC Vector Plot Rev Page SYSTEM LINE L608 ANGLE (DEG) 0.0 GAIN × 1.000 0.000dB 625 LINE PAL BURST FROM SOURCE DISPLAY +V AND – ...
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... DIFFERENTIAL PHASE (DEG) MIN = 0.02 MAX = 0.14 p-p = 0.16 0.00 0.03 –0.02 0.20 0.15 0.10 0.05 –0.00 –0.05 –0.10 1ST 2ND 3RD Figure 92. NTSC Differential Gain and Phase Measurement Rev Page FCC COLOR BAR 0.2 0.1 0.2 0.1 –0.2 –0.3 0.0 0.0 –0.1 –0.3 –0 MAGENTA RED BLUE BLACK MOD 5 STEP 0.11 0.07 0.05 0.14 0.10 0.10 4TH 5TH 6TH ADV7170/ADV7171 ...
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... ADV7170/ADV7171 LUMINANCE NONLINEARITY (NTSC) FIELD = 2 LINE = 21 LUMINANCE NONLINEARITY (%) 99.9 100.4 100.3 100.2 100.1 100.0 99.9 99.8 99.7 99.6 99.5 99.4 99.3 99.2 99.1 99.0 98.9 98.8 98.7 98.6 1ST CHROMINANCE AM PM (NTSC) FULL FIELD (BOTH FIELDS) BANDWIDTH 100Hz TO 500kHz AM NOISE –75.0 PM NOISE –75.0 (0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL) WFM → p-p = 0.2 100.0 99.9 99.9 2ND 3RD ...
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... Figure 96. NTSC SNR Ramp Measurement Rev Page WFM → PEDESTAL NOISE LEVEL = –80.1dB RMS 3.0 4.0 5.0 (MHz) WFM → RAMP SIGNAL NOISE LEVEL = –61.7dB RMS 3.0 4.0 5.0 (MHz) ADV7170/ADV7171 6.0 ...
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... ADV7170/ADV7171 PARADE SMPTE/EBU PAL mV Y(A) 700 600 500 400 300 200 100 0 –100 –200 –300 LIGHTNING L183 YI –274.82 0.93% YI 462.80 –0.50% G 307.54 –0.21% R 156.63 –0.22% CY –262.17 –0.13% COLOR Pk-Pk: B–Y 532.33mV Pk-WHITE: 700.4mV (100%) SETUP –0.01% mV Pb(B) 250 200 150 100 50 0 –50 –100 –150 – ...
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... COMPONENT MULTIBURST LINE = 202 AMPLITUDE (0dB = 100% OF 688.1mV 0.04 –0.02 0.0 –5.0 Y –10.0 0.49 0.99 0.21 0.23 0.0 –5.0 Pb –10.0 0.49 0.99 0.25 0.25 0.0 –5.0 Pr –10.0 0.49 0.99 Figure 100. PAL YUV Multiburst Response Rev Page →Y 82.1 Pb 82.3 Pr 83.3 3.0 4.0 5.0 6.0 (MHz) 683.4mV 668.9mV) –0.05 –0.68 –2.58 –8.05 2.00 3.99 4.79 5.79 –0.78 –2.59 –7.15 1.99 2.39 2.89 –0.77 –2.59 –7.13 1.99 2.39 2.89 (MHz) ADV7170/ADV7171 (dB) ...
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... ADV7170/ADV7171 mV GREEN (A) 700 600 500 400 300 200 100 0 –100 –200 –300 COMPONENT VECTOR SMPTE/EBU, 75 Figure 101. PAL YUV Vector Plot mV BLUE (B) 700 600 500 400 300 200 100 0 –100 –200 –300 Figure 102. PAL RGB Waveforms Rev Page ...
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... SEATING 0.08 MAX PLANE COPLANARITY VIEW A LEAD PITCH VIEW A COMPLIANT TO JEDEC STANDARDS MS-026ACB Figure 104. 44-Lead Thin Plastic Quad Flat Package [TQFP] (SU-44) Dimensions shown in millimeters Rev Page ADV7170/ADV7171 13.45 13.20 SQ 12. 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9.80 PIN 0.45 0.29 LEAD WIDTH 12.00 BSC SQ ...
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... ADV7170KS-REEL −40°C to +85°C 1 ADV7170KSZ −40°C to +85°C ADV7170KSZ-REEL 1 −40°C to +85°C ADV7170KSU −40°C to +85°C ADV7170KSU-REEL −40°C to +85°C 1 ADV7170KSUZ −40°C to +85°C 1 ADV7170KSUZ-REEL −40°C to +85°C ADV7171KS −40°C to +85°C ADV7171KS-REEL − ...
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... NOTES Rev Page ADV7170/ADV7171 ...
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... ADV7170/ADV7171 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...