IDT70V5388 Integrated Device Technology, Inc., IDT70V5388 Datasheet
IDT70V5388
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IDT70V5388 Summary of contents
Page 1
... Port 1 Readback Register Port 1 Mask Register Port 1 Address Decode Port 1 Counter/ Address Register Port 1 CE 0P1 Interrupt INT CE 1P1 Logic CLK P1 MRST 1 IDT70V5388/78 TRST TMS JTAG TCK Controller TDO TDI CLKMBIST MBIST , 64KX18 Memory Array P1 5649 drw 01 JANUARY 2006 DSC-5649/4 ...
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... CE , permits the on-chip circuitry of each port to enter 1 a very low standby power mode. The IDT70V5388/78 provides a wide range of func- Industrial and Commercial Temperature Ranges tions specially designed to facilitate system operations. These include full-boundary, maskable address counters with associated interrupts for each port, mailbox interrupt ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Pin Configuration (4) 09/25/ I/O I/O I/O I/O I I/O I/O I MKRD ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Pin Configuration (2) 09/25/ R/W I ( ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Pin Definitions Port 1 Port 2 (1) ( 0P1 15P1 0P2 15P2 0P3 I/O - I/O I/O - I/O I/O 0P1 17P1 0P2 17P2 0P3 CLK CLK CLK MRST 0P1 1P1 0P2 1P2 0P3 R/W R/W R ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Pin Definitions (con't.) Port 1 Port 2 MKLD MKLD MKLD P1 P2 MKRD MKRD MKRD P1 P2 INT INT INT TMS TRST TCK TDI TDO CLKMBIST GND NOTE for IDT70V5378. 15 Port 3 Port 4 Counter Mask Register Load Input ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Truth Table I—Read/Write and Enable Control OE CE CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ NOTES: 1. "H" "L" " ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Address Counter and Counter-Mask Control Operational Table (Any Port) (1,2) MRST CNTRST MKLD CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ( NOTES: 1. "X" = "don't care", "H" " ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Absolute Maximum Ratings Symbol Rating Terminal Voltage (2) V TERM with Respect to GND Temperature Under Bias (3) T BIAS T Storage Temperature STG T Junction Temperature Output Current OUT NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter Dynamic Operating Current (All Outputs Disabled, (1) Ports Active MAX Standby Current SB1 (All Ports - TTL ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM AC Test Conditions (V Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT 7 6 ∆ 5 tCD (Typical, ns 3.3V) ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) Symbol Parameter f Maximum Frequency 2 MAX t Clock Cycle Time CYC2 t Clock HIGH Time CH2 t Clock LOW Time CL2 t Address Setup Time SA t Address Hold Time ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) Symbol Interrupt Timing Clock to INT Set Time t SINT Clock to INT Reset Time t RINT Clock to CNTINT Set Time t SCINT Clock to CNTINT Reset Time ...
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... ADDRESS (B2) CE 0(B2 DATA OUT(B2) NOTES Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V5388/78 for this waveform, and are setup for depth expansion in this example. ADDRESS 2. LB UB, OE, and CNTLD = 1(B1) 1(B2) (2) t CYC2 t CL2 ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Timing Waveform of Port A Write to Port B Read CLK "A" R/W "A" ADDRESS "A" MATCH DATA VALID IN"A" t CCS CLK "B" R/W "B" ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Timing Waveform of Read-to-Write-to-Read ( OE Controlled) t CYC2 t t CH2 CL2 CLK LB (3) An ADDRESS DATA IN (1) DATA OUT OE READ NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Timing Waveform of Write with Address Counter Advance t CYC2 t CH2 CLK ADDRESS (3) INTERNAL ADDRESS t t SCLD HCLD CNTLD CNTINC DATA IN WRITE EXTERNAL ADDRESS Timing Waveform of Counter Reset t CYC2 t t CH2 ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Timing Waveform of Master Reset CLK t RS MRST t ROF ALL ADDRESS/ DATA LINES ALL OTHER INPUTS CNTINT INT NOTES: 1. Master Reset will reset the device. For JTAG and MBIST reset please refer to the JTAG Timing specification. ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Timing Waveform of Load and Read Address Counter t CYC2 t t CH2 CL2 CLK SCLD HCLD CNTLD CNTINC t SCINC CNTRD INTERNAL ADDRESS DATA OUT Qx- 1 LOAD EXTERNAL ADDRESS NOTES: 1 ...
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... Address FFFEh is the mailbox location for Port 2 of IDT70V5388. Refer to Truth Table III for mailbox location of other Ports (page 22). 6. Port 1 is configured for a write operation (setting the interrupt) in this example, and Port 2 is configured for a read operation (clearing the interrupt). Ports 1 and 2 are used for an example: any port can set an interrupt to any other port per the operations in Truth Table III (page 22) ...
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... Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT70V5388/78 can also be used in applica- tions requiring expanded width, as indicated in Figure 3. Through combining the control signals, the devices can be grouped as necessary to accommodate applications re- quiring 36-bits or wider ...
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... I/O bus. The INT is reset, or goes HIGH again, in relation to the reading port’s clock signal. Master Reset The IDT70V5388/78 is equipped with an asynchro- nous Master Reset input, which can be asserted indepen- dently of all clock inputs and will take effect per the Master Reset timing waveform on page 18 ...
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... When the CNTRD control is asserted, the IDT70V5388/78 will output the current address stored in the internal counter for that port as noted in the Load and Read Address Counter timing waveform on page 19. The address will be output on the address lines ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Counter-Mask Register Load Counter-Mask STEP 1 Register = FF Load Address STEP 2 Counter = FD Max Address STEP 3 Register Max + 1 STEP 4 Address Register NOTE: 1. The "X's" in this diagram represent the upper bits of the counter for IDT70V5378. ...
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... JTAG operations. Memory Built-In-Test Operations Go-NoGo Testing The IDT70V5388/78 is equipped with a self-test function that can be run by the user as the result of a single instruction, implemented via the JTAG TAP interface. If multiple FourPort devices are used on the same board, all can execute MBIST simultaneously, facilitating board checkout ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM JTAG/BIST TAP Controller Block Diagram MBIST Mode Select Register (MSR) TDI CONTROLLER CLKMBIST Bypass Register (BYR Instruction Register (IR MBIST Result Register (MRR Identification Register (IDR) 391 ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM JTAG Timing Specifications TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = All device outputs except TDO reset the test (JTAG) port without resetting the device, TMS must be held LOW for 5 cycles, or TRST must be held LOW for one cycle. ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Identification Register Definitions Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) NOTE: 1. Device ID for IDT70V5378 is 0x31E. Scan Register Sizes Register Name Instruction (IR) MBIST Mode Select Register (MSR) Bypass (BYR) ...
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... IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Ordering Information IDT XXXXX A 999 Device Power Speed Package Type NOTES: 1. Contact your local sales office for industrial temp. range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. ...