IDT70V3579 Integrated Device Technology, Inc., IDT70V3579 Datasheet
IDT70V3579
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IDT70V3579 Summary of contents
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... Dout0-8_L Dout0-8_R Dout9-17_L Dout9-17_R Dout18-26_L Dout18-26_R Dout27-35_L Dout27-35_R 32K x 36 MEMORY ARRAY Din_L Din_R ADDR_L ADDR_R 1 IDT70V3579S R I/O - I/O 0R 35R CLK R A 14R Counter Address CNTRST R Reg. ...
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... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Description: The IDT70V3579 is a high-speed 32K x 36 bit synchronous Dual- Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times ...
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... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Pin Configuration (1,2,3,4) 12/12/ I 18L I/O I 18R 19L I/O I/O I/O 20R 19R V 20L I/O I/O I/O V 21R 21L 22L DDQL I/O I/O I/O V 23L 22R 23R ...
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... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Pin Configuration (1,2,3,4) 12/12/01 1 I/O 19L 2 I/O 19R 3 I/O 20L 4 I/O 20R V 5 DDQL I/O 21L I/O 8 21R 9 I/O 22L I/O 10 22R 11 V DDQR I/O 13 23L 14 I/O 23R I/O 15 24L 16 I/O 24R V 17 DDQL I/O 19 25L I/O 20 25R I/O 21 26L I/O 22 26R V 23 DDQR ...
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... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Pin Names Left Port Right Port Chip Enables , , R/W R/W Read/Write Enable Output Enable Address 0L 14L 0R 14R I/O - I/O I/O - I/O Data Input/Output 0L 35L 0R 35R CLK CLK Clock L R ADS ...
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... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Truth Table II—Address Counter Control Previous Addr (6) Address Address Used CLK ↑ ↑ ↑ ↑ NOTES: 1. "H" "L" "X" = Don't Care. IH, IL, 2. Read and write operations are controlled by the appropriate setting of R/ ...
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... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM (1) Capacitance (T = +25° 1.0MH ) PQFP ONLY A Z Symbol Parameter Conditions C Input Capacitance IN (3) C Output Capacitance V OUT NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from from ...
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... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE and CE I Dynamic Operating DD L Current (Both Outputs Disabled, (1) Ports Active MAX Standby Current SB1 L (1) (Both Ports - TTL ...
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... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM AC Test Conditions (V Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 50Ω DATA OUT Figure 1. AC Output Test load ∆ ...
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... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing 3.3V ± 150mV 0°C to +70° Symbol Parameter t Clock Cycle Time (Pipelined) CYC2 t Clock High Time (Pipelined) CH2 t Clock Low Time (Pipelined) ...
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... A 0 ADDRESS (B2) CE 0(B2 DATA OUT(B2) NOTES Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3579 for this waveform, and are setup for depth expansion in this example. ADDRESS OE, and ADS = V , R/W, CNTEN, and CNTRST = 1(B1) 1(B2) t CL2 ...
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... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Left Port Write to Pipelined Right Port Read CLK R ADDRESS L MATCH DATA VALID INL t CO CLK R R ADDRESS R MATCH DATA ...
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... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled) t CYC2 t t CH2 CL2 CLK (3) An ADDRESS DATA IN (1) DATA OUT OE READ NOTES: 1 ...
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... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Write with Address Counter Advance t CYC2 t t CH2 CL2 CLK ADDRESS (3) INTERNAL (7) An ADDRESS t t SAD HAD ADS CNTEN DATA IN WRITE EXTERNAL ADDRESS Timing Waveform of Counter Reset ...
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... LOW on CE for one clock cycle will power 0 1 down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT70V3579s for depth expansion configurations. Two cycles are required with CE LOW and CE HIGH to re-activate the outputs. 1 ...
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... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Ordering Information IDT XXXXX A 99 Device Power Speed Package Type NOTE: 1. Contact your local sales office for Industrial temp range in other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. ...
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... IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Datasheet Document History (cont'd) 4/10/01: Added Industrial Temperature Ranges and removed related notes 7/19/01: Page 3 Replaced incorrect BGA package drawing 12/12/01: Page 2, 3 & 4 Added date revision to pin configurations Page 6 Removed industrial temp footnote from table 04 Page 8 & ...