MC12439 Freescale Semiconductor, Inc, MC12439 Datasheet

no-image

MC12439

Manufacturer Part Number
MC12439
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC12439
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
MC12439FN
Manufacturer:
MOT
Quantity:
5 510
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
High Frequency Clock Generator
applications that require both serial and parallel interfaces. Its internal
VCO will operate over a range of frequencies from 400 to 800MHz. The
differential PECL output can be configured to be the VCO frequency
divided by 1, 2, 4, or 8. With the output configured to divide the VCO
frequency by 1, and with a 16.66MHz external quartz crystal used to
provide the reference frequency, the output frequency can be specified in
16.66MHz steps.
Functional Description
oscillator is sent directly to the phase detector. With a 16.66MHz crystal, this provides a reference frequency of 16.66MHz.
Although this data sheet illustrates functionality only for a 16MHz and 16.66MHz crystal, any crystal in the 10–20MHz range can
be used. In addition to the crystal, an LVCMOS input can also be used as the PLL reference. The reference is selected via the
XTAL_SEL input pin.
the serial or parallel interfaces. The output of this loop divider is also applied to the phase detector.
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock.
is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This
divider extends performance of the part while providing a 50% duty cycle.
in 50
inputs to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power
becomes valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority
over the serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs to reduce component count in the
application of the chip.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the
programming section for more information.
programming section for more information.
PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de–assertion of the
PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments.
1/97
Motorola, Inc. 1997
50 to 800MHz Differential PECL Outputs
Minimal Frequency Over–Shoot
Synthesized Architecture
Serial 3–Wire Interface
Parallel Interface for Power–Up
Quartz Crystal Interface
28–Lead PLCC Package
Operates from 3.3V or 5.0V Power Supply
The MC12439 is a general purpose synthesized clock source targeting
The internal oscillator uses the external quartz crystal as the basis of its frequency reference. The output of the reference
The VCO within the PLL operates over a range of 400 to 800MHz. Its output is scaled by a divider that is configured by either
The phase detector and loop filter attempt to force the VCO output frequency to be M times the reference frequency by
The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider
The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0]
The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the
The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16. The power down sequence is clocked by the
25ps Typical Peak–to–Peak Output Jitter
to V CC – 2.0.
1
REV 3
HIGH FREQUENCY PLL
CLOCK GENERATOR
28–LEAD PLCC PACKAGE
MC12439
CASE 776–02
FN SUFFIX

Related parts for MC12439

MC12439 Summary of contents

Page 1

... MOTOROLA SEMICONDUCTOR TECHNICAL DATA High Frequency Clock Generator The MC12439 is a general purpose synthesized clock source targeting applications that require both serial and parallel interfaces. Its internal VCO will operate over a range of frequencies from 400 to 800MHz. The differential PECL output can be configured to be the VCO frequency divided ...

Page 2

... MC12439 V CC FOUT FOUT GND S_CLOCK 26 S_DATA 27 S_LOAD 28 1 PLL–V CC PWR_DOWN 2 FREF_EXT 3 XTAL1 XTAL2 OE P_LOAD M[0] PIN DESCRIPTIONS Pin Name Type Inputs XTAL1, XTAL2 — These pins form an oscillator when connected to an external series–resonant crystal. S_LOAD Int. Pulldown This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this signal is HIGH, thus the data must be stable on the HIGH– ...

Page 3

... 17 M[6:0] N[1:0] Figure 2. MC12439 Block Diagram PROGRAMMING INTERFACE FOUT = 16M, FOUT = 8M, FOUT = 4M and FOUT = 2M for 25 < M < 50 The user can identify the proper M and N values for the desired frequency from the above equations. The four output (1) frequency ranges established by N are 400–800MHz, 200– ...

Page 4

... However the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MC12439 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin ...

Page 5

... HIGH PLOADB DECODE Figure 4. Serial Test Clock Block Diagram Min Typ 2.0 TEST 2.5 TEST FOUT 2.27 FOUT FOUT 1.49 FOUT PLL_V MC12439 FOUT N DIVIDE ( (VIA ENABLE GATE) 7 TEST TEST MUX 0 Max Unit Condition 3.3 to 5.0V 0 3.3 to 5.0V 1 Continuous Current ...

Page 6

... MC12439 AC CHARACTERISTICS ( 3.3 to 5.0V 5%) Symbol Characteristic F MAXI Maximum Input Frequency F MAXO Maximum Output Frequency t LOCK Maximum PLL Lock Time t jitter Cycle–to–Cycle Jitter (Peak–to–Peak) (Note 6 Setup Time t h Hold Time tpw MIN Minimum Pulse Width ...

Page 7

... The difference is purely in the way the devices are characterized result a parallel resonant crystal can be used with the MC12439 with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies ...

Page 8

... It is safe to assume that collecting pulse information in this mode will produce period jitter values somewhat larger than if consecutive cycles (cycle–to–cycle jitter) were measured. All of the jitter data reported on the MC12439 was collected in this manner. 8 N=2 ...

Page 9

... ECL devices. Note that if a larger swing is desired the 12439 could drive a single gate ECLinPS Lite amplifier like the MC100LVEL16. The LVEL16 will speed up the output edge rates and produce a full swing ECL output at 800MHz. 9 MC12439 Spec Limit N=1 600 700 800 ...

Page 10

... MC12439 –N – –L – 0.010 (0.250 – NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM – ...

Page 11

... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 *MC12439/D* 11 MC12439 MC12439/D MOTOROLA ...

Related keywords