MT9123AP Zarlink Semiconductor, MT9123AP Datasheet
MT9123AP
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MT9123AP Summary of contents
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... Copyright 1996-2005, Zarlink Semiconductor Inc. All Rights Reserved. Dual Voice Echo Canceller MT9123AP MT9123AE MT9123APR MT9123AP1 MT9123APR1 Description The MT9123 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to ITU-T G.165 requirements. The MT9123 architecture contains two echo cancellers ...
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... Echo Canceller A and B. MT9123 CONFIG2 CONFIG1 BCLK/C4i F0i Rin 5 Rout Sin 6 Sout 7 VSS VDD 8 MCLK IC1 9 F0od NLP 10 S1/DATA1 11 IC2 S2/DATA2 S3/CS S4/SCLK IC4 IC3 Figure 2 - Pin Connections Description 2 Zarlink Semiconductor Inc. Data Sheet • F0i 25 24 Rout 23 Sout PLCC 22 VDD 21 F0od 20 S1/DATA1 19 S2/DATA2 ...
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... PWRDN Power-down (Input). An active low resets the device and puts the MT9123 into a low-power stand-by mode. 15 IC3 Internal Connection 3 (Output). Must be left unconnected. 16 IC4 Internal Connection 4 (Output). Must be left unconnected. MT9123 Description 3 Zarlink Semiconductor Inc. Data Sheet ...
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... BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit clock. This clock must be synchronous with ENA1, ENA2, ENB1 and ENB2 enable strobes. In ST-BUS operation, C4i pin must be connected to the 4.096 MHz (C4) system clock. MT9123 Description 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Vss. Each echo canceller in the MT9123 has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation. These are explained in the section entitled Echo Canceller Functional States. MT9123 Description Controllerless and Controller. Controllerless mode is intended for 5 Zarlink Semiconductor Inc. Data Sheet ...
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... A Rin b) Extended Delay Configuration (128 ms) Optional -12dB pad PORT 2 Sin echo path Rout Optional -12dB pad Figure 3 - Device Configuration Lsin > Lrin + 20log (DTDT Zarlink Semiconductor Inc. Data Sheet PORT 2 channel A Sin + - Adaptive Filter (128 ms) channel A Rout Optional -12dB pad E.C ...
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... The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation: where 0 < NLPTHR < 1 (dec) The comfort noise injection can be disabled by setting the INJDis bit Control Register 1. MT9123 DTDT = hex(DTDT * 32768) (hex) (dec) TSUP = Lrin + 20log (NLPTHR) 10 NLPTHR = hex(NLPTHR * 32768) (hex) (dec) 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Therefore muting Echo Canceller A causes quiet code to be transmitted on Rout, while muting Echo Canceller B causes quiet code to be transmitted on Sout. MT9123 LINEAR SIGN/ CCITT (G.711) 16 bits MAGNITUDE µ-Law 2’s µ-Law complement A-Law 0000h 80h FFh Table 1 - Quiet PCM Code Assignment 8 Zarlink Semiconductor Inc. Data Sheet A-Law D5h ...
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... MCLK pin. The initialization routines execute for one frame and will set the MT9123 to default register values. MT9123 Functional State (1) 00 Mute (2) 01 Bypass (1,3) 10 Disable Adaptation (3) 11 Enable Adaptation Table 2 - Functional States Control Pins 9 Zarlink Semiconductor Inc. Data Sheet Echo Canceller B S4/ ...
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... In Control Register 1, the Normal configuration can be programmed by setting both BBM and Extended-Delay bits to 0. Back-to-Back configuration can be programmed by setting the BBM bit to 1 and Extended-Delay bit to 0. MT9123 CONFIG2 CONFIGURATION 0 0 (selects Controller Mode Extended Delay Mode 1 0 Back-to-Back Mode 1 1 Normal Mode 10 Zarlink Semiconductor Inc. Data Sheet ...
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... Mode 3. 8 bit companded PCM I/O on timeslots 2 & 3. Includes D & C chan- nel bypass in timeslots 0 & Mode 4. 16 bit 2’s complement linear PCM I/O on timeslots Table 4 - ST-BUS Mode Select 11 Zarlink Semiconductor Inc. Data Sheet PORT2 Sin/Rout Enable Pins ENB2 ENA2 ...
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... LAW = LAW = 0 1111 1111 1000 0000 + Zero 1000 0000 1111 1111 - Zero 0000 0000 0111 1111 0111 1111 0000 0000 Table 6 - Companded PCM 12 Zarlink Semiconductor Inc. Data Sheet Port A-LAW LAW =1 1010 1010 1101 0101 0101 0101 0010 1010 ...
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... Command/Address byte is defined differently for Intel and Motorola/National operations. Refer to the relative timing diagrams of Figures 9 and 10. Receive data is sampled on the rising edge of SCLK while transmit data is clocked out on the falling edge of SCLK. Detailed microport timing is shown in Figure 18 and Figure 19. MT9123 13 Zarlink Semiconductor Inc. Data Sheet ...
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... Set pin LAW to 1or 0 to select A-Law or µ-Law respectively. Set pin FORMAT select Sign-Magnitude or ITU-T format respectively. Set bit NBDis Control Register 2 to disable. Set bit HPFDis Control Register 2 to disable. 14 Zarlink Semiconductor Inc. Data Sheet Controller ...
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... ECA ECA Zarlink Semiconductor Inc. Data Sheet ECB ECB ...
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... ECB Zarlink Semiconductor Inc. Data Sheet ECB ...
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... Note that the two ports are independent so that, for example, PORT1 can operate with 8 bit enable strobes and PORT2 can operate with 16 bit enable strobes. MT9123 ECA ECB bits bits bits bits ECA ECB bits bits bits bits Figure 8 - SSI Operation 17 Zarlink Semiconductor Inc. Data Sheet ...
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... Read/Write 6 bits - Addressing Data 1 bit - Unused DATA INPUT DATA OUTPUT bits - Addressing Data 1 bit - Unused 18 Zarlink Semiconductor Inc. Data Sheet ...
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... Bypass PAD AdaptDis ADDRESS = 01h WRITE/READ VERIFY ADDRESS = 21h WRITE/READ VERIFY 0 NBDis HPFDis MuteS MuteR Zarlink Semiconductor Inc. Data Sheet Power Reset Value 0000 0000 Power Reset Value 0000 0010 Power Reset Value 0000 0000 ...
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... Decision indicator for rapid adaptation convergence. Logic high indicates a rapid convergence state. DTDet Logic high indicates the presence of a double-talk condition. MT9123 Conv Down Active Zarlink Semiconductor Inc. Data Sheet ADDRESS = 02h READ ADDRESS = 22h READ Power Reset Value 0000 0000 ...
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... The default value of 7-0 ). The start of the exponential decay is defined as Step Size (SS) ] where 7-0 =4, then the exponential decay start value is 512 - [NS 2-0 21 Zarlink Semiconductor Inc. Data Sheet Power Reset Value 00h Power Reset Value 00h ...
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... Zarlink Semiconductor Inc. Data Sheet ADDRESS = 0Dh READ ADDRESS = 2Dh READ Power Reset Value N/A 8 ADDRESS = 0Ch READ ADDRESS = 2Ch READ Power Reset Value N/A 0 ADDRESS = 0Fh READ ADDRESS = 2Fh READ Power Reset Value N/A 8 ADDRESS = 0Eh READ ...
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... ADDRESS = 1Ah WRITE/READ VERIFY ADDRESS = 3Ah WRITE/READ VERIFY Zarlink Semiconductor Inc. Data Sheet Power Reset Value 48h 8 Power Reset Value 00h 0 Power Reset Value 08h 8 Power Reset Value 00h 0 Power Reset Value 40h 8 Power Reset Value ...
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... MCLK MT9123 is in SSI mode MT9125 ADPCM MT9123 Sin Sout DSTi ADPCMo ADPCMi ENA EN1 ENB EN2 BCLK C20 Rout Rin DSTo MCLK F0i 24 Zarlink Semiconductor Inc. Data Sheet Din Dout BCLK STB1 Dual RF Section Din Dout BCLK STB1 Dual RF Section ...
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... C4i F0i MCLK MT9123 in ST-BUS mode 1 Back-To-Back Configuration using D&C channel bypass MT909x Digital Phone MT9123 Sin Sout DSTi Rout Rin DSTo F0i C4i F0i 25 Zarlink Semiconductor Inc. Data Sheet Din Dout C20 BCLK EN1 STB1 Dual RF Section Handset MCLK ...
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... 0 0. 3. 1.25 26 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0 ±20 mA °C -65 150 500 mW Units Test Conditions V V 400mV noise margin V 400mV noise margin V V °C Units Conditions/Notes µ ...
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... DIH t 20 150 F0iS t 20 150 F0iH t 80 DSD t 80 ASHZ t 20 DSH t 20 DSS t 80 DFD t 200 DFW 27 Zarlink Semiconductor Inc. Data Sheet Test Notes ns ns MHz MHz =150pF =150pF =150pF ...
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... CSH t 100 OHZ Symbol TTL Pin MCH t MCL Figure 15 - Master Clock - MCLK 28 Zarlink Semiconductor Inc. Data Sheet Units Test Notes =150pF =150pF L CMOS Pin Units - V 0.5 0.9 0.1 ...
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... DIS DIH Bit 1 Figure 16 - SSI Data Port Timing Bit 0 Bit DSD C4H t C4L t t DSS DSH Bit 0 Bit 1 Figure 17 - ST-BUS Data Port Timing 29 Zarlink Semiconductor Inc. Data Sheet AHZ BCL SSH ASHZ V TT ...
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... TTL input compatible 3. CMOS input (see Table 8 for symbol definitions) MT9123 DATA OUTPUT DATA INPUT t t IDH SCH t SCL Figure 18 - INTEL Serial Microport Timing t SCH t SCL 30 Zarlink Semiconductor Inc. Data Sheet ODD OHZ SCP CSH V TT ...
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... Zarlink Semiconductor 2005. All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...