IDT71V2577S85PF Integrated Device Technology, Inc., IDT71V2577S85PF Datasheet

IDT71V2577S85PF

Manufacturer Part Number

IDT71V2577S85PF

Description

Manufacturer

Integrated Device Technology, Inc.

Datasheet

1.IDT71V2577S85PF.pdf (23 pages)

Specifications of IDT71V2577S85PF

Case

TQFP

01+

Current page: 1 of 23
Download datasheet (522Kb)

NOTE:

1. BW

CLK

I/O

BWE

ADV

ADSC

ADSP

LBO

-A

128K x 36, 256K x 18 memory configurations

Supports fast access times:

Commercial:

– 7.5ns up to 117MHz clock frequency

Commercial and Industrial:

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

LBO input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte write

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array (fBGA)

-I/O

, CS

, V

, BW

DDQ

and BW

, I/O

, BW

-I/O

, BW

are not applicable for the IDT71V2579.

(1)

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Linear / Interleaved Burst Order

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Address Inputs

Address Status (Cache Controller)

Address Status (Processor)

128K x 36, 256K x 18

3.3V Synchronous SRAMs

2.5V I/O, Flow-Through Outputs

Burst Counter, Single Cycle Deselect

128K x 36/256K x 18. The IDT71V2577/79 SRAMs contain write, data,

address and control registers. There are no registers in the data output

path (flow-through architecture). Internal logic allows the SRAM to

generate a self-timed write based upon a decision which can be left until

the end of the write cycle.

system designer, as the IDT71V2577/79 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will flow-through from the

array after a clock-to-data access time delay from the rising clock edge of

the same cycle. If burst mode operation is selected (ADV=LOW), the

subsequent three cycles of output data will be available to the user on the

next three rising clock edges. The order of these three addresses are

defined by the internal burst counter and the LBO input pin.

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

The IDT71V2577/79 are high-speed SRAMs organized as

The burst mode feature offers the highest level of performance to the

The IDT71V2577/79 SRAMs utilize IDT’s latest high-performance

Supply

Input

I/O

Asynchronous

Synchronous

IDT71V2577

IDT71V2579

N/A

DSC-4877/06

4877 tbl 01

Related parts for IDT71V2577S85PF

IDT71V2577S85PF Summary of contents

Page 1

Supports fast access times: Commercial: – 7.5ns up to 117MHz clock frequency Commercial and Industrial: – 8.0ns up to 100MHz clock frequency – 8.5ns up to 87MHz clock frequency LBO input selects ...

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Symbol Pin Function I Address Inputs 0 17 ADSC Address Status (Cache Controller) ADSP Address Status (Processor) ...

Page 3

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect LBO ADV CLK ADSC ADSP 16/17 GW BWE ...

Page 4

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Symbol Rating (2) V Terminal Voltage with TERM Respect to GND (3,6) V Terminal Voltage with TERM Respect to ...

Page 5

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect 100 I I I/O ...

Page 6

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect 100 ...

Page 7

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect DDQ I I DDQ I/O G ...

Page 8

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect ( I/O NC ...

Page 9

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Symbol Parameter |I | Input Leakage Current LI ZZ and LBO Input Leakage Current | ...

Page 10

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Operation Address Used cte d Cycle , ...

Page 11

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect GW Operation Read Read Write all Bytes Write all Bytes (3) Write Byte 1 (3) Write Byte 2 (3) ...

Page 12

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Symbol Clock Parameter t Clock Cycle Time CYC (1) Clock High Pulse Width t CH (1) Clock Low Pulse ...

Page 13

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges , 6.42 13 ...

Page 14

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6. ...

Page 15

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges GW 6. ...

Page 16

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6. ...

Page 17

Page 18

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect CLK ADSP ADSC ADDRESS GW, BWE, BWx CE DATA OUT NOTES input ...

Page 19

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 19 ...

Page 20

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 20 ...

Page 21

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 21 ...

Page 22

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect IDT XXX Device Power Speed Package Type X Process/ Temperature Range Blank Commercial (0°C to +70°C ...

Page 23

... Pg. 7 Pg. 8 Pg. 20 10/25/00 Pg. 8 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 The IDT logo is a registered trademark of Integrated Device Technology, Inc. Updated to new format Revised I/O pin description Revised block diagram for flow-through functionality Revised I and I for speeds 7.5 to 8.5ns SB1 ZZ Added 119-lead BGA package diagram ...

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