DSPB56367PV150 Freescale Semiconductor, Inc, DSPB56367PV150 Datasheet

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... MHz clock at 1.5 V. This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2001, 2002, 2003, 2004, 2005, 2006, 2007. All rights reserved. Document Number: DSP56367 Rev ...

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Overview This data sheet uses the following conventions: OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) “asserted” Means that a high true (active high) signal is high ...

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Features Core features are described fully in the DSP56300 Family Manual. 1.2 DSP56300 modular chassis • 150 Million Instructions Per Second (MIPS) with a 150 MHz clock at internal logic supply (QVCCL) of 1.8V. • 100 Million Instructions Per ...

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Overview • Serial Audio Interface I(ESAI_1 receivers and transmitters, master or slave. I Sony, AC97, network and other programmable protocols The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT ...

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Signal/Connection Descriptions 2.1 Signal Groupings The input and output signals of the DSP56367 are organized into functional groups, which are listed in Table 2-1 and illustrated in Figure The DSP56367 is operated from a 1.8V supply; however, some of ...

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Signal Groupings PORT A ADDRESS BUS A0-A17 VCCA (3) GNDA (4) PORT A DATA BUS D0-D23 VCCD (4) GNDD (4) PORT A BUS CONTROL AA0-AA2/RAS0-RAS2 CAS VCCC (2) GNDC (2) INTERRUPT AND MODE CONTROL ...

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Power Power Name V PLL Power—V CCP CCP be provided with an extremely low impedance path to the V V (4) Quiet Core (Low) Power—V CCQL tied externally to all other V The user must provide adequate external decoupling ...

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Clock and PLL Ground Name GND (2) Bus Control Ground—GND C tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GND GND Host Ground—GND H to all other chip ground ...

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External Data Bus State during Signal Name Type D0–D23 Input/Output Tri-Stated 2.8 External Bus Control State During Signal Name Type Reset AA0–AA2/ Output Tri-Stated RAS0–RAS2 CAS Output Tri-Stated RD Output Tri-Stated WR Output Tri-Stated TA Input Ignored Input Transfer ...

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Interrupt and Mode Control Table 2-7 External Bus Control Signals (continued) State During Signal Name Type Reset BR Output Output (deasserted) BG Input Ignored Input Bus Grant— active-low input asserted by an external bus arbitration BB ...

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State During Signal Name Type Reset MODA/IRQA Input Input MODB/IRQB Input Input MODC/IRQC Input Input MODD/IRQD Input Input RESET Input Input Freescale Semiconductor Table 2-8 Interrupt and Mode Control Signal Description Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low ...

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Parallel Host Interface (HDI08) 2.10 Parallel Host Interface (HDI08) The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The HDI08 supports a variety of standard buses and can be directly connected ...

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State During Signal Name Type HA2 Input Disconnected HA9 Input PB10 Input, Output, or Disconnected HRW Input Disconnected HRD/ Input HRD PB11 Input, Output, or Disconnected HDS/ Input HDS Disconnected HWR/ Input HWR PB12 Input, Output, or Disconnected Freescale Semiconductor ...

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Parallel Host Interface (HDI08) State During Signal Name Type HCS Input Disconnected HA10 Input PB13 Input, Output, or Disconnected HOREQ/ Output HOREQ Disconnected HTRQ/ Output HTRQ PB14 Input, Output, or Disconnected HACK/ Input HACK Disconnected HRRQ/ Output HRRQ PB15 Input, ...

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Serial Host Interface The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I Signal Signal State During Name Type Reset SCK Input or Tri-Stated Output SCL Input or ...

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Serial Host Interface Table 2-10 Serial Host Interface Signals (continued) Signal Signal State During Name Type Reset MOSI Input or Tri-Stated Output HA0 Input SS Input Tri-Stated HA2 Input HREQ Input or Tri-Stated Output 2-12 Signal Description SPI Master-Out-Slave-In—When the ...

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Enhanced Serial Audio Interface Table 2-11 Enhanced Serial Audio Interface Signals Signal State during Signal Type Name Reset HCKR Input or Output GPIO Disconnected PC2 Input, Output, or Disconnected HCKT Input or Output GPIO Disconnected PC5 Input, Output, or ...

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Enhanced Serial Audio Interface Table 2-11 Enhanced Serial Audio Interface Signals (continued) Signal State during Signal Type Name Reset FST Input or Output GPIO Disconnected PC4 Input, Output, or Disconnected SCKR Input or Output GPIO Disconnected PC0 Input, Output, or ...

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Table 2-11 Enhanced Serial Audio Interface Signals (continued) Signal State during Signal Type Name Reset SDO4 Output GPIO Disconnected SDI1 Input PC7 Input, Output, or Disconnected SDO3/ Output GPIO SDO3_1 Disconnected SDI2/ Input SDI2_1 PC8/PE8 Input, Output, or Disconnected SDO2/ ...

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Enhanced Serial Audio Interface_1 Table 2-11 Enhanced Serial Audio Interface Signals (continued) Signal State during Signal Type Name Reset SDO0/ Output GPIO SDO0_1 Disconnected PC11/ Input, Output, or PE11 Disconnected 2.13 Enhanced Serial Audio Interface_1 Table 2-12 Enhanced Serial Audio ...

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Table 2-12 Enhanced Serial Audio Interface_1 Signals (continued) Signal State during Signal Type Name Reset SCKR_1 Input or Output GPIO Disconnected PE0 Input, Output, or Disconnected SCKT_1 Input or Output GPIO Disconnected PE3 Input, Output, or Disconnected SDO5_1 Output GPIO ...

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SPDIF Transmitter Digital Audio Interface 2.14 SPDIF Transmitter Digital Audio Interface Table 2-13 Digital Audio Interface (DAX) Signals Signal State During Type Name Reset ACI Input GPIO Disconnected PD0 Input, Output, or Disconnected ADO Output GPIO Disconnected PD1 Input, Output, ...

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JTAG/OnCE Interface Signal State during Signal Type Name Reset TCK Input Input TDI Input Input TDO Output Tri-Stated TMS Input Input Freescale Semiconductor Table 2-15 JTAG/OnCE Interface Signal Description Test Clock—TCK is a test clock input signal used to ...

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JTAG/OnCE Interface 2-20 NOTES DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...

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Specifications 3.1 Introduction The DSP56367 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs and outputs. This document contains information on a new product. Specifications and information herein are subject to change without notice. Finalized specifications ...

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Thermal Characteristics 1 Rating Supply Voltage All “3.3V tolerant” input voltages Current drain per pin excluding Operating temperature range Storage temperature 1 GND = 0 V, VCCP, VCCQL = 1.8 V ±5 –40×C to +95×C, ...

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DC Electrical Characteristics Characteristics Supply voltages • Core (V ) CCQL • PLL(V ) CCP Supply voltages • V CCQH • V CCA • V CCD • V CCC • V CCH • V CCS Input high voltage • ...

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AC Electrical Characteristics 3 This characteristic does not apply to PCAP. 4 Appendix A, "Power Consumption Benchmark" The requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are ...

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Characteristics Internal clock cycle time with PLL disabled Instruction cycle time Division Factor Ef = External frequency ET = External clock cycle Multiplication Factor PDF = Predivision Factor T = internal clock cycle C ...

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Phase Lock Loop (PLL) Characteristics No. Characteristics 2 4 EXTAL cycle time • With PLL disabled • With PLL enabled 7 Instruction cycle time = CYC • With PLL disabled • With PLL enabled 1 Measured at ...

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Reset, Stop, Mode Select, and Interrupt Timing Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing No. Characteristics 8 Delay from RESET assertion to all pins at reset value 3 9 Required RESET duration • Power on, external clock ...

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Reset, Stop, Mode Select, and Interrupt Timing Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing No. Characteristics 21 Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts • DRAM for all WS ...

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Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing No. Characteristics 28 DMA Requests Rate • Data read from HDI08, ESAI, ESAI_1, SHI, DAX • Data write to HDI08, ESAI, ESAI_1, SHI, DAX • Timer • IRQ, NMI (edge trigger) ...

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Reset, Stop, Mode Select, and Interrupt Timing RESET 8 All Pins A0–A17 A0–A17 RD WR IRQA, IRQB, IRQC, IRQD, NMI General Purpose I/O IRQA, IRQB, IRQC, IRQD, NMI 3-10 9 Reset Value Figure 3-2 Reset Timing First Interrupt Instruction Execution/Fetch ...

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IRQA, IRQB, IRQC, IRQD, NMI IRQA, IRQB, IRQC, IRQD, NMI Figure 3-4 External Interrupt Timing (Negative Edge-Triggered) RESET MODA, MODB, MODC, MODD, PINIT IRQA A0–A17 Figure 3-6 Recovery from Stop State Using IRQA Interrupt Service Freescale Semiconductor ...

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External Memory Expansion Port (Port A) IRQA A0–A17 Figure 3-7 Recovery from Stop State Using IRQA Interrupt Service A0–A17 RD WR IRQA, IRQB, IRQC, IRQD, NMI Figure 3-8 External Memory Access (DMA Source) Timing 3.10 External Memory Expansion Port (Port ...

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Table 3-8 SRAM Read and Write Accesses (continued) No. Characteristics 104 Address and AA valid to input data valid 105 RD assertion to input data valid 106 RD deassertion to data not valid (data hold time) 107 Address valid to ...

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External Memory Expansion Port (Port A) A0–A17 AA0–AA2 D0–D23 A0–A17 AA0–AA2 D0–D23 3-14 100 113 116 115 105 104 119 Figure 3-9 SRAM Read Access 100 107 101 102 114 108 Figure 3-10 SRAM ...

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DRAM Timing The selection guides provided in Final selection should be based on the timing provided in the following tables example, the selection guide suggests that 4 wait states must be used for 100 MHz operation when ...

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External Memory Expansion Port (Port A) Table 3-9 DRAM Page Mode Timings, Three Wait States No. Characteristics 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses ...

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Table 3-9 DRAM Page Mode Timings, Three Wait States No. Characteristics 153 RD assertion to data valid 154 RD deassertion to data not valid 155 WR assertion to data active 156 WR deassertion to data high impedance 1 The number ...

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External Memory Expansion Port (Port A) Table 3-10 DRAM Page Mode Timings, Four Wait States No. Characteristics 141 CAS assertion to column address not valid 142 Last column address valid to RAS deassertion 143 WR deassertion to CAS assertion 144 ...

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RAS CAS Row A0–A17 Add WR RD D0–D23 Figure 3-12 DRAM Page Mode Write Accesses Freescale Semiconductor 131 137 139 140 141 Column Column Address Address 151 144 145 146 155 150 149 Data Out Data Out DSP56367 Technical Data, ...

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External Memory Expansion Port (Port A) RAS CAS Row A0–A17 Add WR RD D0–D23 Figure 3-13 DRAM Page Mode Read Accesses 3-20 131 137 139 140 141 Column Column Address Address 143 133 153 Data In Data In DSP56367 Technical ...

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DRAM Type (t ns) Note: This figure should be use for primary selection. For exact RAC 100 Wait States 8 Wait States Figure 3-14 DRAM Out-of-Page Wait States Selection Guide Table 3-11 DRAM Out-of-Page ...

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External Memory Expansion Port (Port A) Table 3-11 DRAM Out-of-Page and Refresh Timings, Four Wait States No. Characteristics 165 RAS assertion to CAS deassertion 166 CAS assertion pulse width 167 RAS assertion to CAS assertion 168 RAS assertion to column ...

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Table 3-11 DRAM Out-of-Page and Refresh Timings, Four Wait States No. Characteristics 191 RD assertion to RAS deassertion 192 RD assertion to data valid 193 RD deassertion to data not valid 194 WR assertion to data active 195 WR deassertion ...

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External Memory Expansion Port (Port A) Table 3-12 DRAM Out-of-Page and Refresh Timings, Eleven Wait States No. Characteristics 173 Column address valid to CAS assertion 174 CAS assertion to column address not valid 175 RAS assertion to column address not ...

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Table 3-13 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States No. Characteristics 157 Random read or write cycle time 158 RAS assertion to data valid (read) 159 CAS assertion to data valid (read) 160 Column address valid to data valid ...

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External Memory Expansion Port (Port A) Table 3-13 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States No. Characteristics 183 WR assertion to RAS deassertion 184 WR assertion to CAS deassertion 185 Data valid to CAS assertion (write) 186 CAS assertion ...

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RAS 169 CAS A0–A17 WR RD D0–D23 Figure 3-15 DRAM Out-of-Page Read Access Freescale Semiconductor 157 163 165 167 164 168 170 166 171 173 175 Row Address Column Address 172 176 177 191 160 159 158 192 DSP56367 ...

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External Memory Expansion Port (Port A) 162 RAS 169 CAS A0–A17 WR RD D0–D23 Figure 3-16 DRAM Out-of-Page Write Access 3-28 157 163 165 167 164 168 166 170 171 173 172 176 Row Address Column Address 181 175 188 ...

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RAS 190 170 CAS 177 WR 3.10.3 Arbitration Timings Table 3-14 Asynchronous Bus Arbitration Timing No. Characteristics 250 BB assertion window from BG input negation. 251 Delay from BB assertion to BG assertion 1 Bit 13 in the OMR register ...

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External Memory Expansion Port (Port A) BG1 BB BG2 Figure 3-18 Asynchronous Bus Arbitration Timing BG1 BG2 Figure 3-19 Asynchronous Bus Arbitration Timing 3.10.4 Background explanation for Asynchronous Bus Arbitration: The asynchronous bus arbitration is enabled by internal synchronization circuits ...

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Parallel Host Interface (HDI08) Timing Table 3-15 Host Interface (HDI08) Timing No. Characteristics 317 Read data strobe assertion width HACK read assertion width 318 Read data strobe deassertion width HACK read deassertion width 319 Read data strobe deassertion width ...

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Parallel Host Interface (HDI08) Timing Table 3-15 Host Interface (HDI08) Timing No. 332 HCS assertion to output data valid 333 HCS hold time after data strobe deassertion 334 Address (AD7–AD0) setup time before HAS deassertion (HMUX=1) 335 Address (AD7–AD0) hold ...

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The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single data strobe mode. 10 The host request is HOREQ in the single host request ...

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Parallel Host Interface (HDI08) Timing HA0–HA2 HCS HWR, HDS HD0–HD7 HOREQ, HRRQ, HTRQ Figure 3-22 Write Timing Diagram, Non-Multiplexed Bus 3-34 336 331 320 321 324 340 341 DSP56367 Technical Data, Rev. 2.1 337 333 325 339 AA0485 Freescale Semiconductor ...

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HA8–HA10 322 HAS HRD, HDS HAD0–HAD7 HOREQ, HRRQ, HTRQ Figure 3-23 Read Timing Diagram, Multiplexed Bus Freescale Semiconductor 336 337 323 317 334 335 327 328 329 Address Data 326 340 341 DSP56367 Technical Data, Rev. 2.1 Parallel Host Interface ...

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Parallel Host Interface (HDI08) Timing HA8–HA10 322 HAS HWR, HDS HAD0–HAD7 HOREQ, HRRQ, HTRQ Figure 3-24 Write Timing Diagram, Multiplexed Bus HOREQ (Output) HACK (Input) H0–H7 (Input) Figure 3-25 Host DMA Write Timing Diagram 3-36 336 323 320 334 324 ...

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Figure 3-26 Host DMA Read Timing Diagram 3.12 Serial Host Interface SPI Protocol Timing Table 3-16 Serial Host Interface SPI Protocol Timing 1 No. Characteristics 140 Tolerable spike width on clock or data in 141 Minimum serial clock cycle = ...

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Serial Host Interface SPI Protocol Timing Table 3-16 Serial Host Interface SPI Protocol Timing (continued) 1 No. Characteristics 144 Serial clock rise/fall time 146 SS assertion to first SCK edge CPHA = 0 CPHA = 1 Last SCK edge to ...

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Table 3-16 Serial Host Interface SPI Protocol Timing (continued) No. Characteristics 160 SS deassertion pulse width (CPHA = 0) 161 HREQ in assertion to first SCK edge 162 HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) ...

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Serial Host Interface SPI Protocol Timing SS (Input) SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) MISO (Input) MOSI (Output) 161 HREQ (Input) 3-40 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 162 163 ...

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SS (Input) SCK (CPOL = 0) (Input) SCK (CPOL = 1) (Input) 150 MISO (Output) 148 MOSI (Input) HREQ (Output) Freescale Semiconductor 143 142 144 146 142 144 143 154 152 153 153 MSB 149 MSB Valid 157 Figure 3-29 ...

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Serial Host Interface (SHI Protocol Timing SS (Input) SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 150 MISO (Output) MOSI (Input) HREQ (Output) 3.13 Serial Host Interface (SHI) I No. Characteristics Tolerable spike width ...

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Table 3-17 SHI I No. Characteristics 175 SCL low period 176 SCL high period 177 SCL and SDA rise time 178 SCL and SDA fall time 179 Data set-up time 180 Data hold time 181 DSP clock frequency • Filters ...

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Serial Host Interface (SHI Protocol Timing 3.13.1 Programming the Serial Clock The programmed serial clock cycle, T HCKR (SHI clock control register). The expression for CCP CCP where HRS ...

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SCL 177 172 SDA Stop Start 174 188 HREQ 3.14 Enhanced Serial Audio Interface Timing Table 3-19 Enhanced Serial Audio Interface Timing No. Characteristics 7 430 Clock cycle 431 Clock high period • For internal clock • For external ...

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Enhanced Serial Audio Interface Timing Table 3-19 Enhanced Serial Audio Interface Timing No. Characteristics 437 RXC rising edge to FSR out (wl) high 438 RXC rising edge to FSR out (wl) low 439 Data in setup time before RXC (SCK ...

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Table 3-19 Enhanced Serial Audio Interface Timing No. Characteristics 454 TXC rising edge to data out valid 455 TXC rising edge to data out high impedance 456 TXC rising edge to transmitter #0 drive enable 9 deassertion 457 FST input ...

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Enhanced Serial Audio Interface Timing 8 The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as ...

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RXC (Input/Output) FSR (Bit) Out FSR (Word) Out Data In FSR (Bit) In FSR (Word) In Flags In HCKT SCKT (output) Freescale Semiconductor 430 431 432 433 434 437 439 First Bit 441 443 442 444 Figure 3-33 ESAI Receiver ...

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Digital Audio Transmitter Timing HCKR SCKR (output) 3.15 Digital Audio Transmitter Timing Table 3-20 Digital Audio Transmitter Timing No. Characteristic 1 ACI frequency 220 ACI period 221 ACI high duration 222 ACI low duration 223 ACI rising edge to ADO ...

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Timer Timing No. Characteristics 480 TIO Low 481 TIO High 1.8 V ± 0. –40°C to +95° TIO Figure 3-37 TIO Timer Event Input Restrictions 3.17 GPIO Timing No. Characteristics ...

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JTAG Timing EXTAL (Input) GPIO (Output) GPIO (Input) A0–A17 Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register. GPIO (Output) 3.18 JTAG Timing No. 500 TCK frequency of ...

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No. 509 TMS, TDI data hold time 510 TCK low to TDO data valid 511 TCK low to TDO high impedance 1.8 V ± 0. -40°C to +95° All timings ...

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JTAG Timing TCK V (Input) IL TDI TMS (Input) TDO (Output) TDO (Output) TDO (Output) Figure 3-41 Test Access Port Timing Diagram 3-54 508 Input Data Valid 510 Output Data Valid 511 510 Output Data Valid DSP56367 Technical Data, Rev. ...

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Packaging 4.1 Pin-out and Package Information This section provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated for the package. The ...

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Pin-out and Package Information SCK/SCL 1 SS#/HA2 2 HREQ# 3 SDO0/SDO0_1 4 SDO1/SDO1_1 5 SDO2/SDI3/SDO2_1/SDI3_1 6 SDO3/SDI2/SDO3_1/SDI2_1 7 VCCS 8 GNDS 9 SDO4/SDI1 10 SDO5/SDI0 11 FST 12 FSR 13 SCKT 14 SCKR 15 HCKT 16 HCKR 17 VCCQL 18 ...

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Pin Signal Name Signal Name No D10 A2 76 D11 A3 77 D12 A4 78 D13 A5 79 D14 A6 82 D15 A7 83 D16 A8 84 D17 A9 85 D18 A10 88 D19 A11 ...

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Pin-out and Package Information Table 4-2 Pin Signal Name No. 1 SCK/SCL 2 SS#/HA2 3 HREQ# 4 SDO0/SDO0_1 5 SDO1/SDO1_1 6 SDO2/SDI3/SDO2_1/SDI3_1 7 SDO3/SDI2/SDO3_1/SDI2_1 8 VCCS 9 GNDS 10 SDO4/SDI1 11 SDO5/SDI0 12 FST 13 FSR 14 SCKT 15 SCKR ...

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LQFP Package Mechanical Drawing Figure 4-2 DSP56367 144-pin LQFP Package ( Freescale Semiconductor DSP56367 Technical Data, Rev. 2.1 Pin-out and Package Information 4-5 ...

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Pin-out and Package Information Figure 4-3 DSP56367 144-pin LQFP Package ( 4-6 DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...

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Figure 4-4 DSP56367 144-pin LQFP Package ( Freescale Semiconductor DSP56367 Technical Data, Rev. 2.1 Pin-out and Package Information 4-7 ...

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Pin-out and Package Information 4-8 DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...

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Design Considerations 5.1 Thermal Design Considerations An estimation of the chip junction temperature, T Where: = ambient temperature ° package junction-to-ambient thermal resistance °C/W R qJA P = power dissipation in package W D Historically, thermal ...

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Electrical Design Considerations • To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat ...

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Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the V • All inputs must ...

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PLL Performance Issues One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). A benchmark power consumption test ...

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Appendix A Power Consumption Benchmark The following benchmark program permits evaluation of DSP power usage in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate instructions with a set of synthetic DSP application data ...

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XLOAD_LOOP ; ; Load the Y-data ; move #INT_YDAT,r0 move #YDAT_START,r1 do #(YDAT_END-YDAT_START),YLOAD_LOOP move p:(r1)+,x0 move x0,y:(r0)+ YLOAD_LOOP ; jmp INT_PROG PROG_START move #$0,r0 move #$0,r4 move #$3f,m0 move #$3f,m4 ; clr a clr ...

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dc $8FFD75 dc $9210A dc $A06D7B dc $CEA798 dc $8DFBF1 dc $A063D6 dc $6C6657 dc $C2A544 dc $A3662D dc $A4E762 dc $84F0F3 dc $E6F1B0 dc $B3829 dc $8BF7AE dc $63A94F dc $EF78DC dc $242DE5 dc $A3E0BA dc $EBAB6B dc $8726C8 ...

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XDAT_END YDAT_START ; org y:0 dc $5B6DA dc $C3F70B dc $6A39E8 dc $81E801 dc $C666A6 dc $46F8E7 dc $AAEC94 dc $24233D dc $802732 dc $2E3C83 dc $A43E00 dc $C2B639 dc ...

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YDAT_END Freescale Semiconductor DSP56367 ...

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A-6 NOTES DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...

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Index A ac electrical characteristics 4 B Boundary Scan (JTAG Port) timing diagram 53 bus external address 4 external data 4 C Clock 4 clock external 4 operation 5 clocks internal 4 D DAX 18 dc electrical characteristics 3 design ...

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F functional signal groups 1 G GPIO 18 GPIO timing 51 Ground 3 H HDI08 8, 10 HDI08 timing 31 Host Interface 8, 10 Host Interface timing 31 I internal clocks 4 interrupt and mode control 6, 7 interrupt control ...

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R recovery from Stop state using IRQA 11, 12 RESET 7 Reset timing Serial Host Interface 11 SHI 11 signal groupings 1 signals 1 SRAM read and write accesses 12 write access 14 Stop state recovery from ...

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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2001, 2002, 2003, 2004, 2005, 2006, 2007. All rights reserved. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts ...