CXD3526GG Sony, CXD3526GG Datasheet
CXD3526GG
Specifications of CXD3526GG
Related parts for CXD3526GG
CXD3526GG Summary of contents
Page 1
... Digital Signal Driver/Timing Generator Description The CXD3526GG incorporates digital signal processor type RGB driver, color shading correction and timing generator functions onto a single IC. Operation is possible with a system clock [MHz] (max.). This IC can process video signals in bands up to XGA standard, and can output the timing signals for driving various Sony LCD panels such as XGA and SVGA ...
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... CLKP CLKN CLKSEL CLKPOL PLLDIV RSDA Register I/F DSD TG PLL Direct Clear – 2 – CXD3526GG CLKOUT BOUT CTRL RGT, DWN HST, PST, HCK1, HCK2, DCK1, DCK2, ENB, PCG, PRG, SHST, HD2, HD3, CLR, CLP, HD1, VST, VCK, FRP, XFRP, XRGT, ...
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... View) 136 109 125 135 108 126 134 107 – 3 – CXD3526GG ...
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... GOUT9 O Green data output 35 ROUT2 O Red data output 36 ROUT6 O Red data output Description .) DD2 .) DD2 .) DD2 – 4 – CXD3526GG Input pin processing for open status — — — — — — — — — — — — — — — — ...
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... Serial bus data I/O (host I/ — GND SS 72 BOUT2 O Blue data output 73 BOUT6 O Blue data output Description .) DD2 – 5 – CXD3526GG Input pin processing for open status — — — — — — — — — — — — — — ...
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... O Blue data output 108 BOUT5 O Blue data output 109 BOUT8 O Blue data output 110 GOUT1 O Green data output Description – 6 – CXD3526GG Input pin processing for open status — — — — — — — — — — — — — ...
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... O Horizontal display transfer clock output 2 143 XFRP O AC drive inversion timing pulse output (reversed polarity of FRP) 144 V — I/O power supply DD2 Description – 7 – CXD3526GG Input pin processing for open status — — — — — — — — — — ...
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... RGB input, OSD input, HDIN, VDIN HSCL, HSDA, RSDA CL = 20pF 4 FRP , XFRP, SHST 50pF CLKOUT HCK1, HCK2, DCK1 20pF DCK2 HCK1 CL = 20pF HCK2 CL = 20pF PLLDIV = L — PLLDIV = H – 8 – CXD3526GG (Topr = –20 to +75° 0V) SS Min. Typ. Max. 2.3 2.5 2.7 3.0 3.3 3.6 2.0 — 0.3 DD2 –0.3 — ...
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... Operating Frequency vs. Power Consumption (Maximum Values) 130 120 110 100 500 Power Consumption vs. Junction Temperature (for Various Values of Thermal Resistance 100 Operating frequency [MHz] 43˚C/W 40˚C/W 700 900 1100 1300 1500 Power consumption [mW] – 9 – CXD3526GG 35˚C/W ...
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... TR > 200ns VC, 50% VC tis tih VC, VC, 50% 50 tof tor 50% tor 50% tof 50% 50% 50% 50 50% 50% 50 – 10 – CXD3526GG , V DD2 IH1 IH3 IL1 IL3 V IH3 V IL3 IH1 IH2 IL1 IL2 IH1 IH3 IL3 V ...
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... PLLDIV (Pin 129) sets the divider setting of the internal phase compensation PLL circuit. The setting values for master clock frequency are as follows. PLLDIV 100MHz 27.5 to 55MHz Note that the frequency of the clock input to the CXD3526GG must be within the phase compensation PLL operating range, even during free running. (e) RGB signal input pins (RIN, GIN and BIN) These pins input RGB digital signals in 10 bits ...
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... The pipeline delay for the I/O of the RGB signals is 32 clock cycles of the master clock. In addition, the pipeline delay for the OSD, YS and YM signals is 25 clock cycles of the master clock. or Vss externally. This V and Vss setting drives the device DD DD – 12 – CXD3526GG ...
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... HSDA input from low to high while HSCL input is high. Setting "Stop" status causes read processing to terminate during read operations, and causes the input of write data to terminate during write operations. HSDA HSCL "Start" "Start" Conditions and "Stop" Conditions 2 C bus specification. Also, when accessing gamma RAM, "Stop" – 13 – CXD3526GG ...
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... Acknowledgment on the I C Bus Slave Address Word (8 bits Slave Address Specification 1st memory address 2nd memory address (n) (n) W Byte Write Operation – 14 – CXD3526GG Not acknowledged Acknowledged 8 9 "Acknowledgment" Device R/W Select Code HSEL R/W Write data (n) ...
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... Continuous Write Operation 1st memory address 2nd memory address (n) (n) W Dummy write Slave address Current address read Byte Read Operation – 15 – CXD3526GG Write data (n) Write data ( Read data (n) R ...
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... There is no limit on the number of continuous transfers that are possible to read continuously with this IC. Slave address Read data (n) Read data ( • • • • • • • • Continuous Read Operation – 16 – CXD3526GG Read data ( ...
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... CSC_HP , CSC_VP , CSC_HNUM, CSC_VNUM, CSC_HINT and CSC_VINT. Make all settings in accordance with the specifications of the video signal attempting to be displayed. Gamma RAM access — Yes Yes No Color shading RAM access — Yes Yes No – 17 – CXD3526GG ...
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... EEPROM. The memory capacity of the external EEPROM is set using ROM_MAP of the serial bus control registers. ROM_MAP Operating frequency 35MHz or less 70MHz or less 94.5MHz or less 100MHz or less Usable memory size 512K-bit (65,536 8-bit) 256K-bit (32,768 8-bit) 128K-bit (16,384 8-bit) 64K-bit (8,192 8-bit) – 18 – CXD3526GG 2 C bus ...
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... X7h 0_7FFFh 0_FFFFh 3_7FFFh 3_FFFFh Memory address [18: 1st memory address [7:0] 2nd memory address [7:0] – 19 – CXD3526GG Slave address 0_0000h Bank 0 32K-byte X0h 0_8000h Bank 1 32K-byte X1h 1_0000h • • • 3_8000h Bank 7 32K-byte ...
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... In addition, the size of data transferred during refresh and write-back operations is fixed at 2K bytes for each color in the case of gamma data. The number of bytes transferred in the case of color shading data is the value stored in the color shading data size register plus one. 1st memory address 2nd memory address (n) (n) W Byte Write Operation – 20 – CXD3526GG Write data (n) ...
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... RAM data is stored here. Since registers have a double buffer configuration, data in the first buffer is synchronized with the internal VD and reflected in the second buffer, while data in the second buffer is input to each block. Note, however, that data in the serial bus control register has a single buffer configuration. – 21 – CXD3526GG ...
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... Bits 1 and 0 of the RSCL_SEL register to this value. Set the total capacity of the connected EEPROM devices and set Bits 5 and 4 of the ROM_MAP register to this value. Set the slave addresses of the EEPROM devices connected into the RSLV_ADDR register. Start End Start End – 22 – CXD3526GG ...
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... Is the status "1"? being performed 1: Write-back complete Write "1" to the REF_END register and clear status. Read the REF_RSEL register write-back complete for all RAMs? Yes Is there other gamma and color shading data to be written back? End End – 23 – CXD3526GG ...
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... Is forced refresh complete for all RAMs? Yes Set GAM_ON and CSC_ON so that the gamma RAMs and color shading RAMs will be used by the video signal video signal displayed, cancel muting of the video signal using the DSD register. End – 24 – CXD3526GG ...
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... RAMs. Forced refresh complete for all color shading RAMs. Set GAM_ON so that the color shading RAMs will be used by the video signal video signal displayed, cancel muting of the video signal using the DSD register. End – 25 – CXD3526GG ...
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... Stopping the refresh operation The following procedure is the procedure used to stop the self-refresh operation. Write 00h to the REF_MODE register to stop self-refresh. Start Set the REF_RSEL register to gamma RAM (R). Write "1" to the REF_END register and clear status. End Start End – 26 – CXD3526GG ...
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... PLL Counter HPOS. Counter HPLS N Detector Generator Pic. PLS HPOS. Counter VPLS Generator Register – 27 – CXD3526GG HST, PST, HCK1, HCK2, DCK1, DCK2, ENB, PCG, PRG, SHST, HD2, HD3, CLR CLP, HD1 VST, VCK, FRP, XFRP CTRL RGT, DWN XRGT, PO1, PO2 ...
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... Input a[9:0] Sub gain Sub bright YS OSD Gamma Gamma OSD correction gain Ghost Mute 2 Limiter cancel Coefficient b[7:0] 8 Rounding and clipping c[17:5] – 28 – CXD3526GG Black Mute 1 frame Gamma bright 10 Cycle offset OUT Output ...
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... When the operation results overflow or underflow, clipping is performed. Coefficient 11 b[10:0] Addition/subtraction 10 10 Input and Output a[9:0] clipping Coefficient b[7:0] 8 Rounding and clipping c[17:5] Coefficient b[10:0] 11 Addition/subtraction 10 10 Input and Output a[9:0] clipping – 29 – CXD3526GG 10 Output ...
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... MUTE1_ON Mute processing ON OFF (Settings shared and B_MUTE1: RGB mute data (Set independently for R, G and B) Coefficient 11 11 Pulse decoder Output Selector 10 Processing ON/OFF 10 Input 10 Selector 10 – 30 – CXD3526GG Horizontal display range 1 Horizontal display range 2 Vertical display range 1 Vertical display range 2 Output ...
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... PG_SIG1R (G, B)[9:0] and PG_SIG2R (G, B)[9:0] settings are invalid. The display patterns and signal levels are as follows. (1) Raster display When PG_PAT[2:0] = 0h, a raster is displayed. PG_SIG2R (G, B) PG_SIG1R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW – 31 – CXD3526GG Don't care ...
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... Window display When PG_PAT[2:0] = 1h, a window is displayed. PG_SIG2R (G, B) PG_SIG1R (G, B) PG_SIG1R (G, B) PG_SIG2R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW – 32 – CXD3526GG Don't care ...
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... The stripe period is set by PG_STEP in 1-dot units. The stripe width is set by PG_WIDTH in 1-dot units. PG_SIG2R (G, B) PG_SIG1R (G, B) PG_SIG1R (G, B) PG_SIG2R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW – 33 – CXD3526GG Don't care ...
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... The stripe period is set by PG_STEP in 1-dot units. The stripe width is set by PG_WIDTH in 1-dot units. PG_SIG2R (G, B) PG_SIG1R (G, B) PG_SIG1R (G, B) PG_SIG2R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW – 34 – CXD3526GG Don't care ...
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... The stripe period is set by PG_STEP in 1-dot units. The stripe width is set by PG_WIDTH in 1-dot units. PG_SIG2R (G, B) PG_SIG1R (G, B) PG_SIG1R (G, B) PG_SIG2R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW – 35 – CXD3526GG Don't care ...
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... The stripe period is set by PG_STEP in 1-dot units. The stripe width is set by PG_WIDTH in 1-dot units. PG_SIG2R (G, B) PG_SIG1R (G, B) PG_SIG1R (G, B) PG_SIG2R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW – 36 – CXD3526GG Don't care ...
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... The dot period is set by PG_STEP in 1-dot units. The dot width is set by PG_WIDTH in 1-dot units. PG_SIG2R (G, B) PG_SIG1R (G, B) PG_SIG1R (G, B) PG_SIG2R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW – 37 – CXD3526GG Don't care ...
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... When PG_PAT[2: and PG_STAIR_SW = 0, a horizontal ramp is displayed. The signal level is incremented from 000h by one graduation for each dot. PG_SIG2R (G, B) PG_SIG1R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW – 38 – CXD3526GG Don't care ...
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... When PG_PAT[2: and PG_STAIR_SW = 1, a horizontal stair is displayed. The signal level is incremented from 000h by 64 graduation for each 64 dots. PG_SIG2R (G, B) PG_SIG1R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW – 39 – CXD3526GG Don't care ...
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... When PG_PAT[2: and PG_STAIR_SW = 0, a vertical ramp is displayed. The signal level is incremented from 000h by one graduation for each line. PG_SIG2R (G, B) PG_SIG1R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW – 40 – CXD3526GG Don't care ...
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... When PG_PAT[2: and PG_STAIR_SW = 1, a vertical stair is displayed. The signal level is incremented from 000h by 64 graduation for each 32 lines. PG_SIG2R (G, B) PG_SIG1R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW – 41 – CXD3526GG Don't care ...
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... YS signal input OSD_MIX processing ON OFF OSD signal Gradual data 1 Gradual data 2 Gradual data 3 Gradual data 4 YS signal YM signal 10 Input Selected gradual data B_OSD_DAT1 B_OSD_DAT2 B_OSD_DAT3 B_OSD_DAT4 Selector Half-tone OSD_MIX processing – 42 – CXD3526GG 10 Output ...
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... Next, the c[6] value is checked and rounding is performed to 11 bits. The MSB of the rounded 11 bits is checked, clipping is performed, and the lower 10 bits are output. Coefficient b[7:0] 10 Input a[9:0] 1024 words. The settings are as follows. RAM ON/OFF Data path selection 10 RAM 10 bits 1024 words Selector 8 Rounding and clipping c[17:6] – 43 – CXD3526GG 10 Output Output ...
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... Multiplication is performed using the 10-bit input and a 11-bit coefficient with code. The coefficient MSB is the code bit. Addition is performed when b[10 and subtraction when b[10 However, when performing subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow or underflow, clipping is performed. Input a[9:0] Coefficient b[10:0] 11 Addition/subtraction 10 10 Output and clipping – 44 – CXD3526GG ...
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... RAM address is obtained as follows. RAM address = (m – – 1) For the example on page 47, this is as follows. (9 – – Thus, the correction data must be set in the RAM from address 0 to address 62. (Number of horizontal correction points) – 45 – CXD3526GG ...
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... SVGA (800 600) (number of horizontal correction points) (number of vertical correction points) Correction gap Number of correction points Example of Setting Correction Points – 46 – CXD3526GG G Total 8 1768 8 1536 1768 8 1232 8 8 1040 ...
Page 47
... Correction interval (128 dots) 1024 dots – 47 – CXD3526GG : Correction data that has been set in RAM : Interpolation operation results for the vertical direction : Interpolation operation results for the horizontal direction : Correction data that has been set in RAM : Data assumed to lie in invalid period ...
Page 48
... Screen 2 (Correction Point 2) Screen 3 (Correction Point 3) Screen 4 (Correction Point 4) Screen 5 (Correction Point 5) Screen 6 (Correction Point 6) Screen 7 (Correction Point 7) Screen 8 (Correction Point 8) Data for Screen 8 : Correction data that has been set in RAM (Correction Point 8) : Interpolation operation results for the gradual direction – 48 – CXD3526GG ...
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... Set data so that the relationship L_LIM_DAT < H_LIM_DAT is constantly maintained. When both coefficient values are 000h, limiter processing is not performed. Coefficient (H side) Coefficient (L side) Processing ON/OFF 10 Input 10 Selector 10 L_LIM_DAT, the output is clipped to L_LIM_DAT. input data, the output is clipped to H_LIM_DAT. 10 Input 10 10 Limiter 10 – 49 – CXD3526GG Output Ouput ...
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... In addition, settings can be made so that a limiter is used to ensure processing is performed only when the difference in the video signals set level or higher. Level selection 10 Shift Input Register 6 levels or 12 levels Processing Coefficient Coefficient ON/OFF Arithmetic Limiter Attenuator unit + – 50 – CXD3526GG – Clip processing Output ...
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... TG block register. The counter reset timing is delayed by 9 clocks from the front edge of the HDIN input when HP[10:0] = 000h. CLK HDIN R, G, BOUT HP[10:0] = 000h, 6-dot Period Processed Timing 4 Counter Selector 4 Addition/subtraction 10 Input and clipping clocks – 51 – CXD3526GG 4 12 Coefficient (1 to 12) 10 Output ...
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... ROM_TRAN[7:0] — — — — — — ROM_RST — — — — — — — — — RAM_FAIL – 52 – CXD3526GG Initial value DATA2 DATA1 DATA0 TEST2 RSCL_SEL[1:0] 00h — — — 00h — — 00h — — 00h GAM_ADDR[18:16] ...
Page 53
... These set the test mode. This is fixed to "0". (e) RSLV_ADDR[7:4] (sub address: 0001h) This sets the slave address of the external EEPROM. Although addresses of reserved areas can be set, be sure to set appropriate addresses. The lower portion of the slave addresses is determined by memory mapping. – 53 – CXD3526GG ...
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... The external EEPROM address of data to be transferred is determined by each start address register. Whether the data being transferred is gamma data or color shading data is determined by REF_RSEL[2]. Write-back starts when this mode is set. Each of these modes can be executed by writing these bits. – 54 – CXD3526GG ...
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... ACK is returned by Ack Polling. (p) REF_END (sub address: 000Ch) Indicates that forced refresh or write-back operations are complete. Cleared when "1" is written to this bit. Status Access of external EEPROM is complete Gamma (Green) Color shading (Blue) Gamma (Red). – 55 – CXD3526GG Gamma (Blue) Color ...
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... CLPU[10:8] CLPU[7:0] CLPD[7:0] SHP[5:0] HSTPC[5:0] HSTPF[5:0] PSTPC[5:0] PSTPF[5:0] HCKC[5:0] PCGD[9:8] ENBU[9:8] PCGU[7:0] PCGD[7:0] ENBU[7:0] ENBD[7:0] CLRD[9:8] VCKP[9:8] CLRU[7:0] CLRD[7:0] – 56 – CXD3526GG Initial value DATA2 DATA1 DATA0 RGT DWN FRVCLNK VCKPOL DCKPOL PSTPOL VCKFIX DCKFIX DCKFINV PLLP[10:8] HP[10:8] SHSTD[9:8] HD1D[10:8] CLPD[10:8] DCKW[3:0] ...
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... HCKOE Data DATA5 DATA4 DATA3 VCKP[7:0] VSTP[8:1] HD2U[10:8] HD2U[7:0] HD2D[7:0] HD3U[10:8] HD3U[7:0] HD3D[7:0] PRGOE SHSTOE FRPOE DCKOE VOE PCGOE – 57 – CXD3526GG Initial value DATA2 DATA1 DATA0 00h 00h HD2D[10:8] 00h 00h 00h 00h HD3D[10:8] 00h 00h 00h XFRPOE HD2OE 00h ...
Page 58
... VPOL must be set in accordance with the polarity of the sync signal input from HDIN and VDIN. Set HPOL and VPOL to "1" when the input sync signal is positive polarity "0" when negative polarity. N/2 or less N Must come before VST – 58 – CXD3526GG ...
Page 59
... PO1 and PO2 output settings PO1 and PO2 (sub address: 1029h) These set the PO1 and PO2 output. Setting value High is output Low is output The set data is reflected to the output pins PO1 (Pin 47) and PO2 (Pin 48) of the same name. – 59 – CXD3526GG ...
Page 60
... These set the output limit of HD1, HD2, HD3, CLP , PRG, SHST, PCG and CLR pulses, respectively. Setting value Pulse is output Output is fixed to "0" Pulses synchronized to the HP counter U and D are set to the same value, "1" is output HP[10:0] – 60 – CXD3526GG ...
Page 61
... This sets the vertical display start position in 8 bits. The position can be set in 1-line units using the front edge of VDIN as the reference. The VST, VCK, FRP and XFRP pulse phases change by linking with this setting. Minimum adjustment width: 1H VDIN HDIN VST VCK Tvp minimum and maximum setting values Min. VP[7:0] 000h Tvp 6H Tvp Max. FFh 261H – 61 – CXD3526GG ...
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... Negative 1 0 Negative 1 1 Positive 0 0 Negative 0 1 Negative 1 0 Positive 1 1 Positive PSTPOL RGT PST pulse output polarity 0 0 Positive 0 1 Negative 1 0 Negative 1 1 Positive 0 0 Negative 0 1 Negative 1 0 Positive 1 1 Positive – 62 – CXD3526GG HSTM, PSTM = 1 ...
Page 63
... These set the output limit of HST and PST pulses output limits, respectively. Setting value Pulse is output Output is fixed to "0" 2 – 2)". If higher values are set, the pulses are not 0 HP[10: Setting prohibited HSTPF = 04h – 63 – CXD3526GG HSTPF[5:0] ...
Page 64
... LCD panel Tckw HCKC SVGA 12 clk 0Bh XGA, WXGA 24 clk 17h Tckw HCKPOL RGT Output polarity Negative 1 0 Negative Negative 0 1 Negative HST HCK1 HSTPF[5:0] = 00h – 64 – CXD3526GG Positive Positive Positive Positive Negative HSTPF[5:0] = 00h ...
Page 65
... This sets the output limit of DCK1 and DCK2 pulses. Setting value Pulses are output Output is fixed to "0" Tdckw Tdckw Tdckf DCKFINV RGT Output phase HCK1 HCK2 DCK1 DCK2 – 65 – CXD3526GG ...
Page 66
... This setting eliminates the need to set the sample-and-hold position with a Sony sample-and-hold driver IC, and makes it possible to adjust the phases of the video signal to the LCD panel and the horizontal transfer clock without changing the position of the video signal on the screen. Video signal to LCD panel HCK1 SHP increased CLK SHP decreased – 66 – CXD3526GG ...
Page 67
... This sets the output limit of VST, VCK and ENB pulses. Setting value Pulse is output Output is fixed to "0" POL DWN Output polarity 0 0 Positive 0 1 Negative 1 0 Negative 1 1 Positive 0 0 Negative 0 1 Negative 1 0 Positive 1 1 Positive : VST or VCK – 67 – CXD3526GG ...
Page 68
... XFRP is output as the polarity inverted FRP pulse. (3) FRPOE and XFRPOE (sub address: 102Ch) These set the output limit of FRP and XFRP pulses, respectively. Setting value Pulse is output Output is fixed to "0" 1F – 68 – CXD3526GG ...
Page 69
... Setting value FRP and VCK transition points are shared FRP and VCK transition points are independent When FRVCLNK = 1, the VCK inversion timing is forcibly synchronized with the FRP inversion timing. When FRVCLNK = 0, the VCK transition point is independent of FRP . VCK FRVCLNK = 1 FRP VCK FRVCLNK = 0 FRP FRPP VCKP FRPP – 69 – CXD3526GG ...
Page 70
... G_MUTE1[7:0] B_MUTE1[7:0] B_MUTE1[9:8] G_MUTE1[9:8] R_OSD_DAT1[7:0] R_OSD_DAT2[7:0] R_OSD_DAT3[7:0] R_OSD_DAT4[7:0] R_OSD_DAT3[9:8] R_OSD_DAT2[9:8] G_OSD_DAT1[7:0] G_OSD_DAT2[7:0] G_OSD_DAT3[7:0] G_OSD_DAT4[7:0] G_OSD_DAT3[9:8] G_OSD_DAT2[9:8] B_OSD_DAT1[7:0] B_OSD_DAT2[7:0] B_OSD_DAT3[7:0] – 70 – CXD3526GG Initial value DATA2 DATA1 DATA0 MUTE1_ON FRM_ON 00h GC_MODE GAM_MODE 00h 00h 00h 00h 00h 00h 00h 00h 00h ...
Page 71
... R_MUTE2[7:0] G_MUTE2[7:0] B_MUTE2[7:0] B_MUTE2[9:8] G_MUTE2[9:8] L_LIM_DAT[7:0] H_LIM_DAT[7:0] B_GC_LIM_DAT[9:8] G_GC_LIM_DAT[9:8] R_GC_LIM_DAT[7:0] G_GC_LIM_DAT[7:0] B_GC_LIM_DAT[7:0] R_GC_ATT[7:0] G_GC_ATT[7:0] B_GC_ATT[7:0] – 71 – CXD3526GG Initial value DATA2 DATA1 DATA0 00h B_OSD_DAT1[9:8] 00h 00h 00h GAM_H1[10:8] 00h 00h 00h GAM_V1[10:8] 00h 00h 00h 00h ...
Page 72
... G_OFFSET10[3:0] 204Ch G_OFFSET12[3:0] 204Dh B_OFFSET2[3:0] 204Eh B_OFFSET4[3:0] 204Fh B_OFFSET6[3:0] 2050h B_OFFSET8[3:0] 2051h B_OFFSET10[3:0] 2052h B_OFFSET12[3:0] Data DATA5 DATA4 DATA3 – 72 – CXD3526GG Initial value DATA2 DATA1 DATA0 00h G_OFFSET5[3:0] G_OFFSET7[3:0] 00h 00h G_OFFSET9[3:0] 00h G_OFFSET11[3:0] 00h B_OFFSET1[3:0] B_OFFSET3[3:0] 00h 00h B_OFFSET5[3:0] ...
Page 73
... Black frame display range (g) FRM_ON (sub address: 2000h) This sets the processing ON/OFF for the black frame block. Setting value Black frame processing ON Black frame processing OFF FRM_H2 FRM_H1 Black frame display range FRM_V2 FRM_V1 Black frame display range – 73 – CXD3526GG ...
Page 74
... These set the vertical gamma correction processing range in 11 bits. The range can be set in 1-line units. Set it to match the effective period of the video signal. Set the "effective period – 2" value. VDIN GAM_H1 GAM_H2 Effective period GAM_V1 GAM_V2 Effective period – 74 – CXD3526GG ...
Page 75
... R_GC_LIM_DAT[9:0], G_GC_LIM_DAT[9:0] and B_GC_LIM_DAT[9:0] (sub addresses: 203Ah to 203Dh) These set the limiter data of the R, G and B ghost cancel block in 10 bits. (y) R_GC_ATT[7:0], G_GC_ATT[7:0] and B_GC_ATT[7:0] (sub addresses: 203Fh to 2040h) These set the multiplier arithmetic coefficient of the R, G and B ghost cancel block in 8 bits. – 75 – CXD3526GG ...
Page 76
... OFFSET_MODE (sub address: 2001h) This sets the counter cycle of cycle offset block. Setting value 12-dot period 6-dot period (B) R_OFFSET1 to 12[3:0], G_OFFSET1 to 12[3:0] and B_OFFSET1 to 12[3:0] (sub addresses: 2041h to 2052h) These set the offset data for the cycle offset block in 4 bits with code. – 76 – CXD3526GG ...
Page 77
... CSC_GGP6[9] CSC_GGP1[8:1] CSC_GGP2[8:1] CSC_GGP3[8:1] CSC_GGP4[8:1] CSC_GGP5[8:1] CSC_GGP6[8:1] CSC_GGP7[8:1] CSC_GGP8[8:1] CSC_BGP4[9] CSC_BGP5[9] CSC_BGP6[9] CSC_BGP1[8:1] CSC_BGP2[8:1] CSC_BGP3[8:1] CSC_BGP4[8:1] CSC_BGP5[8:1] CSC_BGP6[8:1] CSC_BGP7[8:1] – 77 – CXD3526GG Initial value DATA2 DATA1 DATA0 CSC_B_RGT CSC_HP[8] 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h CSC_GNUM[2:0] CSC_RGP7[9] ...
Page 78
... CSC_BGD1 CSC_BGD2 CSC_BGD3 3028h Data DATA5 DATA4 DATA3 CSC_BGP8[8:1] CSC_RGD4 CSC_RGD5 CSC_RGD6 CSC_GGD4 CSC_GGD5 CSC_GGD6 CSC_BGD4 CSC_BGD5 CSC_BGD6 CSC_XH_DAT[9:2] – 78 – CXD3526GG Initial value DATA2 DATA1 DATA0 00h CSC_RGD7 CSC_RGD8 00h CSC_GGD7 CSC_GGD8 00h CSC_BGD7 CSC_BGD8 00h 00h —: Don't care ...
Page 79
... Set the "number of correction points – 1" value. The size of the RAM for setting the correction data is 1792 words, so set the number of correction points as follows. Number of horizontal correction points Number of gradual correction points Number of vertical correction points 1792 – 79 – CXD3526GG ...
Page 80
... Correction start position CSC_HP Color shading correction range Correction interval CSC_VINT Correction start position CSC_HP Color shading correction range : Area actually corrected : Area virtually corrected – 80 – CXD3526GG Number of correction points CSC_HNUM 8 9 Virtual correction range CSC_HOS ...
Page 81
... This sets the display level (gradual level) of the cross hatch pattern used for color shading correction in 2-gradual units, 9 bits. Same data as Correction Point 1 CSC_R (G, B) GP1 CSC_R (G, B) GP2 CSC_R (G, B) GP3 CSC_R (G, B) GP4 CSC_R (G, B) GP5 CSC_R (G, B) GP6 CSC_R (G, B) GP7 CSC_R (G, B) GP8 Same data as Correction Point 8 – 81 – CXD3526GG ...
Page 82
... PG_VST[7:0] PG_VSTP[7:0] — PG_VWST[7:0] PG_VWSTP[7:0] PG_STEP[7:0] PG_WIDTH[7:0] — — PG_SIG1R[9:8] PG_SIG1R[7:0] PG_SIG2R[7:0] PG_SIG2G[9:8] PG_SIG1B[9:8] PG_SIG1G[7:0] PG_SIG2G[7:0] PG_SIG1B[7:0] PG_SIG2B[7:0] – 82 – CXD3526GG Initial value DATA2 DATA1 DATA0 PG_PAT[2:0] 00h PG_B_SEL PG_STAIR_SW 00h PG_HSTP[10:8] 00h 00h 00h PG_HWSTP[10:8] 00h 00h 00h PG_VSTP[10:8] 00h ...
Page 83
... PG_PAT[2: 7h) This switches between ramp and stair. Setting value Stair Ramp (g) PG_HST[10:0] (sub addresses: 4002h and 4003h) PG_HSTP[10:0] (sub addresses: 4002h and 4004h) These set the horizontal effective area in 11 bits. The area can be set in 1-dot units. – 83 – CXD3526GG ...
Page 84
... PG_SIG1R (G, B)[9:0] and PG_SIG2R (G, B)[9:0] (sub addresses: 4010h to 4017h) These set the output signal level inside and outside the pattern area within the effective area in 10 bits. The level can be set with an accuracy of 1 bit. PG_HST PG_HWST PG_HWSTP PG_VST Effective area Window area – 84 – CXD3526GG PG_HSTP ...
Page 85
... · · · · – 85 – CXD3526GG RAM address LSB D0 000h D8 D0 001h D8 · · · · · · D0 3FFh D8 3 gradual points = 663 points. RAM address LSB D0 000h (Upper left) · ...
Page 86
... IC junction temperature does not exceed the maximum value. • Be sure to make the number of dot clocks input to the CXD3526GG even number. Note that if there is an odd number of dot clocks, the internal phase compensation PLL will not operate properly. ...
Page 87
... CLKPOL CLKSEL PLLDIV HSEL GND – 87 – CXD3526GG Red output +2.5V 10µ 37 Vss 114 0.1µ V DD2 138 V 0.1µ DD2 139 Vss 140 0.1µ ...
Page 88
... SONY CODE BGA-144P-021 P-BGA144-12X12-0.8 JEITA CODE JEDEC CODE 144PIN BGA X SOLDER BALL 144- 0.45 ± 1.2 PACKAGE STRUCTURE PACKAGE MATERIAL BOARD MATERIAL TERMINAL MATERIAL PACKAGE MASS – 88 – CXD3526GG +0.20 1.25 - 0.10 0.38 ± 0.10 0.1 S DETAIL X EPOXY RESIN COPPER-CLAD LAMINATE SOLDER 0.31g Sony Corporation ...