CXA3246Q Sony, CXA3246Q Datasheet
CXA3246Q
Specifications of CXA3246Q
Related parts for CXA3246Q
CXA3246Q Summary of contents
Page 1
... Flash A/D Converter Description The CXA3246Q is an 8-bit high-speed flash A/D converter capable of digitizing analog signals at the maximum rate of 120MSPS. ECL, PECL or TTL can be selected as the digital input level in accordance with the application. The TTL digital output level allows 1: 2 demultiplexed output. ...
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... V RB +2.9 +1 – N/E|) 0.4 0.8 100 120 –20 VID – 2 – CXA3246Q Unit 0 °C W 50mm, 1.6mm thick) With dual power supply Unit Max. Min. Typ. Max. +5.25 +4.75 +5.0 +5.25 +0.05 –0.05 0 +0.05 +5.25 – ...
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... PECL PECL TTL — +5V 0V TTL 0V +5V +5V 0V TTL 0V +5V TTL TTL TTL TTL PECL PECL – 3 – CXA3246Q Typical voltage level with dual power supply –5.0V 1.4 to 2.6V 0V — + — +5V — 0V 2.9 to 4.1V 0V ECL ECL TTL — +5V 0V ...
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... AGND INV 6bit 8bit 6bit 6bit 8bit 6bit D Q Select SELECT DGND1 DGND2 – 4 – CXA3246Q DGND3 12 (MSB) PBD7 40 PBD6 39 PBD5 38 PBD4 37 PBD3 36 PBD2 35 PBD1 34 PBD0 33 (LSB) (MSB) PAD7 28 PAD6 27 PAD5 26 PAD4 25 PAD3 ...
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... Digital ground. Digital power supply. Digital power supply. Ground for ECL input. +5V for PECL and TTL inputs. Digital power supply. –5V for ECL input. Ground for PECL and TTL inputs. No connected pin. Not connected with the internal circuits. – 5 – CXA3246Q Description ...
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... DGND1 – 6 – CXA3246Q Description Clock input. CLK/E complementary input. When left open, this pin goes to the threshold voltage. Only CLK/E can be used for operation, but complementary inputs are recommended to attain fast and stable operation. Reset signal input. ...
Page 7
... DGND2 D 3 VEE DGND1 – 7 – CXA3246Q Description Top reference voltage. By-pass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. Reference voltage mid point. By-pass to AGND with a 0.1µF chip capacitor. Reference voltage mid point. By-pass to AGND with a 0.1µF chip capacitor ...
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... DMUX mode CLK CLK RESETN – CLK RESETN – CLK (C = 5pF) L DMUX mode (C = 5pF 5pF) L 0 5pF) L 0 5pF) L – 8 – CXA3246Q 25° Min. Typ. Max. Unit 8 bits ±0.5 LSB ±0.5 LSB 100 285 µ ...
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... DMUX mode Error > 16LSB Fc = 120MSPS, { fin = 29.999MHz Fs DMUX mode Error > 16LSB Fc = 100MSPS, { fin = 24.999MHz Fs Straight mode Error > 16LSB and – 9 – CXA3246Q Min. Typ. Max. Unit MHz 250 –12 TPS 10 –9 TPS 10 –9 TPS 98 140 ...
Page 10
... Table 1. I/O Correspondence Table INV – 10 – CXA3246Q ...
Page 11
... Taj is: Taj = / 8 Latch CLK + Latch 16LSB 1/8 – 11 – CXA3246Q Amp Logic CXA3246Q Analizer CLK 1024 samples ECL Buffer 129 128 t (LSB) ...
Page 12
... When using the multiple CXA3246Q in DMUX mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in the example on the next page countermeasure, the CXA3246Q has a function that resets the 1/2 frequency-divided clocks ...
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... The A/D converter can operate at Fc (min.) = 100MSPS in this mode. Digital input level and supply voltage settings The logic input level for the CXA3246Q supports ECL, PECL and TTL levels. The power supplies (DV 3, DGND3) for the logic input block must be set to match the logic input (CLK and EE reset signals) level ...
Page 14
... PAD0 to PAD7 8 bit Digital Data +5V(D) – 14 – CXA3246Q 8 bit Digital Data Latch 8 bit Digital Data Latch 8 bit Digital Data Latch 8 bit Digital Data Latch 8 bit Digital Data Latch 8 bit Digital Data Latch ...
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... Digital Data PECL TTL DG +5V(D) +5V( PBD0 to PBD7 8-bit Digital Data +5V(D) – 15 – CXA3246Q 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch ...
Page 16
... A/D converter. See the Notes on Operation. is the chip capacitor of 0.1µF. Also important to suppress the noise generated during the TTL output circuit is operating. Place C at the fixed position between the pins with the shortest distance. – 16 – CXA3246Q ...
Page 17
... CLK OUT (Pin 43) T_rh T_rs T_rh RESETN (Pin 48 Td_clk; 4.5ns (typ.) 7.0ns (max) 3.0ns (min) 2.0V 2.0V (Reset period) 0.8V 0.8V T_rs – 17 – CXA3246Q Tdo2; 5.0ns (typ.) 3.5ns (min) 7.5ns (max) 2. 0.8V 2. 0.8V Tdo1 0.5ns (typ.) 2.0V 0.8V ...
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... PAD0 to D7 2.0V N – 4 (Pins 21 to 28) 0.8V PBD0 to D7 2.0V N – 3 (Pins 33 to 40) 0.8V Td_clk; 4.5ns (typ.) 3.0ns (min) 7.0ns (max) CLK OUT 2.0V (CLK is inverted and output.) 0.8V (Pin 43 – – – – 1 – 18 – CXA3246Q – ...
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... Notes on Operation • The CXA3246Q has the PECL and TTL input pins for the clock and reset input pins. When the clock is input in PECL level, inputting the reset signal in PECL level is recommended. Also, when the clock is input in TTL level, inputting the reset signal in TTL is recommended. ...
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... Analog input voltage [V] Current consumption vs. Conversion rate characteristics 110 105 100 – Conversion rate [MSPS] Reference current vs. Ambient temperature characteristics –25 Ta – Ambient temperature [°C] – 20 – CXA3246Q f CLK fin = – 1kHz 4 DMUX mode C = 5pF L 60 120 25 75 ...
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... Error rate: 10 TPS 150 140 130 – – Ambient temperature [°C] Error rate vs. Conversion rate characteristics – CLK fin = – 1kHz 4 –7 10 Error > 16LSB –8 10 –9 10 – 120 Fc – Conversion rate [MSPS] 75 – 21 – CXA3246Q 140 160 ...
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... NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). 48PIN QFP (PLASTIC 0.15 0.3 – 0.1 0. 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS – 22 – CXA3246Q + 0.1 0.15 – 0.05 0.15 + 0.2 0.1 – 0.1 EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.7g ...