HD6433657H Renesas Electronics Corporation., HD6433657H Datasheet
HD6433657H
Related parts for HD6433657H
HD6433657H Summary of contents
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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H8/3657 Series HD6473657, HD6433657 H8/3656 HD6433656 H8/3655 HD6433655 H8/3654 HD6433654 H8/3653 HD6433653 H8/3652 HD6433652 Hardware Manual ...
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The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core, with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU. The H8/3657 Series has a system-on-a-chip architecture that includes ...
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Section 1 Overview .......................................................................................................... 1.1 Overview......................................................................................................................... 1.2 Internal Block Diagram .................................................................................................. 1.3 Pin Arrangement and Functions ..................................................................................... 1.3.1 Pin Arrangement................................................................................................. 1.3.2 Pin Functions ...................................................................................................... Section 2 CPU ................................................................................................................... 11 2.1 Overview......................................................................................................................... 11 2.1.1 Features............................................................................................................... 11 2.1.2 Address Space..................................................................................................... 12 2.1.3 ...
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Application Notes ........................................................................................................... 46 2.9.1 Notes on Data Access ......................................................................................... 46 2.9.2 Notes on Bit Manipulation.................................................................................. 48 2.9.3 Notes on Use of the EEPMOV Instruction......................................................... 54 Section 3 Exception Handling 3.1 Overview......................................................................................................................... 55 3.2 Reset ............................................................................................................................ 55 3.2.1 Overview............................................................................................................. ...
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Transition to Watch Mode .................................................................................. 98 5.4.2 Clearing Watch Mode......................................................................................... 98 5.4.3 Oscillator Settling Time after Watch Mode is Cleared ...................................... 98 5.5 Subsleep Mode................................................................................................................ 99 5.5.1 Transition to Subsleep Mode .............................................................................. 99 5.5.2 Clearing Subsleep Mode..................................................................................... 99 5.6 ...
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Pin States ............................................................................................................ 130 8.4 Port 3 ............................................................................................................................ 131 8.4.1 Overview............................................................................................................. 131 8.4.2 Register Configuration and Description ............................................................. 131 8.4.3 Pin Functions ...................................................................................................... 135 8.4.4 Pin States ............................................................................................................ 136 8.4.5 MOS Input Pull-Up............................................................................................. 136 8.5 Port 5 ............................................................................................................................ 137 ...
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Register Descriptions.......................................................................................... 158 9.2.3 Timer Operation.................................................................................................. 160 9.2.4 Timer A Operation States ................................................................................... 161 9.3 Timer B1......................................................................................................................... 162 9.3.1 Overview............................................................................................................. 162 9.3.2 Register Descriptions.......................................................................................... 163 9.3.3 Timer Operation.................................................................................................. 165 9.3.4 Timer B1 Operation States ................................................................................. 166 9.4 Timer V........................................................................................................................... ...
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Operation in Asynchronous Mode...................................................................... 271 10.3.5 Operation in Synchronous Mode ........................................................................ 280 10.3.6 Multiprocessor Communication Function .......................................................... 287 10.3.7 Interrupts............................................................................................................. 294 10.3.8 Application Notes ............................................................................................... 295 Section 11 14-Bit PWM 11.1 Overview......................................................................................................................... 299 11.1.1 Features............................................................................................................... 299 11.1.2 Block Diagram.................................................................................................... ...
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AC Characteristics (HD6433657, HD6433656, HD6433655, HD6433654, HD6433653, HD6433652)............................................................ 333 13.2.6 A/D Converter Characteristics............................................................................ 336 13.3 Operation Timing............................................................................................................ 337 13.4 Output Load Circuit........................................................................................................ 340 Appendix A CPU Instruction Set A.1 Instructions ..................................................................................................................... 341 A.2 Operation Code Map....................................................................................................... 349 A.3 Number ...
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Overview The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/3657 Series of microcomputers are equipped with a ...
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Table 1-1 Features (cont) Item Description Interrupts 33 interrupt sources • 12 external interrupt sources (IRQ • 21 internal interrupt sources Clock pulse generators Two on-chip clock pulse generators • System clock pulse generator MHz • Subclock ...
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Table 1-1 Features (cont) Item Description Timers • Timer V: 8-bit timer — Count-up timer with selection of six internal clock signals or event input — Compare-match waveform output — Incrementing specifiable by external trigger input • Timer X: 16-bit ...
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... Table 1-1 Features (cont) Item Specification Product lineup Mask ROM Version HD6433657W HD6433657X HD6433657H HD6433657F HD6433656W HD6433656X HD6433656H HD6433656F HD6433655W HD6433655X HD6433655H HD6433655F HD6433654W HD6433654X HD6433654H HD6433654F HD6433653W HD6433653X HD6433653H HD6433653F HD6433652W HD6433652X HD6433652H HD6433652F Product Code ZTAT™ Version Package HD6473657W ...
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Internal Block Diagram Figure 1-1 shows a block diagram of the H8/3657 Series. P1 /TMOW /PWM 4 P1 /IRQ /IRQ /IRQ /TRGV ...
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Pin Arrangement and Functions 1.3.1 Pin Arrangement The H8/3657 Series pin arrangement is shown in figures 1-2 (TFP-80C, TFP-80F, FP-80A), and in figures 1-3 (FP-80B ...
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TEST ...
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Pin Functions Table 1-2 outlines the pin functions of the H8/3657 Series. Table 1-2 Pin Functions Pin No. TFP-80C, TFP-80F, Type Symbol FP-80A Power V 13 source pins ...
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Table 1-2 Pin Functions (cont) Pin No. TFP-80C, TFP-80F, Type Symbol FP-80A Timer pins TMIB 26 TMOV 42 TMCIV 41 TMRIV 40 TRGV 75 FTCI 44 FTOA 45 FTOB 46 FTIA 47 FTIB 48 FTIC 49 FTID 50 14-bit PWM ...
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Table 1-2 Pin Functions (cont) Pin No. TFP-80C, TFP-80F, Type Symbol FP-80A I/O ports ...
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Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. • General-register ...
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Address Space The H8/300L CPU supports an address space kbytes for storing program code and data. See 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2-1 shows the register structure ...
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Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H ...
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Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using ...
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Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR ...
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Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-3. Data Type Register No. 7 1-bit data RnH 7 1-bit data RnL 7 Byte data RnH MSB ...
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Memory Data Formats Figure 2-4 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. In word access the least significant bit of the address ...
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Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a subset of these addressing modes. Table 2-1 Addressing Modes No. Address Modes 1 Register direct 2 Register indirect ...
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Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: • Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the ...
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Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 ...
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Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2-3. Table 2-3 Instruction Set Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data ...
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Notation Rd General register (destination) Rs General register (source) Rn General register (EAd), <EAd> Destination operand (EAs), <EAs> Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag ...
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Data Transfer Instructions Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats. Table 2-4 Data Transfer Instructions Instruction Size* MOV B/W POP W PUSH W Notes: * Size: Operand size B: Byte W: Word ...
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Notation: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2-5 Data Transfer ...
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Arithmetic Operations Table 2-5 describes the arithmetic instructions. Table 2-5 Arithmetic Instructions Instruction Size* Function ADD B/W Rd ± Rs SUB Performs addition or subtraction on data in two general registers, or addition on immediate data and data in ...
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Logic Operations Table 2-6 describes the four instructions that perform logic operations. Table 2-6 Logic Operation Instructions * Instruction Size Function AND B Rd Performs a logical AND operation on a general register and another general register or immediate ...
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Figure 2-6 shows the instruction code format of arithmetic, logic, and shift instructions Notation: op: Operation field rm, rn: Register field IMM: Immediate data ...
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Bit Manipulations Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats. Table 2-8 Bit-Manipulation Instructions Instruction Size* Function BSET B 1 Sets a specified bit in a general register or memory to 1. The bit ...
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Table 2-8 Bit-Manipulation Instructions (cont) Instruction Size* Function BXOR B C XORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. BIXOR B C XORs the C flag ...
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Notation: op: Operation field rm, rn: Register ...
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Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 Bit Manipulation Instruction Codes (cont IMM ...
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Branching Instructions Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats. Table 2-9 Branching Instructions Instruction Size Function Bcc — Branches to the designated address if condition cc is true. The branching conditions are given ...
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Notation: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2-8 Branching Instruction Codes 8 7 disp 8 ...
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System Control Instructions Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats. Table 2-10 System Control Instructions Instruction Size* Function RTE — Returns from an exception-handling routine SLEEP — Causes a transition from active ...
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Notation: op: Operation field rn: Register field IMM: Immediate data Figure 2-9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2-11 describes the block data transfer instruction. Figure 2-10 shows its object code format. ...
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Notation: op: Operation field Figure 2-10 Block Data Transfer Instruction Code ...
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Basic Operational Timing CPU operation is synchronized by a system clock (ø subclock (ø clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or ø the next rising edge is ...
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Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions ...
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Three-state access to on-chip peripheral modules ø or ø SUB Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Figure 2-13 On-Chip Peripheral Module Access Cycle (3-State Access) Bus cycle ...
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CPU States 2.7.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or medium- speed) mode and subactive mode. In the program halt ...
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Reset state Reset occurs Program halt state 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one ...
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Memory Map Figure 2-16 shows a memory map of the H8/3657 Series. H'0000 Interrupt vectors H'002F H'0030 H'3FFF On-chip ROM H'5FFF H'7FFF H'9FFF H'BFFF H'EDFF H'EE00 Reserved H'F770 Internal I/O registers (16 bytes) H'F77F H'F780 H'FB80 On-chip RAM H'FF7F ...
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Application Notes 2.9.1 Notes on Data Access 1. The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by ...
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H'0000 Interrupt vector area (48 bytes) H'002F H'0030 On-chip ROM H'EDFF Reserved H'F770 Internal I/O registers (16 bytes) H'F77F H'F780 On-chip RAM H'FF7F H'FF80 Reserved H'FF9F H'FFA0 Internal I/O registers (96 bytes) H'FFFF Notes: The H8/3657 is shown as an ...
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Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers ...
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Example 2: BSET instruction executed designating port 3 P3 and P3 are designated as input pins, with a low-level signal input The remaining pins example, the BSET instruction is used to ...
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As a result of this operation, bit 0 in PDR3 becomes 1, and P3 However, bits 7 and 6 of PDR3 end up with different values. To avoid this problem, store a copy of the PDR3 data in a work ...
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After executing BSET] MOV. B @RAM0, R0L MOV. B R0L, @PDR3 Input/output Input Input Pin state Low High level level PCR3 0 0 PDR3 1 0 RAM0 Bit manipulation in a register containing ...
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After executing BCLR Input/output Output Output Pin state Low High level level PCR3 1 1 PDR3 1 0 [D: Explanation of how BCLR operates] When the BCLR instruction is executed, first the CPU reads PCR3. Since ...
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BCLR instruction executed] BCLR #0 , @RAM0 [C: After executing BCLR] MOV. B @RAM0, R0L MOV. B R0L, @PCR3 Input/output Input Input Pin state Low High level level PCR3 0 0 PDR3 1 0 RAM0 0 ...
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Table 2-13 Registers with Write-Only Bits Register Name Port control register 1 Port control register 2 Port control register 3 Port control register 5 Port control register 6 Port control register 7 Port control register 8 Port control register 9 ...
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Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/3657 Series when a reset or interrupt occurs. Table 3-1 shows the priorities of these two types of exception handling. Table 3-1 Exception Handling Types and Priorities Priority ...
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When system power is turned on or off, the RES pin should be held low. Figure 3-1 shows the reset sequence starting from RES input. RES ø Internal address bus Internal read signal Internal write signal Internal data bus (16-bit) ...
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Interrupt Immediately after Reset After a reset interrupt were to be accepted before the stack pointer (SP: R7) was initialized, PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To prevent ...
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Table 3-2 Interrupt Sources and Their Priorities Interrupt Source Interrupt RES Reset IRQ IRQ 0 0 IRQ IRQ 1 1 IRQ IRQ 2 2 IRQ IRQ 3 3 INT INT 0 0 INT INT 1 1 INT INT 2 2 ...
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Interrupt Control Registers Table 3-3 lists the registers that control interrupts. Table 3-3 Interrupt Control Registers Name Interrupt edge select register 1 Interrupt edge select register 2 Interrupt enable register 1 Interrupt enable register 2 Interrupt enable register 3 ...
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Bit 3: IRQ edge select (IEG3) 3 Bit 3 selects the input sensing of pin IRQ Bit 3 IEG3 Description 0 Falling edge of IRQ 1 Rising edge of IRQ Bit 2: IRQ edge select (IEG2) 2 Bit 2 selects ...
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Interrupt edge select register 2 (IEGR2) Bit 7 INTEG7 INTEG6 Initial value 0 Read/Write R/W IEGR2 is an 8-bit read/write register, used to designate whether pins INT TMIB are set to rising edge sensing or falling edge sensing. Upon ...
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Bits INT to INT edge select (INTEG4 to INTEG0 Bits select the input sensing of pins INT Bit n INTEGn Description 0 Falling edge of INT 1 Rising edge of INT 3. ...
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Bit 5: Reserved bit Bit 5 is reserved always read as 0 and cannot be modified. Bit 4: Reserved bit Bit 4 is reserved always read as 1, and cannot be modified. Bits ...
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Bit 6: A/D converter interrupt enable (IENAD) Bit 6 enables or disables A/D converter interrupt requests. Bit 6 IENAD Description 0 Disables A/D converter interrupt requests 1 Enables A/D converter interrupt requests Bit 5: Reserved bit Bit 5 is reserved: ...
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Interrupt enable register 3 (IENR3) Bit 7 INTEN7 INTEN6 Initial value 0 Read/Write R/W IENR3 is an 8-bit read/write register that enables or disables INT reset, IENR3 is initialized to H'00. Bits INT to INT interrupt ...
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Bit 6: Timer A interrupt request flag (IRRTA) Bit 6 IRRTA Description 0 Clearing conditions: When IRRTA = cleared by writing 0 1 Setting conditions: When the timer A counter value overflows from H'FF to H'00 Bit ...
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Interrupt request register 2 (IRR2) Bit 7 IRRDT Initial value 0 * Read/Write R/W Note: * Only a write of 0 for flag clearing is possible IRR2 is an 8-bit read/write register, in which a corresponding flag is set ...
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Bit 4: SCI1 interrupt request flag (IRRS1) Bit 4 IRRS1 Description 0 Clearing conditions: When IRRS1 = cleared by writing 0 1 Setting conditions: When an SCI1 transfer is completed Bits Reserved bits Bits ...
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When these pins are designated as pins IRQ edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Recognition of these interrupt requests can be disabled individually by clearing bits IEN3 to IEN0 to 0 ...
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Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3-2 shows a block diagram of the interrupt controller. Figure 3-3 shows the flow up to interrupt acceptance. External or internal interrupts External interrupts or internal interrupt enable signals ...
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If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3-4. The PC value pushed ...
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Program execution state No IRRIO = 1 Yes No IENO = 1 Yes IRRI1 = 1 IEN1 = Yes PC contents saved CCR contents saved I 1 Branch to interrupt handling routine Notation: PC: Program ...
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SP – – – – (R7) Stack area Prior to start of interrupt exception handling Notation Upper 8 bits of program counter (PC Lower 8 bits of ...
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Figure 3-5 Interrupt Sequence 74 ...
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Interrupt Response Time Table 3-4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3-4 Interrupt Wait States Item Waiting time for completion of ...
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Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the H8/3657 Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so ...
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Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port ...
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CCR I bit 1 Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 CCR I bit 0 Figure 3-7 Port Mode Register Setting and Interrupt Request Flag Interrupts masked. (Another possibility is to disable the ...
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Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator ...
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System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator providing external clock input. 1. Connecting a crystal oscillator Figure 4-2 shows a typical method of ...
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Connecting a ceramic oscillator Figure 4-4 shows a typical method of connecting a ceramic oscillator. OSC OSC Figure 4-4 Typical Connection to Ceramic Oscillator 3. Notes on board design When generating clock pulses by connecting a crystal or ceramic ...
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External clock input method Connect an external clock signal to pin OSC connection. OSC 1 OSC 2 Figure 4-6 External Clock Input (Example) Frequency Oscillator Clock (ø Duty cycle 45% to 55% , and leave pin OSC open. Figure ...
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Subclock Generator 1. Connecting a 32.768-kHz crystal oscillator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal oscillator, as shown in figure 4-7. Follow the same precautions as noted under 4.2.3, Note on board ...
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Pin connection when not using subclock When the subclock is not used, connect pin X figure 4-9. Figure 4-9 Pin Connection when not Using Subclock to V and leave pin Open ...
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Prescalers The H8/3657 Series is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler 13-bit counter using the system clock (ø) as its input clock. Its prescaled outputs provide internal ...
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Note on Oscillators Oscillator characteristics are closely related to board design and should be carefully evaluated by the user for both mask ROM and ZTAT™ versions, referring to the oscillator element connection examples shown in this section. Oscillator circuit ...
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Section 5 Power-Down Modes 5.1 Overview The H8/3657 Series has eight modes of operation after a reset. These include seven power-down modes, in which power dissipation is significantly reduced. Table 5-1 gives a summary of the eight operating modes. Table ...
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Figure 5-1 shows the transitions among these operation modes. Table 5-2 indicates the internal states in each mode. Reset state Program halt state Standby mode *4 *1 instruction Watch mode Mode Transition Conditions (1) LSON MSON SSBY ...
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Table 5-2 Internal State in Each Operating Mode Active Mode High- Function Speed System clock oscillator Functions Subclock oscillator Functions CPU Instructions Functions operations Registers RAM I/O ports External IRQ Functions 0 interrupts IRQ 1 IRQ 2 IRQ 3 INT ...
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System Control Registers The operation mode is selected using the system control registers described in table 5-3. Table 5-3 System Control Registers Name System control register 1 System control register 2 1. System control register 1 (SYSCR1) Bit 7 ...
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Bits Standby timer select (STS2 to STS0) These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due ...
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System control register 2 (SYSCR2) Bit 7 — Initial value 1 Read/Write — SYSCR2 is an 8-bit read/write register for power-down mode control. Upon reset, SYSCR2 is initialized to H'E0. Bits Reserved bits These bits are ...
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Bit 3: Direct transfer on flag (DTON) This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after ...
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Bits 1 and 0: Subactive mode clock select (SA1 and SA0) These bits select the CPU clock rate (ø be modified in subactive mode. Bit 1 Bit 0 SA1 SA0 Description 0 0 ø ø /4 ...
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Sleep Mode 5.2.1 Transition to Sleep Mode 1. Transition to sleep (high-speed) mode The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1 and the ...
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Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared ...
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Oscillator Settling Time after Standby Mode is Cleared Bits STS2 to STS0 in SYSCR1 should be set as follows. • When a crystal oscillator is used The table below gives settings for various operating frequencies. Set bits STS2 to ...
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Watch Mode 5.4.1 Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA ...
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Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to ...
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Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A or IRQ LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, ...
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Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) Mode If the LSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared transition to active (medium-speed) mode results from IRQ IRQ ...
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Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can ...
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Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, ...
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Overview The H8/3657 has 60 kbytes of on-chip mask ROM or PROM. The H8/3656 has 48 kbytes of mask ROM. The H8/3655 has 40 kbytes of mask ROM. The H8/3654 has 32 kbytes of on-chip mask ROM. The H8/3653 ...
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PROM Mode 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C101 ...
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H8/3657 TFP-80C, TFP-80F FP-80A FP-80B ...
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Address in MCU mode H'0000 H'EDFF Note read in PROM mode, this address area returns unpredictable output data. When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF. If address H'EE00 and higher ...
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Programming The write, verify, and other modes are selected as shown in table 6-3 in H8/3657 PROM mode. Table 6-3 Mode Selection in H8/3657 PROM Mode Mode CE OE Write L H Verify L L Programming L L disabled ...
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Yes Write time Write time Error Figure 6-4 High-Speed, High-Reliability Programming Flow Chart Start Set write/verify mode 0. 12.5 V 0.3 V ...
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Table 6-4 and table 6-5 give the electrical characteristics in programming mode. Table 6-4 DC Characteristics (Conditions 6.0 V ±0. Item Input high level voltage OE, CE, PGM ...
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Table 6-5 AC Characteristics (Conditions 6.0 V ±0. Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time V setup time PP Programming pulse width ...
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Figure 6-5 shows a write/verify timing diagram. Address t AS Data Input data VPS VCS CES PGM OE t Note: * ...
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Programming Precautions • Use the specified programming voltage and timing. The programming voltage in PROM mode (V permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the ...
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Reliability of Programmed Data A highly effective way of assuring data retention characteristics after programming is to screen the chips by baking them at a temperature of 150°C. This quickly eliminates PROM memory cells prone to initial data retention ...
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Overview The H8/3657 Series has 1 kbyte or 2 kbytes of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 ...
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Overview The H8/3657 Series is provided with six 8-bit I/O ports, one 6-bit I/O port, one 5-bit I/O ports, and one 8-bit input-only port. Table 8-1 indicates the functions of each port. Each port has of a port control ...
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Table 8-1 Port Functions (cont) Port Description Port 6 • 8-bit I/O port Port 7 • 8-bit I/O port Port 8 • 8-bit I/O port Port 9 • 5-bit I/O port Port B • 8-bit input port Pins Other Functions ...
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Port 1 8.2.1 Overview Port 8-bit I/O port. Figure 8-1 shows its pin configuration. 8.2.2 Register Configuration and Description Table 8-2 shows the port 1 register configuration. Table 8-2 Port 1 Registers Name Port data register ...
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Port data register 1 (PDR1) Bit Initial value 0 Read/Write R/W R/W PDR1 is an 8-bit register that stores data for port 1 pins P1 bits are set to 1, the values stored in PDR1 ...
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Port pull-up control register 1 (PUCR1) Bit 7 PUCR1 PUCR1 7 Initial value 0 Read/Write R/W R/W PUCR1 controls whether the MOS pull-up of each of the port 1 pins P1 a PCR1 bit is cleared to 0, setting ...
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Bit 6: P1 /IRQ pin function switch (IRQ2 This bit selects whether pin P1 Bit 6 IRQ2 Description 0 Functions Functions as IRQ Note: Rising or falling edge sensing can be designated for IRQ Bit ...
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Bit 0: P1 /TMOW pin function switch (TMOW) 0 This bit selects whether pin P1 Bit 0 TMOW Description 0 Functions Functions as TMOW output pin 8.2.3 Pin Functions Table 8-3 shows the port 1 pin functions. ...
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Table 8-3 Port 1 Pin Functions (cont) Pin Pin Functions and Selection Method P1 /TMOW The pin function depends on bit TMOW in PMR1 and bit PCR1 0 TMOW PCR1 Pin function Note: * Don’t care 8.2.4 Pin States Table ...
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Port 2 8.3.1 Overview Port 8-bit I/O port, configured as shown in figure 8-2. 8.3.2 Register Configuration and Description Table 8-5 shows the port 2 register configuration. Table 8-5 Port 2 Registers Name Port data register ...
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Port control register 2 (PCR2) Bit 7 PCR2 PCR2 7 Initial value 0 Read/Write W PCR2 is an 8-bit register for controlling whether each of the port 2 pins P2 input pin or output pin. Setting a PCR2 bit ...
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Pin Functions Table 8-6 shows the port 2 pin functions. Table 8-6 Port 2 Pin Functions Pin Pin Functions and Selection Method The pin function depends on bit PCR2 7 3 PCR2 Pin function P2 /TXD ...
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Pin States Table 8-7 shows the port 2 pin states in each operating mode. Table 8-7 Port 2 Pin States Pins Reset High /TXD impedance previous 2 P2 /RXD 1 P2 /SCK 0 ...
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Port 3 8.4.1 Overview Port 6-bit I/O port, configured as shown in figure 8-3. 8.4.2 Register Configuration and Description Table 8-8 shows the port 3 register configuration. Table 8-8 Port 3 Registers Name Port data register ...
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Port data register 3 (PDR3) Bit 7 — * Initial value 0 Read/Write — Note: * Bits are reserved; they are always read as 0 and cannot be modified. PDR3 is an 8-bit register that stores ...
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Port pull-up control register 3 (PUCR3) Bit 7 — * Initial value 0 Read/Write — Note: * Bits are reserved; they are always read as 0 and cannot be modified. PUCR3 controls whether the MOS pull-up ...
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Bit 1: P3 /SI pin function switch (SI1 This bit selects whether pin P3 Bit 1 SI1 Description 0 Functions Functions Bit 0: P3 /SCK pin function switch (SCK1 This ...
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Bit 1: Reserved bit Bit 1 is reserved always read as 0 and cannot be modified. Bit 0: P3 /SO pin PMOS control (POF1 This bit controls the PMOS transistor in the P3 Bit 0 POF1 ...
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Table 8-9 Port 3 Pin Functions (cont) Pin Pin Functions and Selection Method P3 /SCK The pin function depends on bit SCK1 in PMR3, bit CKS3 in SCR1, and bit 0 1 PCR3 in PCR3. 0 SCK1 CKS3 PCR3 Pin ...
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Port 5 8.5.1 Overview Port 8-bit I/O port, configured as shown in figure 8-4. 8.5.2 Register Configuration and Description Table 8-11 shows the port 5 register configuration. Table 8-11 Port 5 Registers Name Port data register ...
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Port data register 5 (PDR5) Bit Initial value 0 Read/Write R/W PDR5 is an 8-bit register that stores data for port 5 pins P5 bits are set to 1, the values stored in PDR5 are read, ...
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Pin Functions Table 8-12 shows the port 5 pin functions. Table 8-12 Port 5 Pin Functions Pin Pin Functions and Selection Method P5 /INT The pin function depends on bit PCR5 7 7 PCR5 Pin function P5 /INT /TMIB ...
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Pin States Table 8-13 shows the port 5 pin states in each operating mode. Table 8-13 Port 5 Pin States Pins Reset Sleep P5 /INT to High- Retains /INT impedance previous 0 0 state Note: * ...
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Port 6 8.6.1 Overview Port 8-bit I/O port. The port 6 pin configuration is shown in figure 8-5. 8.6.2 Register Configuration and Description Table 8-14 shows the port 6 register configuration. Table 8-14 Port 6 Registers ...
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Port data register 6 (PDR6) Bit Initial value 0 Read/Write R/W PDR6 is an 8-bit register that stores data for port 6 pins P6 Upon reset, PDR6 is initialized to H'00. 2. Port control register 6 ...
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Pin Functions Table 8-15 shows the port 6 pin functions. Table 8-15 Port 6 Pin Functions Pin Pin Functions and Selection Method The pin function depends on bit PCR6 7 0 PCR6 Pin function 8.6.4 Pin ...
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Port 7 8.7.1 Overview Port 8-bit I/O port, configured as shown in figure 8-6. 8.7.2 Register Configuration and Description Table 8-17 shows the port 7 register configuration. Table 8-17 Port 7 Registers Name Port data register ...
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Port data register 7 (PDR7) Bit Initial value 0 Read/Write R/W R/W PDR7 is an 8-bit register that stores data for port 7 pins P7 bits are set to 1, the values stored in PDR7 ...
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Pin Functions Table 8-18 shows the port 7 pin functions. Table 8-18 Port 7 Pin Functions Pin Pin Functions and Selection Method P7 , The pin function depends on bit PCR7 PCR7 0 Pin ...
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Port 8 8.8.1 Overview Port 8-bit I/O port configured as shown in figure 8-7. 8.8.2 Register Configuration and Description Table 8-20 shows the port 8 register configuration. Table 8-20 Port 8 Registers Name Port data register ...
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Port data register 8 (PDR8) Bit Initial value 0 Read/Write R/W PDR8 is an 8-bit register that stores data for port 8 pins P8 bits are set to 1, the values stored in PDR8 are read, ...
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Pin Functions Table 8-24 shows the port 8 pin functions. Table 8-21 Port 8 Pin Functions Pin Pin Functions and Selection Method P8 The pin function depends on bit PCR8 7 PCR8 Pin function P8 /FTID The pin function ...
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Table 8-21 Port 8 Pin Functions (cont) Pin Pin Functions and Selection Method P8 /FTOA The pin function depends on bit PCR8 1 OEA PCR8 Pin function P8 /FTCI The pin function depends on bit PCR8 0 PCR8 Pin function ...
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Port 9 8.9.1 Overview Port 5-bit I/O port, configured as shown in figure 8-8. 8.9.2 Register Configuration and Description Table 8-23 shows the port 9 register configuration. Table 8-23 Port 9 Registers Name Port data register ...
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Port control register 9 (PCR9) Bit 7 — Initial value 1 Read/Write — PCR9 controls whether each of the port 9 pins P9 Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while clearing the ...
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Port B 8.10.1 Overview Port 8-bit input-only port, configured as shown in figure 8-9. 8.10.2 Register Configuration and Description Table 8-26 shows the port B register configuration. Table 8-26 Port B Register Name Port data register ...
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Pin Functions Table 8-27 shows the port B pin functions. Table 8-27 Port B Pin Functions Pin Pin Functions and Selection Method PB /AN Always as below Pin function 8.10.4 Pin States Table 8-28 shows the port ...
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Overview The H8/3657 Series provides five timers: timers A, B1 and a watchdog timer. The functions of these timers are outlined in table 9-1. Table 9-1 Timer Functions Name Functions Timer A • 8-bit interval timer • ...
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Timer A 9.2.1 Overview Timer 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768-kHz crystal oscillator is connected. A clock signal divided from 32.768 kHz or ...
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Block diagram Figure 9-1 shows a block diagram of timer A. ø 1/4 W ø ø /32 W ø /16 W ø ø TMOW ø/32 ø/16 ø/8 ø/4 ø Notation: TMA: Timer mode ...
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Register configuration Table 9-3 shows the register configuration of timer A. Table 9-3 Timer A Registers Name Timer mode register A Timer counter A 9.2.2 Register Descriptions 1. Timer mode register A (TMA) Bit 7 TMA7 Initial value 0 ...
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Bit 4: Reserved bit Bit 4 is reserved always read as 1, and cannot be modified. Bits Internal clock select (TMA3 to TMA0) Bits select the clock input to TCA. The selection ...
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Timer counter A (TCA) Bit 7 TCA7 Initial value 0 Read/Write R TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to ...
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Real-time clock time base operation When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting clock signals output by prescaler W. The overflow period of timer A is set ...
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Timer B1 9.3.1 Overview Timer 8-bit timer that increments each time a clock pulse is input. This timer has two operation modes, interval and auto reload. 1. Features Features of timer B1 are given below. • ...
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Pin configuration Table 9-5 shows the timer B1 pin configuration. Table 9-5 Pin Configuration Name Abbrev. Timer B1 event input TMIB 4. Register configuration Table 9-6 shows the register configuration of timer B1. Table 9-6 Timer B1 Registers Name ...
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Bits Reserved bits Bits are reserved; they are always read as 1, and cannot be modified. Bits Clock select (TMB12 to TMB10) Bits select the clock input to ...
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Timer load register B1 (TLB1) Bit 7 TLB17 Initial value 0 Read/Write W TLB1 is an 8-bit write-only register for setting the reload value of timer counter B1 (TCB1). When a reload value is set in TLB1, the same ...
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Auto-reload timer operation Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as an 8-bit auto-reload timer. When a reload value is set in TLB1, the same value is loaded into TCB1, becoming the value from ...
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Timer V 9.4.1 Overview Timer 8-bit timer based on an 8-bit counter. Timer V counts external events. Also compare match signals can be used to reset the counter, request an interrupt, or output a pulse signal ...
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Block diagram Figure 9-3 shows a block diagram of timer V. TRGV TMCIV Clock select ø PSS Clear control TMRIV TMOV Notation: TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status ...
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Pin configuration Table 9-8 shows the timer V pin configuration. Table 9-8 Pin Configuration Name Timer V output Timer V clock input Timer V reset input Trigger input 4. Register configuration Table 9-9 shows the register configuration of timer ...
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Register Descriptions 1. Timer counter V (TCNTV) Bit 7 TCNTV TCNTV 7 Initial value 0 Read/Write R/W TCNTV is an 8-bit read/write up-counter which is incremented by internal or external clock input. The clock source is selected by bits ...
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Timer control register V0 (TCRV0) Bit 7 CMIEB CMIEA Initial value 0 Read/Write R/W TCRV0 is an 8-bit read/write register that selects the TCNTV input clock, controls the clearing of TCNTV, and enables interrupts. TCRV0 is initialized to H'00 ...
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Bits 4 and 3: Counter clear 1 and 0 (CCLR1, CCLR0) Bits 4 and 3 specify whether or not to clear TCNTV, and select compare match external reset input. When clearing is specified, if TRGE ...
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Timer control/status register V (TCSRV) Bit 7 CMFB Initial value 0 * Read/Write R/(W) Note: * Bits can be only written with 0, for flag clearing. TCSRV is an 8-bit register that sets compare match flags ...
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Bit 5: Timer overflow flag (OVF) Bit status flag indicating that TCNTV has overflowed from H'FF to H'00. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 5 OVF ...
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Timer control register V1 (TCRV1) Bit 7 — Initial value 1 Read/Write — TCRV1 is an 8-bit read/write register that selects the valid edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV. TCRV1 ...
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Bit 1: Reserved bit Bit 1 is reserved always read as 1, and cannot be modified. Bit 0: Internal clock select 0 (ICKS0) Bit 0 and bits CKS2 to CKS0 in TCRV0 select the TCNTV clock source. For ...
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TCNTV increment timing TCNTV is incremented by an input (internal or external) clock. • Internal clock One of six clocks (ø/128, ø/64, ø/32, ø/16, ø/8, ø/4) divided from the system clock (ø) can be selected by bits CKS2 to ...
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TMCIV (external clock input pin) TCNTV input clock N – 1 TCNTV Figure 9-5 Increment Timing with External Clock 3. Overflow flag set timing The overflow flag (OVF) is set to 1 when TCNTV overflows from H'FF to H'00. ...
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Compare match flag set timing Compare match flag (CMFA or CMFB) is set to 1 when TCNTV matches TCORA or TCORB. The internal compare-match signal is generated in the last state in which the values match ...
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TCNTV clear timing by compare match TCNTV can be cleared by compare match selected by bits CCLR1 and CCLR0 in TCRV0. Figure 9-9 shows the timing. ø Compare match A signal TCNTV Figure 9-9 Clear ...
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Timer V Operation Modes Table 9-10 summarizes the timer V operation states. Table 9-10 Timer V Operation States Operation Mode Reset TCNTV Reset TCRV0, TCRV1 Reset TCORA, TCORB Reset TCSRV Reset 9.4.5 Interrupt Sources Timer V has three interrupt ...
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Application Examples 1. Pulse output with arbitrary duty cycle Figure 9-11 shows an example of output of pulses with an arbitrary duty cycle. To set up this output: • Clear bit CCLR1 to 0 and set bit CCLR0 to ...
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After these settings, a pulse waveform will be output without further software intervention, with a delay determined by TCORA from the TRGV input, and a pulse width determined by (TCORB – TCORA). H'FF TCORB TCORA H'00 TRGV TMOV Compare match ...
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Application Notes The following types of contention can occur in timer V operation. 1. Contention between TCNTV write and counter clear If a TCNTV clear signal is generated in the T precedence and the write to the counter is ...
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Contention between TCNTV write and increment If a TCNTV increment clock signal is generated in the T takes precedence and the counter is not incremented. Figure 9-14 shows the timing. ø Address Internal write signal TCNTV clock TCNTV Figure ...
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Contention between TCOR write and compare match If a compare match is generated in the T TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure 9-15 shows the timing. ø Address Internal write signal TCNTV ...
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Contention between compare match A and B If compare match A and B occur simultaneously, any conflict between the output selections for compare match A and compare match B is resolved by following the priority order in table 9-12. ...
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Table 9-13 Internal Clock Switching and TCNTV Operation Clock Levels Before and After Modifying No. Bits CKS1 and CKS0 1 Goes from low level to 1 low level* 2 Goes from low to high Notes: 1. Including a transition from ...
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Table 9-13 Internal Clock Switching and TCNTV Operation (cont) Clock Levels Before and After Modifying No. Bits CKS1 and CKS0 3 Goes from high level to *1 low level 4 Goes from high to high Notes: 1. Including a transition ...
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Timer X 9.5.1 Overview Timer X is based on a 16-bit free-running counter (FRC). It can output two independent waveforms, or measure input pulse widths and external clock periods. 1. Features Features of timer X are given below. • ...
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Block diagram Figure 9-16 shows a block diagram of timer X. FTIA Input FTIB capture FTIC control FTID FTCI ø PSS FTOA FTOB Notation: TIER: Timer interrupt enable register TCSRX: Timer control/status register X FRC: Free-running counter OCRA: Output ...
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Pin configuration Table 9-14 shows the timer X pin configuration. Table 9-14 Pin Configuration Name Counter clock input Output compare A Output compare B Input capture A Input capture B Input capture C Input capture D Abbrev. I/O FTCI ...