MT9300BV Zarlink Semiconductor, MT9300BV Datasheet
MT9300BV
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MT9300BV Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2000-2006, Zarlink Semiconductor Inc. All Rights Reserved. Multi-Channel Voice Echo Canceller Ordering Information MT9300BL MT9300BV MT9300BV2 **Pb Free Tin/Silver/Copper • Protection against narrow band signal divergence • Offset nulling of all PCM channels • ...
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... ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds echo cancellation. This provides 32 channels of 64 milliseconds to 16 channels of 128 milliseconds echo cancellation or any combination of the two configurations. The MT9300B supports ITU-T G.165 and G.164 tone disable requirements. MT9300B 2 Zarlink Semiconductor Inc. Data Sheet ...
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... ICO V SS DD1 SS V Rin V Rout V Sin SS SS DD1 DD2 SS DD1 SS DD1 DD2 DD1 SS DD1 SS DD1 MT9300BV ...
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... RESET V 159 DD1 MT9300B 109 107 105 103 101 MT9300BL Figure 3 - 160 Pin MQFP 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Interrupt Request (Open Drain Output). This output goes low when an interrupt occurs in any channel. IRQ returns high when all the interrupts have been read from the Interrupt FIFO Register. A pull-up resistor (1 K typical) is required at this output. 5 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Receive PCM Signal Input (Input). Port 1 TDM data input streams. Rin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. 111 F0i Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS or GCI interface specifications. 6 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Control and Status Registers to their default power-up values. V These LBGA pins should be wired to V DD2 FUTURE USE. If the customer does not intend to use future generation of the device, then these pins should be NO CONNECTS 7 Zarlink Semiconductor Inc. Data Sheet Description . SS . DD1 = 1.8 V for DD2 ...
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... Offset Linear/ + Processor Null - Microprocessor Interface Double-Talk Detector Narrow-Band MuteR Detector Offset 12dB Null Attenuator Echo Canceller (N), where 0 8 Zarlink Semiconductor Inc. Data Sheet Sout /A-Law (channel N) MuteS Path Change Detector GCI PORT1 Disable Tone Detector /A-Law/ Rin Linear (channel ...
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... PathClr bit in Control Register A3/B3 to "1". With path clearing turned on, the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled with zeroes) upon detection of a major path change. MT9300B Lsin > Lrin + 20log (DTDT) 10 DTDT = hex(DTDT * 32768) (hex) (dec) 9 Zarlink Semiconductor Inc. Data Sheet ...
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... If the disable tone is present for a minimum of 400 milliseconds, with or without phase reversal, the Tone Detector will trigger. MT9300B TSUP = Lrin + 20log (NLPTHR) 10 NLPTHR = hex(NLPTHR * 32768) (hex) (dec) (hex) 10 Zarlink Semiconductor Inc. Data Sheet will reduce the noise level, values greater ...
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... The Instability Detector is activated by setting the RingClr bit in Control Register A3/B3 to "1". MT9300B Tone Detector ECA Status reg TD bit Tone Detector Echo Canceller A Tone Detector ECB Status reg TD Tone Detector Echo Canceller B Figure 5 - Disable Tone Detection 11 Zarlink Semiconductor Inc. Data Sheet bit ...
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... E.C.A b) Extended Delay Configuration (128ms) + Sin - echo path Adaptive Filter (64 ms) Rout PORT2 E.C.A c) Back-to-Back Configuration (64 ms) Figure 6 - Device Configuration 12 Zarlink Semiconductor Inc. Data Sheet + Sout - Adaptive Filter (128 ms) Rin PORT1 Optional -12dB pad Sout Optional -12dB pad Adaptive echo path Filter (64 ms) ...
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... Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with quiet code. +Zero (quiet code) MT9300B LINEAR SIGN/ CCITT (G.711) 16 bits MAGNITUDE 2’s -Law -Law complement A-Law 0000h 80h FFh Table 1 - Quiet PCM Code Assignment 13 Zarlink Semiconductor Inc. Data Sheet A-Law D5h ...
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... PCM Send and Receive channels, as illustrated in Figure 4. F0i ST-Bus F0i GCI interface Rin/Sin Channel 0 Rout/Sout Note: Refer to Figures 9 and 10 for timing details Figure 7 - ST-BUS and GCI Interface Channel Assignment for 2 Mb/s Data Streams MT9300B 125 sec Channel 1 Channel 30 14 Zarlink Semiconductor Inc. Data Sheet Channel 31 ...
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... Sin Peak Detect Reg 2Eh Error Peak Detect Reg Error Peak Detect Reg 30h Reserved Reserved 32h DTDT Reg DTDT Reg 34h Reserved Reserved 36h NLPTHR NLPTHR 38h Step Size, MU Step Size, MU 3Ah Reserved Reserved 3Ch Reserved Reserved 3Eh 15 Zarlink Semiconductor Inc. Data Sheet ...
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... Channel Ctrl/Stat Registers 0060H --> Channel 30 Ctrl/Stat Registers 03C0H --> Channel 31 Ctrl/Stat Registers 03E0H --> Main Control Registers <15:0> 0400H --> 040FH 0410H Interrupt FIFO Register 0411H Test Register Figure 9 - Memory Mapping 16 Zarlink Semiconductor Inc. Data Sheet 001FH 003FH 005FH 007FH 03DFH 03FFH ...
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... MT9300B Channel Group Table 2 - Group and Channel allocation 17 Zarlink Semiconductor Inc. Data Sheet Channel 16, 17 18, 19 20, 21 22, 23 24, 25 26, 27 28 Base Address+ ...
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... The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrent with the operation of the device and without interfering with the on-chip logic. MT9300B Nb_of_groups + 40 Zarlink Semiconductor Inc. Data Sheet ...
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... The Bypass register is a single stage shift register that provides a one-bit path from TDI TDO. • Device Identification register The Device Identification register provides access to the following encoded information: device version number, part number and manufacturer's name. MT9300B 19 Zarlink Semiconductor Inc. Data Sheet . SS ...
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... Note: Do not enable both Extended-Delay and BBM configurations at the same time. Control Register B1 bit reserved bit and should be written “0”. MT9300B Read/Write Address AdpDis 0 ExtDl Reset Value: Read/Write Address Reset Value: AdpDis 1 0 Description 20 Zarlink Semiconductor Inc. Data Sheet + Base Address Base Address ...
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... When high, data on Sout is muted to quiet code. When low, Sout carries active code. 0 MuteR When high, data on Rout is muted to quiet code. When low, Rout carries active code. MT9300B Read/Write Address: 01 Read/Write Address MuteS MuteR Reset Value: Description 21 Zarlink Semiconductor Inc. Data Sheet + Base Address H + Base Address ...
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... Logic high indicates the presence of a narrow-band signal on Rin. MT9300B Read Address: Read Address TDG NB Reset Value: Description Read Address: Read Address TDG NB Reset Value: Description 22 Zarlink Semiconductor Inc. Data Sheet 02 + Base Address Base Address Base Address Base Address ...
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... FIR filter. The valid range 7-0 £ 128 in extended-delay mode. The default value Step Size (SS)] where 7-0 =4, then the exponential decay start value is 512 - [NS 2-0 23 Zarlink Semiconductor Inc. Data Sheet + Base Address H + Base Address H Power Reset Value Base Address ...
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... When high, the path change detector is activated. When low, the path change detector is disabled. 0 res Reserved bit. Must always be set to zero for normal operation. MT9300B Read/Write Address: 08 Read/Write Address PathDet res Reset Value: Description 24 Zarlink Semiconductor Inc. Data Sheet + Base Address H + Base Address ...
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... Read Address: 0E Read Address Zarlink Semiconductor Inc. Data Sheet + Base Address H + Base Address H Power Reset Value N/A + Base Address H + Base Address H Power Reset Value N/A + Base Address H + Base Address H Power Reset Value N/A + Base Address ...
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... DTDT DTDT DTDT DTDT DTDT DTDT Zarlink Semiconductor Inc. Data Sheet + Base Address H + Base Address H Power Reset Value N/A + Base Address H + Base Address H Power Reset Value N/A + Base Address H + Base Address H Power Reset Value 48 H (DTDT) ...
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... Read/Write Address: 1A Read/Write Address (MU Zarlink Semiconductor Inc. Data Sheet + Base Address H + Base Address H Power Reset Value Base Address H + Base Address H Power Reset Value Base Address H + Base Address H Power Reset Value 40 H ...
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... A/m Law: When high, both Echo Cancellers A and B for a given group, accept A-Law companded PCM code. When low, both Echo Cancellers A and B for a given group, accept m-Law companded PCM code. MT9300B Read/Write Address: 400 1 0 LAW PWUP Reset Value: Description . 28 Zarlink Semiconductor Inc. Data Sheet ...
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... Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application. MT9300B Read/Write Address: 400 1 0 LAW PWUP Reset Value: Description 29 Zarlink Semiconductor Inc. Data Sheet ...
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... Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Description 30 Zarlink Semiconductor Inc. Data Sheet 00 H 401 H 402 H 403 H 404 H 405 H 406 H ...
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... Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Description 31 Zarlink Semiconductor Inc. Data Sheet 00 H 401 H 402 H 403 H 404 H 405 H 406 H ...
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... Interrupt FIFO Register. When low, normal operation is selected. MT9300B Read Address Reset Value: Description Read/Write Address: 411 1 0 res Tirq Reset Value: Description 32 Zarlink Semiconductor Inc. Data Sheet 410 (Read only ...
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... C V 0.7V IH DD1 V 0. -30 - 0.8V OH DD1 V 0 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0.3 5 0.3 V +0.5 SS DD1 V - 0.3 5 2.0 -55 150 Units Test Conditions DD1 V V DD1 ) unless otherwise stated. Units Test Conditions A RESET = 0 ...
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... Serial Streams for ST-BUS and GCI Backplanes ‡ Sym. Min. Typ. Max SIS t 10 SIH t 60 SOD t 30 ODE , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet Units Conditions Units Notes Units Test Conditions ...
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... Bit 6, Channel 0 Bit 5, Channel Bit 1, Channel 0 Bit 2, Channel 0 t SIH Bit 1, Channel 0 Bit 2, Channel ODE ODE V Valid Data HiZ HiZ TT 35 Zarlink Semiconductor Inc. Data Sheet ...
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... DDR t 3 DHR t 0 DSW t 0 DHW t AKD t 0 AKH t 20 IRD , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet ). unless otherwise stated. SS Units Notes MHz MHz Max. Units Test Conditions ...
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... READ D0-D7 WRITE DTA IRQ Figure 14 - Motorola Non-Multiplexed Bus Timing MT9300B t CSS t RWS t ADS VALID ADDRESS t DDR VALID READ DATA t DSW VALID WRITE DATA t AKD t IRD 37 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH DHR DHW ...
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