HD6472655F Renesas Electronics Corporation., HD6472655F Datasheet
HD6472655F
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HD6472655F Summary of contents
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REJ09B0331-0500 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 Rev. 5.00 Revision Date: Sep ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Rev. 5.00 Sep 14, 2006 page iv of xxviii ...
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The H8S/2655 Group is a series of high-performance microcontrollers with a 32-bit H8S/2600 CPU core, and a set of on-chip supporting functions required for system configuration. The H8S/2600 CPU can execute basic instructions in one state, and is provided with ...
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Rev. 5.00 Sep 14, 2006 page vi of xxviii ...
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Main Revisions for This Edition Item Page All — 5.3.1 External 102 Interrupts 5.4.6 Interrupt 122 Exception Handling Sequence Figure 5.11 Interrupt Exception Handling 7.2.4 DMA Control 227 Register (CMACR) 9.4.3 Pin Functions 373 Table 9.7 Port 3 Pin Functions ...
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Item Page 10.2.3 Timer I/O 451 Control Register (TIOR) 454 14.2.6 Serial Control 598 Register (SCR) Rev. 5.00 Sep 14, 2006 page viii of xxviii Revision (See Manual for Details) Bits I/O Control (IOA3 ...
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Item Page 14.2.8 Bit Rate 601 Register (BRR) Table 14.3 BRR Setting for Various Bit Rates (Asynchronous Mode) 602 15.2.3 Serial Mode 656 Register (SMR) 657 16.6 Usage Notes 707 19.1.1 Block Diagram 721 Figure 19.1 Block Diagram of ROM ...
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Item Page B.2 Functions 926 931 Rev. 5.00 Sep 14, 2006 page x of xxviii Revision (See Manual for Details) DMABCRH, DMABCRL H'FF06, H'FF07 DMAC Figure amended Full address mode (cont) Bit : DMABCRL : DTME1 ...
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Item Page B.2 Functions 998 1004 1010 Appendix G Package 1058 Dimensions Figure G.1 TFP-120 Package Dimensions Figure G.2 FP-128 1059 Package Dimensions Revision (See Manual for Details) TSR0 H'FFD5 TPU0 Figure amended TGR Input Capture/Output Compare Flag A TGR ...
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Rev. 5.00 Sep 14, 2006 page xii of xxviii ...
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Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Block Diagram .................................................................................................................. 1.3 Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions in Each Operating Mode ............................................................... 1.3.3 Pin Functions ....................................................................................................... 14 Section 2 CPU ...................................................................................................................... 23 2.1 Overview........................................................................................................................... 23 2.1.1 Features................................................................................................................ ...
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Basic Timing ..................................................................................................................... 67 2.9.1 Overview.............................................................................................................. 67 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 67 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 69 2.9.4 External Address Space Access Timing .............................................................. 70 Section 3 MCU Operating Modes 3.1 Overview........................................................................................................................... 71 3.1.1 ...
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Section 5 Interrupt Controller 5.1 Overview........................................................................................................................... 93 5.1.1 Features................................................................................................................ 93 5.1.2 Block Diagram ..................................................................................................... 94 5.1.3 Pin Configuration................................................................................................. 94 5.1.4 Register Configuration......................................................................................... 95 5.2 Register Descriptions ........................................................................................................ 96 5.2.1 System Control Register (SYSCR) ...................................................................... 96 5.2.2 Interrupt Control Registers A ...
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Register Descriptions ........................................................................................................ 135 6.2.1 Bus Width Control Register (ABWCR)............................................................... 135 6.2.2 Access State Control Register (ASTCR) ............................................................. 136 6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 137 6.2.4 Bus Control Register H (BCRH).......................................................................... 140 6.2.5 Bus Control ...
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Basic Timing........................................................................................................ 192 6.6.6 Precharge State Control ....................................................................................... 193 6.6.7 Wait Control ........................................................................................................ 194 6.6.8 Burst Operation.................................................................................................... 196 6.6.9 Refresh Control.................................................................................................... 199 6.6.10 Power-On Sequence............................................................................................. 200 6.7 DMAC Single Address Mode and DRAM/PSRAM Interface.......................................... 201 6.7.1 When DDS = ...
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DMA Band Control Register (DMABCR)........................................................... 231 7.3 Register Descriptions (2) (Full Address Mode) ................................................................ 237 7.3.1 Memory Address Register (MAR)....................................................................... 237 7.3.2 I/O Address Register (IOAR) .............................................................................. 238 7.3.3 Execute Transfer Count Register (ETCR) ........................................................... 238 7.3.4 DMA Control ...
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DTC Source Address Register (SAR).................................................................. 315 8.2.4 DTC Destination Address Register (DAR).......................................................... 315 8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 316 8.2.6 DTC Transfer Count Register B (CRB)............................................................... 316 8.2.7 DTC Enable Registers (DTCER) ......................................................................... 317 8.2.8 DTC ...
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Port 5................................................................................................................................. 376 9.6.1 Overview.............................................................................................................. 376 9.6.2 Register Configuration......................................................................................... 376 9.6.3 Pin Functions ....................................................................................................... 379 9.7 Port 6................................................................................................................................. 380 9.7.1 Overview.............................................................................................................. 380 9.7.2 Register Configuration......................................................................................... 381 9.7.3 Pin Functions ....................................................................................................... 383 9.8 Port A................................................................................................................................ 385 9.8.1 Overview.............................................................................................................. 385 9.8.2 ...
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Section 10 16-Bit Timer Pulse Unit (TPU) 10.1 Overview........................................................................................................................... 427 10.1.1 Features................................................................................................................ 427 10.1.2 Block Diagram ..................................................................................................... 431 10.1.3 Pin Configuration................................................................................................. 432 10.1.4 Register Configuration......................................................................................... 434 10.2 Register Descriptions ........................................................................................................ 436 10.2.1 Timer Control Register (TCR) ............................................................................. 436 10.2.2 Timer ...
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Pin Configuration................................................................................................. 521 11.1.4 Registers............................................................................................................... 522 11.2 Register Descriptions ........................................................................................................ 523 11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 523 11.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 524 11.2.3 Next Data Registers H and ...
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Operation with Cascaded Connection.................................................................. 560 12.4 Interrupt Sources............................................................................................................... 561 12.5 Sample Application........................................................................................................... 562 12.6 Usage Notes ...................................................................................................................... 563 12.6.1 Contention between TCNT Write and Clear........................................................ 563 12.6.2 Contention between TCNT Write and Increment ................................................ 564 12.6.3 Contention between TCOR ...
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Receive Shift Register (RSR) .............................................................................. 588 14.2.2 Receive Data Register (RDR) .............................................................................. 588 14.2.3 Transmit Shift Register (TSR) ............................................................................. 589 14.2.4 Transmit Data Register (TDR)............................................................................. 589 14.2.5 Serial Mode Register (SMR)................................................................................ 590 14.2.6 Serial Control Register (SCR).............................................................................. 593 14.2.7 ...
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Section 16 A/D Converter 16.1 Overview........................................................................................................................... 679 16.1.1 Features................................................................................................................ 679 16.1.2 Block Diagram ..................................................................................................... 680 16.1.3 Pin Configuration................................................................................................. 680 16.1.4 Register Configuration......................................................................................... 681 16.2 Register Descriptions ........................................................................................................ 682 16.2.1 A/D Data Registers (ADDRA to ADDRH).............................................. 682 16.2.2 ...
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Register Descriptions ........................................................................................................ 718 18.2.1 System Control Register (SYSCR) ...................................................................... 718 18.3 Operation .......................................................................................................................... 719 18.4 Usage Notes ...................................................................................................................... 719 Section 19 ROM .................................................................................................................. 721 19.1 Overview........................................................................................................................... 721 19.1.1 Block Diagram ..................................................................................................... 721 19.1.2 Register Configuration......................................................................................... 722 19.2 Register ...
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Medium-Speed Mode........................................................................................................ 748 21.4 Sleep Mode ....................................................................................................................... 749 21.5 Module Stop Mode ........................................................................................................... 750 21.5.1 Module Stop Mode .............................................................................................. 750 21.5.2 Usage Notes ......................................................................................................... 752 21.6 Software Standby Mode.................................................................................................... 753 21.6.1 Software Standby Mode....................................................................................... 753 21.6.2 Clearing Software Standby ...
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Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram ..................................................................................................... 1012 C.2 Port 2 Block Diagram ..................................................................................................... 1015 C.3 Port 3 Block Diagram ..................................................................................................... 1019 C.4 Port 4 Block Diagram ..................................................................................................... 1022 C.5 Port 5 Block Diagram ..................................................................................................... ...
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Overview The H8S/2655 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2600 CPU, employing Renesas Technology proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2600 CPU has an internal 32-bit architecture, is provided with ...
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Section 1 Overview Table 1.1 Overview Item Specification CPU General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation suitable for realtime control Maximum clock rate: 20 MHz High-speed arithmetic operations 8/16/32-bit ...
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Item Specification DMA controller Choice of short address mode or full address mode (DMAC) 4 channels in short address mode 2 channels in full address mode Transfer possible in repeat mode, block transfer mode, etc. Single address mode transfer possible ...
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Section 1 Overview Item Specification D/A converter Resolution: 8 bits Output: 2 channels I/O ports 87 I/O pins, 8 input-only pins Memory PROM or mask ROM High-speed static RAM Product Name H8S/2655 H8S/2653 Nine external interrupt pins (NMI, IRQ Interrupt ...
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... Specification Clock pulse Built-in duty correction circuit generator Packages 120-pin plastic TQFP (TFP-120) 128-pin plastic QFP (FP-128) Product lineup 5 V Version ( ±10%) CC HD6472655TE HD6472655F HD6432655(***)TE HD6432655(***)F HD6432653(***)TE HD6432653(***)F Legend: Marked (***) is ROM code. Model Name Low-Voltage Version (V = 2 HD6472655VTE HD6472655VF ...
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Section 1 Overview 1.2 Block Diagram Figure 1.1 shows an internal block diagram of the H8S/2655 Group EXTAL XTAL STBY RES WDTOVF NMI / /RD 5 Port PF ...
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Pin Description 1.3.1 Pin Arrangement Figures 1.2 and 1.3 show the pin arrangement of the H8S/2655 Group ...
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Section 1 Overview ...
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Pin Functions in Each Operating Mode Table 1.2 shows the pin functions of the H8S/2655 Group in each of the operating modes. Table 1.2 Pin Functions in Each Operating Mode Pin No. TFP-120 FP-128 Mode 1 Mode 2 1 ...
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Section 1 Overview Pin No. TFP-120 FP-128 Mode 1 Mode /IRQ /IRQ /IRQ /IRQ — ...
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Pin No. TFP-120 FP-128 Mode 1 Mode /RxD /RxD /SCK /SCK ...
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Section 1 Overview Pin No. TFP-120 FP-128 Mode 1 Mode / TIOCA3 TIOCA3 WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF RES RES NMI NMI STBY ...
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Pin No. TFP-120 FP-128 Mode 1 Mode 2 100 110 P4 / 101 111 P4 / 102 112 P4 / 103 113 AV ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.3 outlines the pin functions of the H8S/2655 Group. Table 1.3 Pin Functions Type Symbol Power supply Clock XTAL EXTAL Rev. 5.00 Sep 14, 2006 page 14 of 1060 ...
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Type Symbol Operating mode control MD 0 RES System control STBY BREQ BREQO BACK Pin No. TFP-120 FP-128 I/O 115 to 125 to Input 113 123 73 81 Input 75 83 Input 88 96 Input 86 94 ...
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Section 1 Overview Type Symbol Interrupts NMI IRQ to 7 IRQ 0 Address bus Data bus Bus control HWR Rev. 5.00 Sep 14, ...
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Type Symbol LWR Bus control CAS/ OE LCAS WAIT DREQ DMA controller , 1 DREQ (DMAC) 0 TEND , 1 TEND 0 DACK , 1 DACK 0 Pin No. TFP-120 FP-128 I Output Low write/lower column address 116 ...
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Section 1 Overview Type Symbol 16-bit timer- TCLKD to pulse unit TCLKA (TPU) TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4 TIOCA5, TIOCB5 Programmable pulse generator PO 0 (PPG) 8-bit timer ...
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Type Symbol WDTOVF Watchdog timer (WDT) Serial TxD , 2 communication TxD , 1 interface (SCI) TxD 0 Smart Card RxD , 2 interface RxD , 1 RxD 0 SCK , 2 SCK 1 SCK 0 A/D converter AN to ...
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Section 1 Overview Type Symbol I/O ports ...
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Type Symbol I/O ports Pin No. TFP-120 FP-128 I 39 45, I 80, 88, I/O ...
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Section 1 Overview Rev. 5.00 Sep 14, 2006 page 22 of 1060 REJ09B0331-0500 ...
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Overview The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear ...
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Section 2 CPU High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate: 8/16/32-bit register-register add/subtract 8-bit register-register multiply: 16 ÷ 8-bit register-register divide: 16 16-bit register-register multiply: 32 ÷ 16-bit register-register divide: ...
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Higher speed Basic instructions execute twice as fast. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements. Additional control register One 8-bit and two 32-bit control registers have been added. Enhanced ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area ...
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Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 2.2). The exception vector table differs depending ...
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Section 2 CPU Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are ...
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Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and ...
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Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception ...
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Address Space Figure 2.6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 ...
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Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ...
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General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can ...
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Section 2 CPU SP (ER7) 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC). (1) Program Counter (PC) This 24-bit counter indicates the ...
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Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. (3) Condition-Code Register (CCR) ...
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Section 2 CPU Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to appendix A.1, Instruction List. Operations can be performed on the CCR bits by the ...
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Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. The ...
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Section 2 CPU Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General ...
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Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made to ...
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Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV POP * , PUSH * 1 ...
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Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Function Instruction Data MOV BWL BWL BWL BWL BWL BWL transfer ...
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Section 2 CPU Function Instruction Branch Bcc, BSR — JMP, JSR — RTS — System TRAPA — control RTE — SLEEP — LDC B STC — ANDC, ORC, B XORC NOP — Block data transfer — Legend: B: Byte W: ...
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Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation General register (destination General register (source General register * ...
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Section 2 CPU Table 2.3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH LDM STM Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 5.00 Sep 14, 2006 page ...
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Type Instruction Arithmetic ADD operations SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS DIVXU Note: * Size refers to the operand size. B: Byte W: Word L: Longword Size * Function B/W/L Rd ± Rs Rd, Rd ...
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Section 2 CPU Type Instruction Arithmetic DIVXS operations CMP NEG EXTU EXTS TAS MAC CLRMAC LDMAC STMAC Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 5.00 Sep 14, 2006 page 46 of 1060 ...
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Type Instruction Logic AND operations OR XOR NOT Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Size refers to the operand size. B: Byte W: Word L: Longword Size * Function B/W Rd, Rd ...
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Section 2 CPU Type Instruction Bit- BSET manipulation instructions BCLR BNOT BTST BAND BIAND BOR BIOR Note: * Size refers to the operand size. B: Byte Rev. 5.00 Sep 14, 2006 page 48 of 1060 REJ09B0331-0500 Size * Function B ...
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Type Instruction Bit- BXOR manipulation instructions BIXOR BLD BILD BST BIST Note: * Size refers to the operand size. B: Byte Size * Function B C (<bit-No.> of <EAd>) Exclusive-ORs the carry flag with a specified bit in a general ...
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Section 2 CPU Type Instruction Branch Bcc instructions JMP BSR JSR RTS Rev. 5.00 Sep 14, 2006 page 50 of 1060 REJ09B0331-0500 Size * Function — Branches to a specified address if a specified condition is true. The branching conditions ...
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Type Instruction System TRAPA control RTE instructions SLEEP LDC STC ANDC ORC XORC NOP Note: * Size refers to the operand size. B: Byte W: Word Size * Function — Starts trap-instruction exception handling. — Returns from an exception-handling routine. ...
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Section 2 CPU Type Instruction Block data EEPMOV.B transfer instruction EEPMOV.W 2.6.4 Basic Instruction Formats The H8S/2655 Group instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective ...
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Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension op (4) Operation field, effective address extension, and condition field op cc Figure 2.12 Instruction Formats (Examples ...
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Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the ...
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Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of ...
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Section 2 CPU Table 2.5 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction 24 bits (@aa:24) address (6) Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), ...
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Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Specified Branch address by @aa:8 (a) Normal Mode Figure 2.13 Branch Address Specification in Memory Indirect ...
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Section 2 CPU Table 2.6 Effective Address Calculation Rev. 5.00 Sep 14, 2006 page 58 of 1060 REJ09B0331-0500 ...
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Section 2 CPU Rev. 5.00 Sep 14, 2006 page 60 of 1060 REJ09B0331-0500 ...
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Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state ...
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Section 2 CPU End of bus request Bus-released state End of exception handling Exception-handling state RES = high Reset state * 1 From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. ...
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Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table ...
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Section 2 CPU (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start ...
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Normal mode SP CCR CCR * PC (16 bits) (a) Interrupt control modes 0 and 1 Advanced mode SP CCR PC (24 bits) (c) Interrupt control modes 0 and 1 Note: * Ignored when returning. Figure 2.16 Stack Structure after ...
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Section 2 CPU 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. ...
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Basic Timing 2.9.1 Overview The H8S/2600 CPU is driven by a system clock, denoted by the symbol . The period from one rising edge of to the next is referred “state.” The memory cycle or bus ...
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Section 2 CPU Address bus AS RD HWR, LWR Data bus Figure 2.18 Pin States during On-Chip Memory Access Rev. 5.00 Sep 14, 2006 page 68 of 1060 REJ09B0331-0500 Bus cycle T1 Unchanged High High High High-impedance state ...
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On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the access ...
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Section 2 CPU Address bus AS RD HWR, LWR Data bus Figure 2.20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8S/2655 Group has seven operating modes (modes 1 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width ...
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Section 3 MCU Operating Modes The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If ...
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Register Descriptions 3.2.1 Mode Control Register (MDCR) 7 Bit : — Initial value : 1 R/W : — Note: * Determined by pins MD MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2655 ...
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Section 3 MCU Operating Modes Bit 7 MACS Description 0 Non-saturating calculation for MAC instruction 1 Saturating calculation for MAC instruction Bit 6—Reserved: Read-only bit, always read as 0. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): ...
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Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled, and 8-bit bus mode is set, immediately after a reset. Ports B and C function as an ...
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Section 3 MCU Operating Modes The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches ...
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Pin Functions in Each Operating Mode The pin functions of ports vary depending on the operating mode. Table 3.3 shows their functions in each operating mode. Table 3.3 Pin Functions in Each Mode Port Mode 1 ...
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Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'EC00 On-chip RAM * H'FBFF H'FC00 External address space H'FE3F Internal I/O registers H'FF08 External address space H'FF28 Internal I/O registers H'FFFF ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFEC00 On-chip RAM * 3 H'FFFBFF External address H'FFFC00 space H'FFFE3F Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. ...
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Section 3 MCU Operating Modes Rev. 5.00 Sep 14, 2006 page 80 of 1060 REJ09B0331-0500 ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. ...
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Table 4.2 Exception Vector Table Exception Source Power-on reset Manual reset Reserved for system use Trace Reserved for system use External interrupt NMI Trap instruction (4 sources) Reserved for system use External interrupt IRQ 0 IRQ 1 IRQ 2 IRQ ...
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Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2655 Group enters the reset state. A reset initializes the internal state of the ...
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Reset Sequence The H8S/2655 Group enters the reset state when the RES pin goes low. To ensure that the H8S/2655 Group is reset, hold the RES pin low for at least power-up. To reset the H8S/2655 ...
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Section 4 Exception Handling RES Address bus RD HWR, LWR (1) (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) ...
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Traces Traces are enabled in interrupt control modes 2 and 3. Trace mode is not activated in interrupt control modes 0 and 1, irrespective of the state of the T bit. For details of interrupt control modes, see section ...
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Section 4 Exception Handling 4.4 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ 52 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and the number of interrupts of each type. ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table ...
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Section 4 Exception Handling 4.6 Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP CCR CCR * PC (16 bits) (a) Interrupt control modes 0 and 1 ...
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Notes on Use of the Stack When accessing word data or longword data, the H8S/2655 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and ...
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Section 4 Exception Handling Rev. 5.00 Sep 14, 2006 page 92 of 1060 REJ09B0331-0500 ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The H8S/2655 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features: Four interrupt control modes Any of four interrupt control modes can be set by ...
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Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISCR Internal interrupt request WOVI to TEI ...
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Table 5.1 Interrupt Controller Pins Name Symbol Nonmaskable interrupt NMI IRQ External interrupt requests 5.1.4 Register Configuration Table 5.2 summarizes the registers of the interrupt controller. Table 5.2 Interrupt Controller Registers Name System control register IRQ sense ...
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Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : 7 MACS Initial value : 0 R/W : R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for ...
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Interrupt Control Registers (ICRA to ICRC) Bit : 7 ICR7 ICR6 Initial value : 0 R/W : R/W R/W The ICR registers are three 8-bit readable/writable registers that set the interrupt control level for interrupts other ...
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Section 5 Interrupt Controller Bits 7 and 3—Reserved: Read-only bits, always read as 0. Table 5.4 Correspondence between Interrupt Sources and IPR Settings Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK As shown in table 5.4, ...
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IRQ Enable Register (IER) IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ to IRQ . 7 0 Bit : 7 IRQ7E IRQ6E Initial value : 0 R/W R/W R/W : IER is ...
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Section 5 Interrupt Controller The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ The ISCR registers are initialized to H'0000 by a reset ...
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Bits 7 to 0—IRQ to IRQ flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ 7 0 IRQ interrupt requests. 0 Bit n IRQnF Description 0 [Clearing conditions] Cleared by reading IRQnF flag when IRQnF = 1, then ...
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Section 5 Interrupt Controller 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ used to restore the H8S/2655 Group from software standby mode. NMI Interrupt NMI ...
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IRQnSCA, IRQnSCB Edge/level detection circuit IRQ input n Note Figure 5.2 Block Diagram of Interrupts IRQ Figure 5.3 shows the timing of setting IRQnF. IRQ n input pin IRQnF Figure 5.3 Timing of Setting IRQnF The ...
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Section 5 Interrupt Controller 5.3.2 Internal Interrupts There are 52 sources for internal interrupts from on-chip supporting modules. For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling ...
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Table 5.5 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Interrupt Source Source NMI External pin IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 SWDTEND (software DTC activation interrupt end) ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Source Source Reserved — TGI1A (TGR1A input TPU capture/compare match) channel 1 TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input TPU capture/compare match) channel 2 TGI2B ...
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Origin of Interrupt Interrupt Source Source TGI5A (TGR5A input TPU capture/compare match) channel 5 TGI5B (TGR5B input capture/compare match) TCI5V (overflow 5) TCI5U (underflow 5) CMIA0 (compare match A0) 8-bit timer channel 0 CMIB0 (compare match B0) OVI0 (overflow 0) ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Source Source ERI1 (receive error 1) SCI channel 1 85 RXI1 (reception completed 1) TXI1 (transmit data empty 1) TEI1 (transmission end 1) ERI2 (receive error 2) SCI channel 2 89 RXI2 ...
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Table 5.6 Interrupt Control Modes SYSCR Interrupt Control Mode INTM1 INTM0 Figure 5.4 shows a block diagram of the priority decision circuit. ICR Interrupt acceptance Interrupt control and source 3-level ...
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Section 5 Interrupt Controller (1) Interrupt Acceptance Control and 3-Level Control In interrupt control modes 0, 1, and 3, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR, and ICR ...
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Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR and ICR, acceptance of multiple interrupts is enabled, and so ...
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Section 5 Interrupt Controller 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR, and ICR. Interrupts are enabled when the ...
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Program execution status Interrupt generated? Yes Control level 1 interrupt? Yes No IRQ 0 No Yes IRQ 1 Yes TEI2 Yes Save PC and CCR Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to ...
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Section 5 Interrupt Controller 5.4.3 Interrupt Control Mode 1 Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by means of the I and UI bits in the CPU’s CCR, and ICR. Control level 0 interrupt requests ...
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If an interrupt source occurs when the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, ...
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Section 5 Interrupt Controller Control level 1 interrupt? No IRQ 0 Yes IRQ Figure 5.7 Flowchart of Procedure Up to Interrupt Acceptance in Rev. 5.00 Sep 14, 2006 page 116 of 1060 REJ09B0331-0500 Program execution status Interrupt ...
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Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits EXR in the CPU with IPR. Figure 5.8 shows a ...
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Section 5 Interrupt Controller Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5.8 Flowchart of Procedure Up to Interrupt Acceptance in Rev. 5.00 Sep 14, 2006 page 118 of 1060 REJ09B0331-0500 Program execution status No Interrupt generated? ...
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Interrupt Control Mode 3 Control of IRQ interrupts and on-chip supporting module interrupts is performed by a combination of interrupt masking set by the I and UI bits and control level setting by ICR, based on 8-level interrupt mask ...
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Section 5 Interrupt Controller [ interrupt source occurs when the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, it ...
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Highest-priority selection Priority level > mask level? Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in 5.4.6 Interrupt Exception Handling Sequence Figure 5.11 shows the interrupt exception handling sequence. The example shown is for the case ...
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Section 5 Interrupt Controller Figure 5.11 Interrupt Exception Handling Rev. 5.00 Sep 14, 2006 page 122 of 1060 REJ09B0331-0500 ...
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Interrupt Response Times The H8S/2655 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high- speed processing. Table 5.10 shows ...
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Section 5 Interrupt Controller 5.5 Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an ...
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The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.5.2 Instructions That Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any ...
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Section 5 Interrupt Controller 5.6 DTC and DMAC Activation by Interrupt 5.6.1 Overview The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: Interrupt request to CPU Activation request to DTC Activation ...
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Operation The interrupt controller has three main functions in DTC and DMAC control. (1) Selection of Interrupt Source With the DMAC, the activation source is input directly to each channel. The activation source for each DMAC channel is selected ...
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Section 5 Interrupt Controller Table 5.12 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTA bit of DMABCR in the DMAC, the DTCE bit of DTCEA to DTCEF in the DTC and the ...
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Section 6 Bus Controller 6.1 Overview The H8S/2655 Group has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set ...
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Section 6 Bus Controller Choice of auto-refreshing or self-refreshing Burst ROM interface Burst ROM interface can be set for area 0 Choice 2-state burst access Idle cycle insertion An idle cycle can be inserted in case of ...
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Block Diagram Figure 6.1 shows a block diagram of the bus controller External bus control signals BREQ BACK BREQO WAIT External DRAM/ PSRAM control signals Figure 6.1 Block Diagram of Bus Controller Area decoder ...
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Section 6 Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Bus Controller Pins Name Address strobe Read High write/write enable/upper write enable Low write/lower column address strobe/lower write enable Chip select 0 ...
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Name Chip select 5/row address strobe 5 Chip select 6 Chip select 7 Upper column address strobe/ column address strobe/output enable/refresh Lower column strobe Wait Bus request Bus request acknowledge Bus request output * Using the LCASS bit in BCRL, ...
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Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the registers of the bus controller. Table 6.2 Bus Controller Registers Name Bus width control register Access state control register Wait control register H Wait control register L Bus control ...
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Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) Bit : 7 ABW7 ABW6 Modes Initial value : R/W Mode 4 Initial value : R/W ABWCR is an ...
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Section 6 Bus Controller 6.2.2 Access State Control Register (ASTCR) Bit : 7 AST7 AST6 Initial value : 1 R/W : R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a ...
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Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. In normal mode, only part of area enabled, and bits ...
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Section 6 Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is ...
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WCRL Bit : 7 W31 Initial value : 1 R/W : R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space ...
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Section 6 Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is ...
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Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 Description 0 Idle cycle not inserted ...
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Section 6 Bus Controller Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access 1 Max. 8 ...
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Bus Control Register L (BCRL) Bit : 7 BRLE BREQOE Initial value : 0 R/W : R/W BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, the area partition unit, the LCAS signal, ...
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Section 6 Bus Controller Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF are to be internal addresses or external addresses. This setting is invalid in normal mode. Bit 5 EAE Description 0 Addresses H'010000 to H'01FFFF are ...
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Bit 2—Area Partition Unit Select (ASS): Selects the area partition unit. Bit 2 ASS Description 0 Area partition unit is 128 kbytes (1 Mbit) 1 Area partition unit is 2 Mbytes (16 Mbits) Bit 1—Write Data Buffer Enable (WDBE): Selects ...
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Section 6 Bus Controller MCR is initialized to H' power-on reset and in hardware standby mode not initialized by a manual reset or in software standby mode. Bit 7—TP Cycle Control (TPC): Selects whether a 1-state ...
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Bit 4—2-CAS Method/2-WE Method Select (CW2): Selects whether the 2-CAS method method is used for byte access when areas are designated as 16-bit DRAM space. Bit 4 CW2 Description 2-CAS method selected: CASH, CASL, ...
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Section 6 Bus Controller Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This setting is used for all ...
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Bit 6—RAS-CAS Wait (RCW): Controls wait state insertion in DRAM interface CAS-before- RAS refreshing. In case of the PSRAM interface, the value of this bit should be kept at 0. Bit 6 RCW Description 0 Wait state insertion in CAS-before-RAS ...
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Section 6 Bus Controller Bit 3—Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag in DRAMCR is set to 1. When refresh control is performed (RFSHE = 1), the CMIE ...
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Refresh Timer/Counter (RTCNT) Bit : 7 Initial value : 0 R/W : R/W RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits CKS2 to CKS0 in DRAMCR. When RTCNT matches RTCOR (compare ...
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Section 6 Bus Controller 6.3 Overview of Bus Control 6.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas 128-kbyte or 2-Mbyte units, and performs bus control for ...
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Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are ...
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Section 6 Bus Controller Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH, WCRL ABWn ASTn Wn1 0 0 — — 6.3.3 Memory Interfaces The H8S/2655 Group memory ...
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Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on ...
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Section 6 Bus Controller Area 7 Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the ...
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Chip Select Signals The H8S/2655 Group can output chip select signals (CS driven low when the corresponding external space area is accessed. In normal mode, only the CS signal can be output. Figure 6.3 shows an example of CS ...
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Section 6 Bus Controller 6.4 Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data ...
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Access Space Figure 6.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D 15 amount of data that can be accessed at one time is one byte or one ...
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Section 6 Bus Controller 6.4.3 Valid Strobes Table 6.4 shows the data buses used and valid strobes for the access spaces read, the RD signal is valid without discrimination between the upper and lower halves of the data ...
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Basic Timing 8-Bit 2-State Access Space Figure 6.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half ( The LWR pin is fixed high. Wait ...
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Section 6 Bus Controller 8-Bit 3-State Access Space Figure 6.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half ( The LWR pin is fixed high. ...
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Access Space Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D 15 half ( for the odd address ...
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Section 6 Bus Controller Address bus Read HWR LWR Write Note Figure 6.9 Bus Timing for ...
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Address bus Read HWR LWR Write Note Figure 6.10 Bus Timing ...
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Section 6 Bus Controller 16-Bit 3-State Access Space Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed, the upper half (D lower half ( for the ...
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Address bus Read HWR LWR Write Note Figure 6.12 Bus Timing ...
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Section 6 Bus Controller Address bus Read HWR LWR Write Note ...
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Wait Control When accessing external space, the H8S/2655 Group can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: program wait insertion and pin w wait insertion ...
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Section 6 Bus Controller WAIT Address bus AS RD Read Data bus HWR, LWR Write Data bus indicates the timing of WAIT pin sampling. Note: Figure 6.14 Example of Wait State Insertion Timing The settings after a power-on reset are: ...
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DRAM Interface 6.5.1 Overview When the H8S/2655 Group is in advanced mode, external space areas can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the ...
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Section 6 Bus Controller 6.5.3 Address Multiplexing With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table ...