M38504E6FP Renesas Electronics Corporation., M38504E6FP Datasheet
M38504E6FP
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M38504E6FP Summary of contents
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REJ09B0080-0103Z 8 RENESAS 8-BIT CISC SINGLE-CHIP MICROCOMPUTER Before using this material, please visit our website to confirm that this is the most current document available. Rev. 1.03 Revision date: Sep. 18, 2003 3850 Group (Spec. H) User's Manual 740 FAMILY ...
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Keep safety first in your circuit designs! Renesas Technology Corporation puts the maximum effort into making semiconductor prod- • ucts better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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REVISION HISTORY Rev. Date Page 1.0 – First edition issued Aug. 30, 2001 1.1 3-5 Limits and test conditions into Table 3.1.5 are partly added. Sep. 10, 2001 1.02 1-6 Fig partly revised. Aug. 29, 2003 1-7 Table ...
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Preface This user’s manual describes Renesas’s CMOS 8-bit microcomputers 3850 Group (Spec. H). After reading this manual, the user should have a through knowledge of the functions and features of the 3850 Group (Spec. H), and should be able to ...
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BEFORE USING THIS MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. Chapter 3 also includes necessary information for systems development. You must refer ...
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Table of contents CHAPTER 1 HARDWARE DESCRIPTION ................................................................................................................................ 1-2 FEATURES .................................................................................................................................... 1-2 APPLICATION ................................................................................................................................ 1-2 PIN CONFIGURATION .................................................................................................................. 1-2 FUNCTIONAL BLOCK .................................................................................................................. 1-3 PIN DESCRIPTION ........................................................................................................................ 1-4 PART NUMBERING ....................................................................................................................... 1-5 GROUP EXPANSION .................................................................................................................... 1-6 Memory Type ............................................................................................................................ 1-6 Memory ...
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Table of contents 2.3 Timer ....................................................................................................................................... 2-20 2.3.1 Memory map ................................................................................................................. 2-20 2.3.2 Relevant registers ........................................................................................................ 2-20 2.3.3 Timer application examples ........................................................................................ 2-27 2.3.4 Notes on timer .............................................................................................................. 2-39 2.4 Serial I/O ................................................................................................................................ 2-40 2.4.1 Memory map ................................................................................................................. 2-40 2.4.2 ...
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Electrical characteristics ................................................................................................ 3-4 3.1.4 A-D converter characteristics ....................................................................................... 3-6 3.1.5 Timing requirements and switching characteristics ................................................... 3-7 3.2 Standard characteristics .................................................................................................... 3-11 3.2.1 Flash memory version power source current standard characteristics ................ 3-11 3.2.2 Mask ROM version power ...
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List of figures CHAPTER 1 HARDWARE Fig. 1 M38503MXH-XXXFP/SP pin configuration ...................................................................... 1-2 Fig. 2 Functional block diagram ................................................................................................... 1-3 Fig. 3 Part numbering .................................................................................................................... 1-5 Fig. 4 Memory expansion plan ..................................................................................................... 1-6 Fig. 5 740 Family CPU register structure ...
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Fig. 46 CPU rewrite mode set/reset flowchart ......................................................................... 1-42 Fig. 47 Program flowchart ........................................................................................................... 1-44 Fig. 48 Erase flowchart ............................................................................................................... 1-44 Fig. 49 Full status check flowchart and remedial procedure for errors ............................... 1-46 Fig. 50 ROM code protect control ...
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List of figures Fig. 2.2.14 Sequence of check of interrupt request bit .......................................................... 2-19 Fig. 2.3.1 Memory map of registers relevant to timers .......................................................... 2-20 Fig. 2.3.2 Structure of Prescaler 12, Prescaler X, Prescaler Y ............................................ 2-20 Fig. 2.3.3 Structure ...
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Fig. 2.4.28 Control procedure of Serial I/O1 ............................................................................ 2-58 Fig. 2.4.29 Registers setting relevant to Serial I/O2 .............................................................. 2-59 Fig. 2.4.30 Setting of serial I/O2 transmission data ............................................................... 2-59 Fig. 2.4.31 Control procedure of Serial I/O2 ............................................................................ 2-60 Fig. 2.4.32 ...
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List of figures Fig. 2.10.4 Reset input time ..................................................................................................... 2-101 Fig. 2.11.1 Memory map of flash memory version for 3850 Group ................................... 2-103 Fig. 2.11.2 Memory map of registers relevant to flash memory ......................................... 2-104 Fig. 2.11.3 Structure of Flash ...
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Fig. 3.2.23 CMOS large current output port N-channel side characteristics ( °C) . 3-23 Fig. 3.2.24 CMOS output port P-channel side characteristics ( °C) ....................... 3-24 Fig. 3.2.25 CMOS output port N-channel side characteristics (Ta = ...
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List of figures Fig. 3.5.23 Structure of MISRG ................................................................................................. 3-61 Fig. 3.5.24 Structure of Watchdog timer control register ....................................................... 3-62 Fig. 3.5.25 Structure of Interrupt edge selection register ...................................................... 3-62 Fig. 3.5.26 Structure of CPU mode register ............................................................................ 3-63 Fig. ...
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List of tables CHAPTER 1 HARDWARE Table 1 Pin description ................................................................................................................. 1-4 Table 2 Support products ............................................................................................................. 1-7 Table 3 3850 group (standard) and 3850 group (spec. H) corresponding products ............ 1-7 Table 4 Differences between 3850 group (standard) and ...
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List of tables CHAPTER 3 APPENDIX Table 3.1.1 Absolute maximum ratings ....................................................................................... 3-2 Table 3.1.2 Recommended operating conditions (1) ................................................................ 3-3 Table 3.1.3 Recommended operating conditions (2) ................................................................ 3-4 Table 3.1.4 Electrical characteristics (1) ..................................................................................... 3-4 Table 3.1.5 Electrical characteristics ...
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HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING NOTES ON USAGE DATA REQUIRED FOR MASK ORDERS DATA REQUIRED FOR One Time ...
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HARDWARE DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION DESCRIPTION The 3850 group (spec the 8-bit microcomputer based on the 740 family core technology. The 3850 group (spec designed for the household products and office automation equipment and includes serial I/O functions, ...
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FUNCTIONAL BLOCK Fig. 2 Functional block diagram 3850 Group (Spec. H) User’s Manual HARDWARE FUNCTIONAL BLOCK 1-3 ...
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HARDWARE PIN DESCRIPTION PIN DESCRIPTION Table 1 Pin description Pin Name Power source CNV CNV input SS SS Reset input RESET X Clock input IN X Clock output OUT IN2 P0 /S ...
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PART NUMBERING Product name M3850 Fig. 3 Part numbering H– XXX SP Package type SP : 42P4B FP : 42P2R-A 42S1B-A ROM number Omitted in One Time PROM version shipped in blank, EPROM version, and ...
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HARDWARE GROUP EXPANSION GROUP EXPANSION Renesas Technology plans to expand the 3850 group (spec follows. Memory Type Support for mask ROM, One Time PROM, and flash memory ver- sions. Memory Size Flash memory size ......................................................... 32 K bytes ...
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... H) M38503M2-XXXFP/SP M38503M2H-XXXFP/SP M38503M4-XXXFP/SP M38503M4H-XXXFP/SP M38503E4-XXXFP/SP M38504M6-XXXFP/SP M38503E4FP/SP M38504E6-XXXFP/SP M38503E4SS M38504E6FP/SP M38504E6SS M38507M8-XXXFP/SP M38507F8FP/SP Table 4 Differences between 3850 group (standard) and 3850 group (spec. H) Serial I/O 1: Serial I/O (UART or Clock-synchronized) A-D converter Unserviceable in low-speed mode Large current port 5: P1 – ...
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HARDWARE FUNCTIONAL DESCRIPTION FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3850 group (spec. H) uses the standard 740 Family instruc- tion set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual ...
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HARDWARE FUNCTIONAL DESCRIPTION [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions ...
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Mode Register (CPUM)] 003B The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B b 7 Fig. 7 Structure of CPU mode register CPU mode ...
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HARDWARE FUNCTIONAL DESCRIPTION MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine ...
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HARDWARE FUNCTIONAL DESCRIPTION I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input ...
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HARDWARE FUNCTIONAL DESCRIPTION (9) Port P2 4 Serial I/O1 enable bit Receive enable bit Direction register Port latch Data bus Serial I/O1 input (11) Port P2 6 Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode ...
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Port P4 4 PWM output enable bit Direction register Port latch Data bus PWM output Interrupt input Fig. 12 Port block diagram (3) 3850 Group (Spec. H) User’s Manual HARDWARE FUNCTIONAL DESCRIPTION 1-17 ...
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HARDWARE FUNCTIONAL DESCRIPTION INTERRUPTS Interrupts occur by 15 sources among 15 sources: six external, eight internal, and one software. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except ...
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Table 8 Interrupt vector addresses and priority Vector Addresses (Note 1) Interrupt Source Priority High Reset (Note 2) 1 FFFD INT 0 2 FFFB FFF9 Reserved 3 INT 1 4 FFF7 INT 5 FFF5 2 INT / Serial I/O2 3 ...
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HARDWARE FUNCTIONAL DESCRIPTION Interrupt request bit Interrupt enable bit Fig. 13 Interrupt control ...
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TIMERS The 3850 group (spec. H) has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding ...
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HARDWARE FUNCTIONAL DESCRIPTION ...
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SERIAL I/O SERIAL I/O1 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation CLK1 BRG count ...
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HARDWARE FUNCTIONAL DESCRIPTION (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data transfer formats ...
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Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output Receive buffer read signal ST Serial input Notes 1: Error flag detection occurs at the same time that the RBF ...
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HARDWARE FUNCTIONAL DESCRIPTION ...
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SERIAL I/O2 The serial I/O2 can be operated only as the clock synchronous type synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection bit (b6) of ...
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HARDWARE FUNCTIONAL DESCRIPTION ...
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S CMP2 S CLK2 S OUT2 S IN2 Fig output operation CMP2 Judgement of I/O data comparison 3850 Group (Spec. H) User’s Manual HARDWARE FUNCTIONAL DESCRIPTION 1-29 ...
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HARDWARE FUNCTIONAL DESCRIPTION PULSE WIDTH MODULATION (PWM) The 3850 group (spec. H) has a PWM function with an 8-bit resolution, based on a signal that is the clock input X clock input divided by 2. Data Setting The PWM output ...
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HARDWARE FUNCTIONAL DESCRIPTION A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 0035 , 0036 16 16 The A-D conversion registers are read-only registers that store the result of an A-D conversion. Do not read these registers during an A-D conversion. [AD ...
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WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). The watchdog timer consists of an 8-bit watchdog timer ...
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HARDWARE FUNCTIONAL DESCRIPTION RESET CIRCUIT To reset the microcomputer, RESET pin must be held at an “L” level for 20 cycles or more Then the RESET pin is returned “H” level (the power source ...
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Port P0 (P0) (2) Port P0 direction register (P0D) (3) Port P1 (P1) (4) Port P1 direction register (P1D) (5) Port P2 (P2) (6) Port P2 direction register (P2D) (7) Port P3 (P3) (8) Port P3 direction register (P3D) ...
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HARDWARE FUNCTIONAL DESCRIPTION CLOCK GENERATING CIRCUIT The 3850 group (spec. H) has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator be- tween X and X (X and X IN OUT CIN COUT in accordance ...
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MISRG consists of three control bits (bits for middle-speed mode automatic switch and one control bit (bit 0) for oscillation stabilizing time set after STP instruction released. By setting the middle-speed mode automatic ...
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HARDWARE FUNCTIONAL DESCRIPTION Reset MHz) 6 “ 1 ” ...
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FLASH MEMORY VERSION Summary Table 9 shows the summary of the M38507F8 (flash memory version). Table 9 Summary of M38507F8 (flash memory version ...
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HARDWARE FUNCTIONAL DESCRIPTION Flash Memory Mode The M38507F8 (flash memory version) has an internal new DINOR (DIvided bit line NOR) flash memory that can be rewritten with a single power source when and 2 power sources ...
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CPU Rewrite Mode In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the user ROM area shown in Figure 44 ...
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HARDWARE FUNCTIONAL DESCRIPTION ...
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Software Commands Table 10 lists the software commands. After setting the CPU rewrite mode select bit to “1”, write a software command to specify an erase or program operation. The content of each software command is explained below. Read Array ...
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HARDWARE FUNCTIONAL DESCRIPTION Program Command ( Program operation starts when the command code “40 in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming ...
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Status Register The status register shows the operating state of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways. (1) By reading an arbitrary address from the ...
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HARDWARE FUNCTIONAL DESCRIPTION Full Status Check By performing full status check possible to know the execution results of erase and program operations. Figure 49 shows a full sta- Read status register YES SR4=1 and SR5 = ...
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Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a ROM code protect function for use in parallel I/O mode and an ID ...
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HARDWARE FUNCTIONAL DESCRIPTION ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the peripheral unit is compared with the ID code written ...
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Parallel I/O Mode The parallel I/O mode is entered by making connections shown in Figure 52 and then turning the Vcc power supply on. Address The user ROM is only one block as shown in Figure 44. The block address ...
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HARDWARE FUNCTIONAL DESCRIPTION Table 13 Description of Pin Function (Flash Memory Parallel I/O Mode ...
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P4 /INT /PWM /INT / RY/BY P4 /CNTR /CNTR / /SCL /SDA 4 ...
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HARDWARE FUNCTIONAL DESCRIPTION Software Commands Table 14 lists the software commands. By entering a software com- mand from the data I/O pins (D – Write mode, specify the con tent of the operation, such as erase ...
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Program Command ( The program operation starts when the command code “40 ten in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data program- ming ...
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HARDWARE FUNCTIONAL DESCRIPTION Status Register The status register indicates status such as whether an erase opera- tion or a program ended successfully or in error. It can be read under the following conditions. (1) In the read array mode when ...
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Read status register YES SR4=1 and SR5 = Block erase error SR5=0? YES NO SR4=0? YES End (block erase, program) Note: When one of SR5 to SR4 is set to “1” , none of the program, all ...
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HARDWARE FUNCTIONAL DESCRIPTION Standard serial I/O mode The standard serial I/O mode inputs and outputs the software com- mands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This ...
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Table 16 Pin functions (Flash memory standard serial I/O mode) Pin Name V ,V Power input CC SS CNV CNV SS SS Reset input RESET X Clock input IN X Clock output OUT AV Analog power supply input SS V ...
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HARDWARE FUNCTIONAL DESCRIPTION P4 /INT /INT /CNTR 0 B USY P2 /CNTR CLK1 6 P2 TxD RxD CNV PP P2 ...
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Software Commands Table 17 lists software commands. In the standard serial I/O mode, erase operations, programs and reading are controlled by transfer- ring software commands via the RxD pin. Software commands are Table 17 Software commands (Standard serial I/O mode ...
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HARDWARE FUNCTIONAL DESCRIPTION Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the “FF ” command code ...
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Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the “41 ” command code with the 1st ...
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HARDWARE FUNCTIONAL DESCRIPTION Download Command This command downloads a program to the RAM for execution. Ex- ecute the download command as explained here following. (1) Transfer the “FA ” command code with the 1st byte. 16 (2) Transfer the program ...
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ID Check This command checks the ID code. Execute the boot ID check com- mand as explained here following. (1) Transfer the “F5 ” command code with the 1st byte. 16 (2) Transfer addresses ...
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HARDWARE FUNCTIONAL DESCRIPTION Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read ...
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Full Status Check Results from executed erase and program operations can be known ...
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HARDWARE FUNCTIONAL DESCRIPTION Flash memory Electrical characteristics Table 20 Absolute maximum ratings Symbol Parameter V Power source voltage CC Input voltage P0 – – REF V Input voltage ...
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AC Electrical characteristics o ( 4.5 to 5.5V unless otherwise noted) CC Table 22 Read-only mode Symbol t Read cycle time RC ta Address access time (AD) _____ CE access time ta (CE) _____ ta ...
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HARDWARE FUNCTIONAL DESCRIPTION Flash memory mode Electrical characteristics o ( 4.5 to 5.5V unless otherwise noted) CC _____ Table 24 Read / Write mode (CE control) Symbol t Write cycle time WC t Address set ...
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Inhibit read / write 5. GND t VCS Fig power up / power down timing CC Inhibit read / write t ...
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HARDWARE FUNCTIONAL DESCRIPTION V IH Address HIGH-Z DATA Fig wave for read ...
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V IH Address DATA 40H RY/ ...
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HARDWARE FUNCTIONAL DESCRIPTION V IH Address DATA RY/ ...
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NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags which affect program execution. In ...
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HARDWARE DATA REQUIRED FOR MASK ORDERS/DATA REQUIRED FOR One Time PROM PROGRAMMING ORDERS/ROM PROGRAMMING METHOD DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: 1. Mask ROM Order Confirmation Form 2. Mark Specification ...
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FUNCTIONAL DESCRIPTION SUPPLEMENT A-D Converter A-D conversion is started by setting AD conversion completion bit to “0”. During A-D conversion, internal operations are performed as follows. 1. After the start of A-D conversion, A-D conversion register goes to “00 ”. ...
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HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT Figures 76 shows the A-D conversion equivalent circuit, and Figure 77 shows the A-D conversion timing chart. About REF AV SS Fig. ...
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APPLICATION 2.1 I/O port 2.2 Interrupt 2.3 Timer 2.4 Serial I/O 2.5 PWM 2.6 A-D converter 2.7 Watchdog timer 2.8 Reset 2.9 Clock generating circuit 2.10 Standby function 2.11 Flash memory mode ...
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APPLICATION 2.1 I/O port 2.1 I/O port This paragraph describes the setting method of I/O port relevant registers, notes etc. 2.1.1 Memory map Address 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 Fig. 2.1.1 Memory map of I/O ...
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Port Pi direction register Fig. 2.1.3 Structure of Port Pi direction register ( 2.1.3 Terminate unused pins Table 2.1.1 Termination of unused pins Pins/Ports name • ...
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APPLICATION 2.1 I/O port 2.1.4 Notes on I/O port (1) Notes in standby state 1 In standby state , do not make input levels of an I/O port “undefined”, especially for I/O ports of the N-channel open-drain. When setting the ...
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Termination of unused pins (1) Terminate unused pins Output ports : Open Input ports : Connect each pin for pins whose potential affects to operation modes such as pins CNV the V pin or the V ...
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APPLICATION 2.2 Interrupt 2.2 Interrupt This paragraph explains the registers setting method and the notes relevant to the interrupt. 2.2.1 Memory map 003A 16 003C 16 003D 16 003E 16 003F 16 Fig. 2.2.1 Memory map of registers relevant to ...
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Relevant registers Interrupt edge selection register Fig. 2.2.2 Structure of Interrupt edge selection register Interrupt edge selection register (INTEDGE: address Name Functions INT active edge 0: Falling ...
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APPLICATION 2.2 Interrupt Interrupt request register Fig. 2.2.3 Structure of Interrupt request register 1 Interrupt request register Fig. 2.2.4 Structure of Interrupt ...
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Interrupt control register Fig. 2.2.5 Structure of Interrupt control register 1 Interrupt control register Fig. 2.2.6 Structure of Interrupt ...
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APPLICATION 2.2 Interrupt 2.2.3 Interrupt source The 3850 group permits interrupts of 15 sources. These are vector interrupts with a fixed priority system. Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted ...
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Interrupt operation When an interrupt request is accepted, the contents of the following registers just before acceptance of the interrupt requests are automatically pushed onto the stack area in the order of High-order contents of program counter (PC Low-order ...
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APPLICATION 2.2 Interrupt (1) Processing upon acceptance of interrupt request Upon acceptance of an interrupt request, the following operations are automatically performed. The processing being executed is stopped. The contents of the program counter and the processor status register are ...
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Timing after acceptance of interrupt request The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently being executed. Figure 2.2.9 shows the time up to execution of interrupt processing routine and ...
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APPLICATION 2.2 Interrupt 2.2.5 Interrupt control The acceptance of all interrupts, excluding the BRK instruction interrupt, can be controlled by the interrupt request bit, interrupt enable bit, and an interrupt disable flag, as described in detail below. Figure 2.2.11 shows ...
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Interrupt disable flag The interrupt disable flag is allocated to bit 2 of the processor status register. The interrupt disable flag controls the acceptance of interrupt request except BRK instruction. When this flag is “1”, the acceptance of interrupt ...
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APPLICATION 2.2 Interrupt ...
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INT interrupt The INT interrupt requests is generated when the microcomputer detects a level change of each INT pin (INT –INT ). 0 3 (1) Active edge selection INT –INT can be selected from either a falling edge or ...
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APPLICATION 2.2 Interrupt 2.2.7 Notes on interrupts (1) Change of relevant register settings When the setting of the following registers or bits is changed, the interrupt request bit may be set to “1”. When not requiring the interrupt occurrence synchronized ...
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Check of interrupt request bit When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to “0” by using a data transfer instruction, execute one or ...
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APPLICATION 2.3 Timer 2.3 Timer This paragraph explains the registers setting method and the notes relevant to the timers. 2.3.1 Memory map Address 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 ...
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Timer Fig. 2.3.3 Structure of Timer 1 Timer Fig. 2.3.4 Structure of Timer 2 Timer 1 (T1: address ...
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APPLICATION 2.3 Timer Timer X, Timer Fig. 2.3.5 Structure of Timer X, Timer Y 2-22 Timer X, Timer Y (TX, TY: addresses Functions 0 ...
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Timer XY mode register Fig. 2.3.6 Structure of Timer XY mode register Table 2.3.1 CNTR /CNTR active edge switch bit function 0 1 Timer X /Timer Y Set value operation modes Timer ...
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APPLICATION 2.3 Timer Timer count source selection register Fig. 2.3.7 Structure of Timer count source selection register 2-24 Timer count source selection register (TCSS: address Name Functions 0: ...
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Interrupt request register Fig. 2.3.8 Structure of Interrupt request register 1 Interrupt request register Fig. 2.3.9 Structure of Interrupt request register 2 ...
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APPLICATION 2.3 Timer Interrupt control register Fig. 2.3.10 Structure of Interrupt control register 1 Interrupt control register Fig. 2.3.11 Structure ...
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Timer application examples (1) Basic functions and uses [Function 1] Control of Event interval (Timer X, Timer Y, Timer 1, Timer 2) When a certain time, by setting a count value to each timer, has passed, the timer interrupt ...
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APPLICATION 2.3 Timer (2) Timer application example 1: Clock function (measurement of 250 ms) Outline: The input clock is divided by the timer so that the clock can count up at 250 ms intervals. Specifications: •The clock f(X •The clock ...
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SEI IREQ1 ( ...
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APPLICATION 2.3 Timer (3) Timer application example 2: Piezoelectric buzzer output Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer output. Specifications: •The rectangular waveform, dividing the clock f(X 2 kHz (2048 Hz), is ...
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APPLICATION 2.3 Timer ...
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Timer application example 3: Frequency measurement Outline: The following two values are compared to judge whether the frequency is within a valid range. •A value by counting pulses input to P4 •A reference value Specifications: •Clock f(X •The pulse ...
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APPLICATION 2.3 Timer ...
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APPLICATION 2.3 Timer (5) Timer application example 4: Measurement of FG pulse width for motor Outline: The timer X counts the “H” level width of the pulses input to the CNTR is detected by the timer X interrupt and an ...
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...
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APPLICATION 2.3 Timer RESET ...
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Notes on timer If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). When switching the count source by the timer 12, X and Y count source selection bits, ...
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APPLICATION 2.4 Serial I/O 2.4 Serial I/O This paragraph explains the registers setting method and the notes relevant to the Serial I/O. 2.4.1 Memory map Address 0015 0016 0017 0018 0019 001A 001B 001C 003A 003C 003D 003E 003F Fig. ...
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Relevant registers Serial I/O2 control register Fig. 2.4.2 Structure of Serial I/O2 control register 1 Serial I/O2 control register Fig. 2.4.3 ...
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APPLICATION 2.4 Serial I/O Serial I/O2 register Fig. 2.4.4 Structure of Serial I/O2 register Transmit/Receive buffer register Fig. 2.4.5 Structure of Transmit/Receive buffer register ...
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Serial I/O1 status register Fig. 2.4.6 Structure of Serial I/O1 status register Serial I/O1 status register (SIOSTS: address 19 b Name Functions Transmit buffer 0: Buffer full 0 empty flag (TBE) 1: ...
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APPLICATION 2.4 Serial I/O Serial I/O1 control register Fig. 2.4.7 Structure of Serial I/O1 control register UART control register Fig. 2.4.8 Structure of UART ...
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Baud rate generator Fig. 2.4.9 Structure of Baud rate generator Interrupt edge selection register Fig. 2.4.10 Structure of Interrupt edge selection register Baud rate ...
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APPLICATION 2.4 Serial I/O Interrupt request register Fig. 2.4.11 Structure of Interrupt request register 1 Interrupt request register Fig. 2.4.12 Structure of ...
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Interrupt control register Fig. 2.4.13 Structure of Interrupt control register 1 Interrupt control register Fig. 2.4.14 Structure of Interrupt ...
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APPLICATION 2.4 Serial I/O 2.4.3 Serial I/O connection examples (1) Control of peripheral IC equipped with CS pin Figure 2.4.15 shows connection examples of a peripheral IC equipped with the CS pin. There are connection examples using a clock synchronous ...
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Connection with microcomputer Figure 2.4.16 shows connection examples with another microcomputer. (1) Selecting internal clock S CLK1 3850 group (3) Using signal output function S RDY1 (Selecting an external clock) S RDY1 S ...
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APPLICATION 2.4 Serial I/O 2.4.4 Setting of serial I/O transfer data format A clock synchronous or clock asynchronous (UART) can be selected as a data format of Serial I/O1. A clock synchronous is used as a data format of Serial ...
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Serial I/O application examples (1) Communication using clock synchronous serial I/O (transmit/receive) Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O. The S signal is used for communication control. RDY1 Figure 2.4.18 shows a ...
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APPLICATION 2.4 Serial I ...
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APPLICATION 2.4 Serial I/O Figure 2.4.22 shows a control procedure of the transmitting side, and Figure 2.4.23 shows a control procedure of the receiving side Initialization ( ...
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RESET SIOCON (Address : 1A Pass 2 ms ...
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APPLICATION 2.4 Serial I/O (2) Output of serial data (control of peripheral IC) Outline : 4-byte data is transmitted and received, using the clock synchronous serial I/O. The CS signal is output to a peripheral IC through port P4 Figure ...
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Figure 2.4.26 shows registers setting relevant to Serial I/O1, and Figure 2.4.27 shows a setting of serial I/O1 transmission data ...
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APPLICATION 2.4 Serial I/O Example for using Serial I/O1 When the registers are set as shown in Figure 2.4.26, the Serial I/O1 can transmit 1-byte data by writing data to the transmit buffer register. Thus, after setting the CS signal ...
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Figure 2.4.29 shows registers setting relevant to Serial I/O2, and Figure 2.4.30 shows a setting of serial I/O2 transmission data ...
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APPLICATION 2.4 Serial I/O Example for using Sreial I/O2 When the registers are set as shown in Fig. 2.4.29, the Serial I/O2 can transmit 1-byte data by writing data to the serial I/O2 register. Thus, after setting the CS signal ...
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Cyclic transmission or reception of block data (data of specified number of bytes) between two microcomputers Outline : When the clock synchronous serial I/O is used for communication, synchronization of the clock and the data between the transmitting and ...
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APPLICATION 2.4 Serial I/O The communication is performed according to the timing shown in Figure 2.4.33. In the slave unit, when a synchronous clock is not input within a certain time (heading adjustment time), the next clock input is processed ...
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Control procedure : Control in the master unit After setting the relevant registers shown in Figure 2.4.34, the master unit starts transmission or reception of 1-byte data by writing transmission data to the transmit buffer register. To perform the communication ...
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APPLICATION 2.4 Serial I/O Control in the slave unit After setting the relevant registers as shown in Figure 2.4.34, the slave unit becomes the state where a synchronous clock can be received at any time, and the serial I/O receive ...
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Communication (transmit/receive) using asynchronous serial I/O (UART) Outline : 2-byte data is transmitted and received, using the asynchronous serial I/O. Port P4 is used for communication control. 0 Figure 2.4.37 shows a connection diagram, and Figure 2.4.38 shows a ...
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APPLICATION 2.4 Serial I/O Table 2.4.1 and Table 2.4.2 show setting examples of the baud rate generator (BRG) values and transfer bit rate values; Figure 2.4.39 shows registers setting relevant to the transmitting side; Figure 2.4.40 shows registers setting relevant ...
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APPLICATION 2.4 Serial I ...
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Figure 2.4.41 shows a control procedure of the transmitting side, and Figure 2.4.42 shows a control procedure of the receiving side Initialization ...
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APPLICATION 2.4 Serial I ...
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Notes on serial I/O (1) Notes when selecting clock synchronous serial I/O (Serial I/O1) Stop of transmission operation Clear the serial I/O1 enable bit and the transmit enable bit to “0” (Serial I/O1 and transmit disabled). Reason Since transmission ...
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APPLICATION 2.4 Serial I/O (2) Notes when selecting clock asynchronous serial I/O (Serial I/O1) Stop of transmission operation Clear the transmit enable bit to “0” (transmit disabled). Reason Since transmission is not stopped and the transmission circuit is not initialized ...
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Data transmission control with referring to transmit shift register completion flag (Serial I/O1) The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with ...
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APPLICATION 2.5 PWM 2.5 PWM This paragraph explains the registers setting method and the notes relevant to the PWM. 2.5.1 Memory map Address 001D 16 001E 16 001F 16 Fig. 2.5.1 Memory map of registers relevant to PWM 2.5.2 Relevant ...
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PWM prescaler Fig. 2.5.3 Structure of PWM prescaler PWM register Fig. 2.5.4 Structure of PWM register PWM prescaler (PREPWM: address ...
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APPLICATION 2.5 PWM 2.5.3 PWM output circuit application example <Motor control> Outline : The rotation speed of the motor is controlled by using PWM (pulse width modulation) output. Figure 2.5.5 shows a connection diagram ; Figures 2.5.6 shows PWM output ...
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APPLICATION 2.5 PWM Control procedure : By setting the related registers as shown by Figure 2.5.7, PWM waveforms are output to the externals. This PWM output is integrated through the low pass filter, and that converted into DC signals is ...
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A-D converter This paragraph explains the registers setting method and the notes relevant to the A-D converter. 2.6.1 Memory map Address 0034 16 0035 16 0036 16 003D 16 003F 16 Fig. 2.6.1 Memory map of registers relevant to ...
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APPLICATION 2.6 A-D converter A-D conversion register (high-order Fig. 2.6.3 Structure of A-D conversion register (high-order) A-D conversion register (low-order Fig. 2.6.4 Structure of ...
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Interrupt request register Fig. 2.6.5 Structure of Interrupt request register 2 Interrupt control register Fig. 2.6.6 Structure of Interrupt control register ...
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APPLICATION 2.6 A-D converter 2.6.3 A-D converter application examples (1) Conversion of analog input voltage Outline : The analog input voltage input from a sensor is converted to digital values. Figure 2.6.7 shows a connection diagram, and Figure 2.6.8 shows ...
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An analog input signal from a sensor is converted to the digital value according to the relevant registers setting shown by Figure 2.6.8. Figure 2.6.9 shows the control procedure for 8-bit read, and Figure 2.6.10 shows the control procedure for ...
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APPLICATION 2.6 A-D converter 2.6.4 Notes on A-D converter (1) Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0. Further, be ...
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Watchdog timer This paragraph explains the registers setting method and the notes relevant to the watchdog timer. 2.7.1 Memory map Address 0039 003B Fig. 2.7.1 Memory map of registers relevant to watchdog timer 2.7.2 Relevant registers Watchdog timer control ...
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APPLICATION 2.7 Watchdog timer CPU mode register Fig. 2.7.3 Structure of CPU mode register 2-86 CPU mode register (CPUM: address Name Functions Processor mode ...
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Watchdog timer application examples (1) Detection of program runaway Outline: If program runaway occurs, let the microcomputer reset, using the internal timer for detection of program runaway. Specifications: •An underflow of watchdog timer H is judged to be program ...
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APPLICATION 2.7 Watchdog timer ...
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Reset 2.8.1 Connection example of reset IC Power source M62022L Fig. 2.8.1 Example of poweron reset circuit Figure 2.8.2 shows the system example which switches to the RAM backup mode by detecting a drop of the system power source ...
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APPLICATION 2.8 Reset 2.8.2 Notes on RESET pin (1) Connecting capacitor In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the V connecting the capacitor, note the following ...
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Clock generating circuit This paragraph explains how to set the registers relevant to the clock generating circuit and describes an application example. 2.9.1 Relevant registers CPU mode register Fig. 2.9.1 ...
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APPLICATION 2.9 Clock generating circuit 2.9.2 Clock generating circuit application example (1) Status transition during power failure Outline: The clock counts up every second by using the timer interrupt during a power failure. Fig. 2.9.2 Connection diagram Specifications: •Reducing power ...
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CPU mode register (address 3B b7 CPUM 0 0 CPU mode register (address 3B b7 CPUM 0 0 (Note 2) CPU mode register (address 3B b7 CPUM 1 0 CPU mode register (address 3B b7 CPUM 1 0 Notes 1: ...
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APPLICATION 2.9 Clock generating circuit Control procedure: To prepare for a power failure, set the relevant registers in the order shown below. RESET ...
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Standby function The 3850 group is provided with standby functions to stop the CPU by software and put the CPU into the low-power operation. The following two types of standby functions are available. •Stop mode using STP instruction •Wait ...
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APPLICATION 2.10 Standby function 2.10.2 Stop mode The stop mode is set by executing the STP instruction. In the stop mode, the oscillation of both clocks (X – –X ) stop and the internal clock IN OUT CIN ...
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Release of stop mode The stop mode is released by a reset input or by the occurrence of an interrupt request. Note the differences in the restoration process according to reset input or interrupt request, as described below. Restoration ...
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APPLICATION 2.10 Standby function Restoration by interrupt request The occurrence of an interrupt request in the stop mode releases the stop mode result, oscillation is resumed. The interrupts available for restoration are: •INT –INT 0 3 •CNTR , ...
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When restoring microcomputer from stop mode by INT CIN (System clock) INT pin 0 Prescaler 12 counter Timer 1 counter INT interrupt request bit 0 Peripheral device Operating CPU Operating Execute STP instruction Note: f(X Fig. ...
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APPLICATION 2.10 Standby function 2.10.3 Wait mode The wait mode is set by execution of the WIT instruction. In the wait mode, oscillation continues, but the internal clock stops at the “H” level. The CPU stops, but most of the ...
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Release of wait mode The wait mode is released by reset input or by the occurrence of an interrupt request. Note the differences in the restoration process according to reset input or interrupt request, as described below. In the ...
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APPLICATION 2.10 Standby function Restoration by interrupt request In the wait mode, the occurrence of an interrupt request releases the wait mode and supply of the internal clock to the CPU is started. At the same time, the interrupt request ...
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Flash memory mode This paragraph explains the registers setting method and the notes relevant to the flash memory version. 2.11.1 Overview The functions of the flash memory version are similar to those of the mask ROM version except that ...
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APPLICATION 2.11 Flash memory mode 2.11.3 Relevant registers Address 0FFE 16 Fig. 2.11.2 Memory map of registers relevant to flash memory Flash memory control register Fig. 2.11.3 Structure of Flash memory control ...
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Parallel I/O mode In the parallel I/O mode, program/erase to the built-in flash memory can be performed by a EPROM programmer (EFP-I). The memory area of program/erase is from 0F000 0FFFF (user ROM area). Be especially careful when erasing; ...
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APPLICATION 2.11 Flash memory mode 2.11.6 CPU rewrite mode In the CPU rewrite mode, issuing software commands through the Central Processing Unit (CPU) can rewrite the built-in flash memory. Accordingly, the contents of the built-in flash memory can be rewritten ...