HM5212165FTD-A60 Renesas Electronics Corporation., HM5212165FTD-A60 Datasheet
HM5212165FTD-A60
Related parts for HM5212165FTD-A60
HM5212165FTD-A60 Summary of contents
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HM5212165F-75/A60/B60 HM5212805F-75/A60/B60 128M LVTTL interface SDRAM 2-Mword 16-bit 4-bank/4-Mword 8-bit 4-bank PC/133, PC/100 SDRAM Description The Hitachi HM5212165F is a 128-Mbit SDRAM organized as 2097152-word Hitachi HM5212805F is a 128-Mbit SDRAM organized as 4194304-word outputs are referred to the rising ...
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... HM5212165F/HM5212805F-75/A60/B60 2 variations of refresh Auto refresh Self refresh Full page burst length capability Sequential burst Burst stop capability Ordering Information Type No. Frequency 1 HM5212165FTD-75* 133 MHz HM5212165FTD-A60 100 MHz 2 HM5212165FTD-B60* 100 MHz 1 HM5212165FLTD-75* 133 MHz HM5212165FLTD-A60 100 MHz 2 HM5212165FLTD-B60* 100 MHz 1 HM5212805FTD-75* ...
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Pin Arrangement (HM5212165F) Pin Description Pin name Function A0 to A13 Address input Row address Column address Bank select address A12/A13 (BS) V DQ0 to DQ15 Data-input/output CS Chip select RAS Row address strobe command CAS Column address strobe command ...
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HM5212165F/HM5212805F-75/A60/B60 Pin Arrangement (HM5212805F) Pin Description Pin name Function A0 to A13 Address input Row address Column address Bank select address A12/A13 (BS) V DQ0 to DQ7 Data-input/output CS Chip select RAS Row address strobe command CAS Column address strobe ...
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Block Diagram (HM5212165F) Column address counter Row decoder Memory array Bank0 4096 row 512 column 8 bit Memory array Bank0 4096 row 512 column 8 bit Row decoder Column address counter HM5212165F/HM5212805F-75/A60/B60 A0 to A13 A0 to A13 A0 to ...
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HM5212165F/HM5212805F-75/A60/B60 Block Diagram (HM5212805F) Column address counter Row decoder Memory array Bank0 4096 row 1024 column 4 bit Memory array Bank0 4096 row 1024 column 4 bit Row decoder Column address counter A13 A0 to A13 A0 ...
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Pin Functions CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is ...
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HM5212165F/HM5212805F-75/A60/B60 Command Operation Command Truth Table The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins. Command Ignore command No operation Burst stop in full page Column address and read command READ Read with ...
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Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY8; HM5212165F, AY0 to AY9; HM5212805F) and the bank select address (A12/A13) become the burst ...
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HM5212165F/HM5212805F-75/A60/B60 DQM Truth Table (HM5212165F) Command Upper byte (DQ8 to DQ15) write enable/output enable ENBU Lower byte (DQ0 to DQ7) write enable/output enable Upper byte (DQ8 to DQ15) write inhibit/output disable MASKU Lower byte (DQ0 to DQ7) write inhibit/output disable ...
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CKE Truth Table Current state Command Active Clock suspend mode entry Any Clock suspend Clock suspend Clock suspend mode exit Idle Auto-refresh command (REF) Idle Self-refresh entry (SELF) Idle Power down entry Self refresh Self refresh exit (SELFX) Power down ...
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HM5212165F/HM5212805F-75/A60/B60 Self-refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM starts self- refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self- refresh is performed internally and automatically, external ...
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CS RAS CAS WE Current state Row active Read ...
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HM5212165F/HM5212805F-75/A60/B60 CS RAS CAS WE Current state Write Write with auto- H precharge L H ...
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From PRECHARGE state, command operation To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM enters the IDLE state after t has elapsed from the completion of precharge. RP From IDLE state, command operation To [DESL], [NOP], [BST], ...
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HM5212165F/HM5212805F-75/A60/B60 From READ with AUTO-PRECHARGE state, command operation To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the SDRAM then enters precharge mode. To [ACTV]: This command makes other banks bank active. (However, an ...
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Simplified State Diagram MODE REGISTER (on full page) Write CKE_ WRITE SUSPEND CKE WRITE WITH AP CKE_ WRITEA SUSPEND CKE POWER POWER APPLIED ON Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh ...
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HM5212165F/HM5212805F-75/A60/B60 Mode Register Configuration The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A13, ...
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Burst Sequence Burst length = 2 Starting Ad. Addressing(decimal) A0 Sequential Burst length = 8 Starting Ad. Addressing(decimal Sequential ...
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HM5212165F/HM5212805F-75/A60/B60 Operation of the SDRAM Read/Write Operations Bank active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank ...
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Burst Length CLK t RCD Command ACTV READ Address Row Column out out 0 out Dout out 0 out 1 out 2 out out 0 out 1 out ...
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HM5212165F/HM5212805F-75/A60/B60 2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0 single write operation, data is only written to the column address (AY0 to AY8; HM5212165F, AY0 to AY9; HM5212805F) and ...
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Write with auto-precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after the ...
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HM5212165F/HM5212805F-75/A60/B60 Full-page Burst Stop Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. ...
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Burst stop command at burst write: The burst stop command (BST command) is used to stop data input during a full-page burst write. No data is written in the same clock as the BST command, and in subsequent clocks. In ...
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HM5212165F/HM5212805F-75/A60/B60 Command Intervals Read command to Read command interval: 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can ...
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Write command to Write command interval: 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an ...
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HM5212165F/HM5212805F-75/A60/B60 Read command to Write command interval: 1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after ...
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Write command to Read command interval: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an ...
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HM5212165F/HM5212805F-75/A60/B60 Read with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. Even when the first read with auto-precharge is a burst read that ...
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Read with auto precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. However, DQM, DQMU/DQML must be set High so that the output buffer becomes ...
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HM5212165F/HM5212805F-75/A60/B60 Write with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. However,in case of a burst write, data will continue to be written ...
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Read command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output buffer ...
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HM5212165F/HM5212805F-75/A60/B60 READ to PRECHARGE Command Interval (same bank): To stop output data CAS Latency = 2, Burst Length = full page burst CLK READ Command PRE/PALL Dout CAS Latency = 3, Burst Length = 1, 2, ...
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Write command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write ...
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HM5212165F/HM5212805F-75/A60/B60 Bank active command interval: 1. Same bank: The interval between the two bank-active commands must be no less than the case of different bank-active commands: The interval between the two bank-active commands must be no less ...
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Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than l CLK Command MRS Address CODE Mode Register Set DQM Control The DQM mask the DQ ...
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HM5212165F/HM5212805F-75/A60/B60 Reading CLK DQM, DQMU/DQML DQ (output) Writing CLK DQM, DQMU/DQML DQ (input) 38 High-Z out 0 out Latency DOD Latency DID out ...
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Refresh Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the auto- refresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address ...
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HM5212165F/HM5212805F-75/A60/B60 Power up sequence CKE, DQM, Low DQMU/DQML Low CLK Low CS, DQ Power stabilize Absolute Maximum Ratings Parameter Voltage on any pin relative Supply voltage relative to V ...
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V /V Clamp IL IH clamp for CLK, CKE, CS, DQM and DQ pins. This SDRAM has V and Minimum V Clamp Current IL V (V) IL –2 –1.8 –1.6 –1.4 –1.2 –1 –0.9 –0.8 –0.6 –0.4 ...
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HM5212165F/HM5212805F-75/A60/B60 Minimum V Clamp Current (referred ( 0.8 CC ...
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I /I Characteristics OL OH Output Low Current ( Vout (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3 3.45 250 200 150 100 0.5 HM5212165F/HM5212805F-75/A60/B60 Min (mA) Max ...
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HM5212165F/HM5212805F-75/A60/B60 Output High Current ( +70˚ Vout (V) 3.45 3.3 3 2.6 2.4 2 1.8 1.65 1.5 1 0.5 –100 –200 –300 –400 –500 –600 ...
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DC Characteristics ( +70˚C, V (HM5212165F) HM5212165F -75 Parameter Symbol Min Operating current (CAS latency = 2) I — CC1 (CAS latency = 3) I — CC1 Standby current in I — CC2P power down Standby current ...
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HM5212165F/HM5212805F-75/A60/B60 DC Characteristics ( +70˚C, V (HM5212805F) HM5212805F -75 Parameter Symbol Min Operating current (CAS latency = 2) I — CC1 (CAS latency = 3) I — CC1 Standby current in I — CC2P power down Standby ...
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Notes depends on output load condition when the device is selected output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. ...
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HM5212165F/HM5212805F-75/A60/B60 AC Characteristics ( +70˚C, V HITACHI Parameter Symbol System clock cycle time (CAS latency = (CAS latency = CLK high pulse width t CKH CLK low pulse width t CKL ...
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Notes measurement assumes t 2. Access time is measured at 1.5 V. Load condition pF (min) defines the time at which the outputs achieves the low impedance state (max) ...
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HM5212165F/HM5212805F-75/A60/B60 Relationship Between Frequency and Minimum Latency Parameter Frequency (MHz) t (ns) CK Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same ...
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Parameter Frequency (MHz) t (ns command disable Power down exit to command input Burst stop to output valid data hold (CAS latency = 2) (CAS latency = 3) Burst stop to output high impedance (CAS latency = ...
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HM5212165F/HM5212805F-75/A60/B60 Timing Waveforms Read Cycle CKH CKL CLK V IH CKE t RCD RAS CAS t t ...
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Write Cycle CKH CKL CLK V IH CKE t RCD RAS CAS ...
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HM5212165F/HM5212805F-75/A60/B60 Mode Register Set Cycle CLK V CKE IH CS RAS CAS WE BS Address valid code DQM, DQMU/DQML DQ (output) DQ (input) l RSA l RP Precharge Mode If needed register Set Read Cycle/Write Cycle ...
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Read/Single Write Cycle CLK V CKE IH CS RAS CAS WE BS Address R:a C:a DQM, DQMU/DQML DQ (input) DQ (output) Bank 0 Bank 0 Active Read CKE RAS CAS WE BS R:a ...
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HM5212165F/HM5212805F-75/A60/B60 Read/Burst Write Cycle CLK CKE CS RAS CAS WE BS Address R:a C:a DQM, DQMU/DQML DQ (input) DQ (output) Bank 0 Bank 0 Active Read V CKE IH CS RAS CAS WE BS R:a C:a ...
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Full Page Read/Write Cycle CLK V CKE IH CS RAS CAS WE BS Address R:a C:a R:b DQM, DQMU/DQML DQ (output) DQ (input) Bank 0 Bank 0 Bank 3 Active Read Active V CKE IH CS RAS CAS WE BS ...
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HM5212165F/HM5212805F-75/A60/B60 Auto Refresh Cycle CLK CKE RAS CAS WE BS Address A10=1 DQM, DQMU/DQML DQ (input) DQ (output Auto Refresh Precharge If needed Self Refresh Cycle CLK CKE Low CKE ...
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Clock Suspend Mode t CES CLK CKE CS RAS CAS WE BS Address R:a DQM, DQMU/DQML DQ (output) DQ (input) Bank0 Active clock Active clock Active suspend start suspend end CKE CS RAS CAS ...
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HM5212165F/HM5212805F-75/A60/B60 Power Down Mode CLK CKE CS RAS CAS WE BS Address A10=1 DQM, DQMU/DQML DQ (input) DQ (output Precharge command If needed Initialization Sequence CLK CKE RAS CAS WE Address valid ...
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... Package Dimensions HM5212165FTD/HM5212805FTD Series/ HM5212165FLTD/HM5212805FLTD Series (TTP-54DA) 22.22 22.72 Max 54 1 0.80 + 0.10 *0.30 – 0.05 0.13 M 0.28 0.05 0.91 Max 0.10 *Dimension including the plating thickness Base material dimension HM5212165F/HM5212805F-75/A60/B60 28 27 11.76 0.20 0 – 5 Hitachi Code JEDEC EIAJ Weight (reference value) Unit: mm 0.80 0.50 0.10 TTP-54DA — — 0. ...
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HM5212165F/HM5212805F-75/A60/B60 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may ...
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Revision Record Rev. Date Contents of Modification 0.0 May. 17, 1999 Initial issue 1.0 Jan. 31, 2000 Deletion of preliminary CKE Truth table Clock suspend mode entry CS Addition of description to clock suspend mode entry HM5212165F/HM5212805F-75/A60/B60 Drawn ...